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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:53 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 01/12] spi: dt-bindings: introduce the ``fifo-depth`` property Date: Thu, 8 Feb 2024 13:50:34 +0000 Message-ID: <20240208135045.3728927-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339036438560155 X-GMAIL-MSGID: 1790339036438560155 There are instances of the same IP that are configured by the integrator with different FIFO depths. Introduce the fifo-depth property to allow such nodes to specify their FIFO depth. We haven't seen SPI IPs with different FIFO depths for RX and TX, thus introduce a single property. Signed-off-by: Tudor Ambarus Reviewed-by: Conor Dooley --- Documentation/devicetree/bindings/spi/spi-controller.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/spi-controller.yaml b/Documentation/devicetree/bindings/spi/spi-controller.yaml index 524f6fe8c27b..99272e6f115e 100644 --- a/Documentation/devicetree/bindings/spi/spi-controller.yaml +++ b/Documentation/devicetree/bindings/spi/spi-controller.yaml @@ -69,6 +69,11 @@ properties: Should be generally avoided and be replaced by spi-cs-high + ACTIVE_HIGH. + fifo-depth: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Size of the data FIFO in bytes. + num-cs: $ref: /schemas/types.yaml#/definitions/uint32 description: From patchwork Thu Feb 8 13:50:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198417 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179260dyd; Thu, 8 Feb 2024 05:52:52 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXKKdzlPYvzJ4zS0r5InFcsw/Zm2MwFalvpjA4YkIScXhsXZCiivmqsBjscN4qZr+XPU2A1K5TOrvbxky1vCtRiLKmSCQ== X-Google-Smtp-Source: AGHT+IHsv3yLemz3cBBmJxPhSEXh+IPn/B+qdEkT/+fH/D7UxH/rp2CNhuLNbncfc1yHmDqe6aOE X-Received: by 2002:a05:6a00:1e19:b0:6e0:3361:523b with SMTP id gx25-20020a056a001e1900b006e03361523bmr4713269pfb.29.1707400371981; Thu, 08 Feb 2024 05:52:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400371; cv=pass; d=google.com; s=arc-20160816; b=MdWmtYKHewAiMfY0+6Lpo8PNHijiOYOafXEh7sB/iGF8n84tc/1Sr5O9SGF1cEXASm U9KWkNTtS98wiYVjBYkRsNXexg6NiJWc81NDXAVjLzGzPJuYAcAqNjc03KgVc/rTq7Oy F+x+mMULBeLl9B1NkVZRDKsUle+see/KOi7F27BTa7tuudKsdSbIM31uA1aJhRKyqnO4 Kh41eFeEca6rPISD/Ah9AWjJ48R69YxiOSiUSq4rcJYAi3d5DBpQYtHJooa4t0tWud1W j7GREsBP8T2zcrIm6vuD2bSaIq8026wmt0Z5FJufvNHgw/baUTSyboRbbSlRldcAP/J9 K5SA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=/YEBZ5QgPmZi1uvEzjonJi8xfKR7wdfW/zkTSEaERIc=; fh=vuWsakXLbTavTIT2tJPZT20eZbuHf0ICiSFrWOAHf5M=; b=JCT4A9FoHFUBKO7tC23tlCBnsq6ZqG3osWzTI2/vyC9DDKRLXFA0Y5SeWE1ZVF1W7E r6DS5be+YzP4GkaQGJ9LE/N2h2WH0jAOWLXwPlTkjngNoaSiPZl2s+IG3wvNRR9ol1zL cUoSulF1F6uTTsjzFnVJ6l5doRBlNtxuKMR6iBIMzRPy1BNViLKd5NgpgG9RljChdG/M A5utu9EIwy5rvnk8H6CMwOLUPJIbUpmqN5p+IEZqR6N+PAOn/qO+O5DpIkWOLd44oIpQ TzXKzHe1sqf5+2ak3l/675SMiEW1Qed+Cx3BXzKWYmujpDstM0JRiZQ72pXZoXZLTqOP YNAw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hvMXUvZt; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58177-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58177-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCUxbNhW4arHswW1BY0Xs7KFGM467w1E3ec2+ekSf2L7xFeAOy1Tcil8VcZYbf6dhT3DrlAgQCS64yNA+1L90qXZtY/WOw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:53 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 02/12] spi: s3c64xx: define a magic value Date: Thu, 8 Feb 2024 13:50:35 +0000 Message-ID: <20240208135045.3728927-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339052224166423 X-GMAIL-MSGID: 1790339052224166423 Define a magic value, it will be used in the next patch as well. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6f29dca68491..6ff3b25b6feb 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -78,6 +78,7 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) @@ -108,7 +109,8 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ + FIFO_LVL_MASK(i)) #define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ FIFO_LVL_MASK(i)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) From patchwork Thu Feb 8 13:50:36 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198420 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179440dyd; Thu, 8 Feb 2024 05:53:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IGoAa6wTnGWQySoIsEnNLlc791g60rMH6AHiqYonk+osCb5Du28ELpdsOyiTDWJB7NBo/Ja X-Received: by 2002:a05:6a21:8184:b0:19e:a3b9:1e0f with SMTP id pd4-20020a056a21818400b0019ea3b91e0fmr3611236pzb.11.1707400392791; Thu, 08 Feb 2024 05:53:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400392; cv=pass; d=google.com; s=arc-20160816; b=Y4ylNxIxRWTebsZxFpSh1N+E6hYcrtcnhL0H032JY7nXu40cN8CPE6bHcVtUK7gFk+ 3ryRx8twlDa6EEJl1hb2lYdHMwn2sZgPv2VK3UvvcxTj78VhFIRjRwdRTV+h9/mQM6nx On+MTCx83lrdPPNmammq0FRbJcLPi+bbRwHi4DUZLqpMmVCOR1+muoTUT6K+IzgkrhLE KhsepZw7pdzsXf8L/SoJS7bM4J3MACQ7EPUWyiln0/MlgIAAmi8+QXWsvyDRpb9AcCt4 EFOOCJZZkcs0p0tiZ+h3Ef8dbC7N6WRPZngHnr4bJzXQPq9k4tqHfKFz+BdO8wBMAHjU IYSA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3UCCMmhJgpPZWbOVTAspr0xjn11XvYuA37qXyTRrUkA=; fh=4R9ylH6JgJ4DwyNkWGPDIBm+9is9aE0ToXf1j8S/pqg=; b=nzg4xdZJQ/rDJkfuP/TIb7nrd5coFMmuGvNfD0gnF3KAU/xV7sck5Rz0+JVzyJ7B1q d7JpfWV2LUdU+A9UmSM3GLyoYzhQLF1f4nqt5gq4LKCTpf/PI3CFceHLOEXQQZnAZSJ6 ZumECrE1gZzKWMIlvrEQL/dyz/0A+aoJX3cLkFQHAuC8AoIAmQixjDUMOQuGoorJ8UQb ENn9awKDXiLiJ1BzorUb934X2KpTUyrn6C9436LTh8GJAC5vTVvj9nU96ifXtvQv4bA6 km/jxSAOg4HVOpJzAffNn6POW68+glVUCcUOztrbsSeGAFrorwvj7uNbnq1D4YVZAI5Y dDDQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YcrtGknA; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58178-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58178-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCV+DGDhkUFsfVzR0hJu33KRQiTMO6YQSjKZNRtkaJa41pjyhJ10YRmE29we60Uz4FChtmxXDXB+Xo/zAYFHwMba8CRSIg== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:54 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 03/12] spi: s3c64xx: allow full FIFO masks Date: Thu, 8 Feb 2024 13:50:36 +0000 Message-ID: <20240208135045.3728927-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339074625908168 X-GMAIL-MSGID: 1790339074625908168 The driver is wrong because is using partial register field masks for the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. We see s3c64xx_spi_port_config.fifo_lvl_mask with different values for different instances of the same IP. Take s5pv210_spi_port_config for example, it defines: .fifo_lvl_mask = { 0x1ff, 0x7F }, fifo_lvl_mask is used to determine the FIFO depth of the instance of the IP. In this case, the integrator uses a 256 bytes FIFO for the first SPI instance of the IP, and a 64 bytes FIFO for the second instance. While the first mask reflects the SPI_STATUS.{RX, TX}_FIFO_LVL register fields, the second one is two bits short. Using partial field masks is misleading and can hide problems of the driver's logic. Allow platforms to specify the full FIFO mask, regardless of the FIFO depth. Introduce {rx, tx}_fifomask to represent the SPI_STATUS.{RX, TX}_FIFO_LVL register fields. It's a shifted mask defining the field's length and position. We'll be able to deprecate the use of @rx_lvl_offset, as the shift value can be determined from the mask. The existing compatibles shall start using {rx, tx}_fifomask so that they use the full field mask and to avoid shifting the mask to position, and then shifting it back to zero in the {TX, RX}_FIFO_LVL macros. @rx_lvl_offset will be deprecated in a further patch, after we have the infrastructure to deprecate @fifo_lvl_mask as well. No functional change intended. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 40 +++++++++++++++++++++++++++++++++++---- 1 file changed, 36 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 6ff3b25b6feb..338ca3f03ea5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -3,6 +3,7 @@ // Copyright (c) 2009 Samsung Electronics Co., Ltd. // Jaswinder Singh +#include #include #include #include @@ -109,10 +110,10 @@ #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) -#define TX_FIFO_LVL(v, i) (((v) >> S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT) & \ - FIFO_LVL_MASK(i)) -#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \ - FIFO_LVL_MASK(i)) +#define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ + __ffs((sdd)->tx_fifomask)) +#define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ + __ffs((sdd)->rx_fifomask)) #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff @@ -136,6 +137,10 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. * @clk_div: Internal clock divider * @quirks: Bitmask of known quirks @@ -154,6 +159,8 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + u32 rx_fifomask; + u32 tx_fifomask; int tx_st_done; int quirks; int clk_div; @@ -184,6 +191,10 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. + * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's + * length and position. */ struct s3c64xx_spi_driver_data { void __iomem *regs; @@ -203,6 +214,8 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + u32 rx_fifomask; + u32 tx_fifomask; }; static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) @@ -1183,6 +1196,23 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) +{ + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; + + if (port_conf->rx_fifomask) + sdd->rx_fifomask = port_conf->rx_fifomask; + else + sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << + port_conf->rx_lvl_offset; + + if (port_conf->tx_fifomask) + sdd->tx_fifomask = port_conf->tx_fifomask; + else + sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << + S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; +} + static int s3c64xx_spi_probe(struct platform_device *pdev) { struct resource *mem_res; @@ -1231,6 +1261,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + s3c64xx_spi_set_fifomask(sdd); + sdd->cur_bpw = 8; sdd->tx_dma.direction = DMA_MEM_TO_DEV; From patchwork Thu Feb 8 13:50:37 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198421 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179487dyd; Thu, 8 Feb 2024 05:53:19 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcTYUaC2MBFOvKqi323kmytpWRJ6kBwtKcTTZq+hvOCPCdZ74yR/TOUd8Fb3sdKFuoxcJm X-Received: by 2002:a05:6a00:1d03:b0:6e0:8057:b2aa with SMTP id a3-20020a056a001d0300b006e08057b2aamr167096pfx.28.1707400398823; Thu, 08 Feb 2024 05:53:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400398; cv=pass; d=google.com; s=arc-20160816; b=drbEQpEAiEYUd7ArcFT+p5wAgfdE8gvrD1/w8kl2av6IM2wJwwPRDB6ritRdlvMKCI se9mPFNSAR7lA1I5RBCyVtZ7fR26QTkT5fMvkgy8VismEDMfduDzGVRW/IX66R7aSWV1 Jvfgs37XfNESRdvLKJlnHf6RgruModE+c/uQeDO3oBZ/CfAtjsLl+m6bWP3+eEsmg2Kz wFV+zevqrAsw4elfM6D66haCRZcDXXWKeq/8x3MintTGx4kX9/m7DluX4XylQvgw/h8N I10wXjbD9naJ7TwZue82m8Yxn2ItydaSxHxhnFc+qiBV1oSfsHdh+cXqDzpl7g2WOdqP +I1g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=NGH79biiaV6ew1Z0cXAg/aqisf4dNxuTnwEmj4C4qiQ=; fh=DfbVPRnzE4Gf6hKZu8yqKhO1c51U8xRVKHuHZO+ua48=; b=BvkeWCWYHBfZROVH+4tTLM/fdk/IEy8ywLyBk0tkXVIikfQdDfkGgZPAJIxkhSCcQd ZmgIm5GH1UOpKfHE6lPAPztT/xYiqhZvu9BsvI+/xH+OOGqjle7fDMI+Gg8VkwYesVbk IIoF3b/G0UYCoryb2Mu3M2ZG2zrgX+u1Juddf8s79OvOGbuMS45+NkbTbYmQVG9axWVe hTIkpcftlmUmqagLxn75FyxaCvnDhpx5Ja9CGiQQA+gOXxZM/7pNFPZ5201miKepAJ7Q PwuXZhfxqsi0asGRrn505nonIwoIbRZ41+byaKXRniibkFbOIR9Rk4Qz98oxGt1Zdo/A 7u9g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lh8ZzVZv; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58179-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58179-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWIN4wZwDeCvNM1nlY/+mWKi6QsBLvCbqJIpPZ6s5yf7MOJp6RnnvmsRCLcj4WqYkzFSPhG9hN/WDAfW9KssGlL8EKoMg== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:55 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 04/12] spi: s3c64xx: determine the fifo depth only once Date: Thu, 8 Feb 2024 13:50:37 +0000 Message-ID: <20240208135045.3728927-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339080588282257 X-GMAIL-MSGID: 1790339080588282257 Determine the FIFO depth only once, at probe time. ``sdd->fifo_depth`` can be set later on with the FIFO depth specified in the device tree. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 338ca3f03ea5..72572e23cde5 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -191,6 +191,7 @@ struct s3c64xx_spi_port_config { * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data * @port_id: Port identification number + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -214,6 +215,7 @@ struct s3c64xx_spi_driver_data { struct s3c64xx_spi_dma_data tx_dma; const struct s3c64xx_spi_port_config *port_conf; unsigned int port_id; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; }; @@ -424,7 +426,7 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); if (sdd->rx_dma.ch && sdd->tx_dma.ch) - return xfer->len > FIFO_DEPTH(sdd); + return xfer->len > sdd->fifo_depth; return false; } @@ -548,7 +550,7 @@ static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, void __iomem *regs = sdd->regs; unsigned long val = 1; u32 status; - u32 max_fifo = FIFO_DEPTH(sdd); + u32 max_fifo = sdd->fifo_depth; if (timeout_ms) val = msecs_to_loops(timeout_ms); @@ -655,7 +657,7 @@ static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, * For any size less than the fifo size the below code is * executed atleast once. */ - loops = xfer->len / FIFO_DEPTH(sdd); + loops = xfer->len / sdd->fifo_depth; buf = xfer->rx_buf; do { /* wait for data to be received in the fifo */ @@ -792,7 +794,7 @@ static int s3c64xx_spi_transfer_one(struct spi_controller *host, struct spi_transfer *xfer) { struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); - const unsigned int fifo_len = FIFO_DEPTH(sdd); + const unsigned int fifo_len = sdd->fifo_depth; const void *tx_buf = NULL; void *rx_buf = NULL; int target_len = 0, origin_len = 0; @@ -1261,6 +1263,8 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } + sdd->fifo_depth = FIFO_DEPTH(sdd); + s3c64xx_spi_set_fifomask(sdd); sdd->cur_bpw = 8; @@ -1352,7 +1356,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", sdd->port_id, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", - mem_res, FIFO_DEPTH(sdd)); + mem_res, sdd->fifo_depth); pm_runtime_mark_last_busy(&pdev->dev); pm_runtime_put_autosuspend(&pdev->dev); From patchwork Thu Feb 8 13:50:38 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198418 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179330dyd; Thu, 8 Feb 2024 05:53:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IF7OoRUNK9CGcsjfWcdqjHGwuo/bWKrgHMF1XB+r8NSKwaxWPxzaOaWp6FGBHDkAtUUjJV9 X-Received: by 2002:ac8:5b92:0:b0:42c:b61:ef3c with SMTP id a18-20020ac85b92000000b0042c0b61ef3cmr9818296qta.43.1707400380422; Thu, 08 Feb 2024 05:53:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400380; cv=pass; d=google.com; s=arc-20160816; b=YmzqPvPBS6wbxU+qtt+d8X4G1uZiobNlgkbywvua1quP1ynWhcSlJQyk3tIv3YbxL5 LBYYs392s1QzT2DYBA0SRwBg23+XCk2ZZj4bDwQl/pVBZgzKZ470u+LgEf2Au+vaa14U Yfvg5UV0NeXZGfkrI2v8/vGss3YTJ+oZsT27RrvvMBtzhwsHSdg7btmWcrEgu2TtdAlP oWyb0MxuHq6mCdFgO9rRtj2yFqaA2PxAQu+oNlwLTG8SC1UMTglX2AYtDCHbnRV24i6S GjtlQFjgLmK2YO0HEwb8L4TYQfUznqoOFDp19YxQWm8kvu1b9j7VlvQnP/oQ68xbBRb7 FVLQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=VwdchoB+O7sv0WsEEn/4CtktSHX1kT968ZrMEmEikx8=; fh=ZtGfpbBgwJu92k8A5qO7Nq/6zvaadxupT9nnGXCfMc4=; b=rkciU5A7xKfZpCDkXZg7AeBdST1gXW5jNNBnUk7e462SGSzCfKRpf5gVgyMUedcvz7 Sef+d8mlmSwOWqt0cc/ht8PgxZqdp5wrDQz4TVYu6lxqksP8LkTRYskBYxsuQ10yDXGB u9EfrCobPjxkqa1Ox+wf4FSVJ/fEathiahYmSJPzbVx884L/0CtVParyPi0t2XZd9rsu u+z/G1tJeohOviasDjZTHJ/F5VBpXwIwnY3ArlI8zTx6bAHJm7BqTtWASqJDhRQ1y0Rt zKyHU+Xo47JFFm0VBwdpS5naFHhmiOkkbk6pkml8VDHtKXIriYidX2WS5rBOjyYMv3NC XTvA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CfU4L5YR; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58180-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58180-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCVoJP+UhDSFUNxxuc+M6agC0s01JtfQho4MRwmOei6RdaZK4sZX/8FVeM54FyoSOXcj7uhlYwrMmv5bRfM/mnY3kQsgiA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:56 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 05/12] spi: s3c64xx: retrieve the FIFO depth from the device tree Date: Thu, 8 Feb 2024 13:50:38 +0000 Message-ID: <20240208135045.3728927-6-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339060997324378 X-GMAIL-MSGID: 1790339060997324378 There are SoCs that configure different FIFO depths for their instances of the SPI IP. See the fifo_lvl_mask defined for exynos4_spi_port_config for example: .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, The first instance of the IP is configured with 256 bytes FIFOs, whereas the last two are configured with 64 bytes FIFOs. Instead of mangling with the .fifo_lvl_mask and its dependency of the DT alias ID, allow such SoCs to determine the FIFO depth via the ``fifo-depth`` DT property. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 72572e23cde5..b1c63f75021d 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1263,7 +1263,9 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - sdd->fifo_depth = FIFO_DEPTH(sdd); + if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) + sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Thu Feb 8 13:50:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198419 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179382dyd; Thu, 8 Feb 2024 05:53:06 -0800 (PST) X-Google-Smtp-Source: AGHT+IEuX6bZfGl+6Y3+XPlIfoI13Ghlc9XC4GTc3BmPnpL7tfP7nUjLCJWbCgFeSgUtRQf4S6jP X-Received: by 2002:a0c:df8c:0:b0:68c:ade7:ac42 with SMTP id w12-20020a0cdf8c000000b0068cade7ac42mr7683877qvl.47.1707400386451; Thu, 08 Feb 2024 05:53:06 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400386; cv=pass; d=google.com; s=arc-20160816; b=alOCVBE1iSYGzwqi/xW/CcFTV+YIj5bVMAZ55rAXZaYU9N2SR3iPPpVMSh4mFoBkcN X6hlj4PXswfAqorb2fqTaRIJOUy2+9+ka9GzePzOPDMRfMsKbNSo59sfdv4cZ1JEfWi4 topYpP3TzmWWwWcO6r6rNm+oTQl6Dt9C9w2gfskINUGFpAu/jIEOjTfz2xcdfcgsgDeu cjtfDRUBSVLY5F4YEwx+/u86Bhv3BY3EvyffYqeuwg10eUiXevtryMe0YD84FG1lTWzg VqrjpLBbvx1ImWxS7TTEiVcUoIGXIyejcLX2d/i6xvml8XHquxH+M6qaRYCzHJYR4/Gw 4f2Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=BwyqOxCBKuWUKHqwJM3+S1e7+XETwlW6DJMJjNuYLS0=; fh=Yq164QNX8LuCbhiyQr46fADkmHLBhTD3c53ILNkqIbI=; b=z2Y9Wsow5Fqy5/YKC2KUQGXGFbjb0gSjVIe59fHd1rpY7ew4S+uHifLa/FfBiC1Qo4 cZeamdsByCmBOCTPWrfDv0KocJw4QPkCPCvJnu+VrM3tw60aJMoMqU8ykbH/GxQlvFjg u89JmFzCIw3AYIXQ7eMNrDueHeOxrhetN+nbq/lZGlJ3P0cqIY1ChlSfsHM3IyFG4tAV G5CXH0TFHdHM4cbjH3kc6zBHxKMQHMUPobNhS9i8HCfkNyUJ1e32ZTiYhyS87LWbcCx4 u5zUGHsJreDIQoaKsuxmo6P0xNl5oVoQpN6tGkF1GSF8YPwQmq+DR4G2eXoKClOs4s0X PFTg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZX6lfn6m; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58181-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58181-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCUG+Qg7+NOO5k84wRBnnAOHYMWc48B3aUglYvPSJhRWxpUojs9hS/ejoCrILZu2ad+oalRpu36yGUHGIAgyOIJr5p37yg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:57 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 06/12] spi: s3c64xx: allow FIFO depth to be determined from the compatible Date: Thu, 8 Feb 2024 13:50:39 +0000 Message-ID: <20240208135045.3728927-7-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339067442166162 X-GMAIL-MSGID: 1790339067442166162 There are SoCs that use the same FIFO depth for all the instances of the SPI IP. See the fifo_lvl_mask defined for gs101 for example: .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, Instead of specifying the FIFO depth with the same value for all 16 nodes in this case, allow such SoCs to infer the FIFO depth from the compatible. There are other SoCs than can benefit of this, see: {gs101, fsd, exynos850, s3c641, s3c2443}_spi_port_config. The FIFO depth inferred from the compatible has a higher precedence than the one that might be specified via device tree, the driver shall know better. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index b1c63f75021d..68f95c04d092 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -137,6 +137,7 @@ struct s3c64xx_spi_dma_data { * struct s3c64xx_spi_port_config - SPI Controller hardware info * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's @@ -159,6 +160,7 @@ struct s3c64xx_spi_dma_data { struct s3c64xx_spi_port_config { int fifo_lvl_mask[MAX_SPI_PORTS]; int rx_lvl_offset; + unsigned int fifo_depth; u32 rx_fifomask; u32 tx_fifomask; int tx_st_done; @@ -1263,8 +1265,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->port_id = pdev->id; } - if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", - &sdd->fifo_depth)) + if (sdd->port_conf->fifo_depth) + sdd->fifo_depth = sdd->port_conf->fifo_depth; + else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", + &sdd->fifo_depth)) sdd->fifo_depth = FIFO_DEPTH(sdd); s3c64xx_spi_set_fifomask(sdd); From patchwork Thu Feb 8 13:50:40 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198422 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179501dyd; Thu, 8 Feb 2024 05:53:20 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVGMm2T0K7/rvQHpOVN37h7hXBBL7syMuMQAIVVno336NutCQw6lxfoug1KbgoMFT450S8UqjXDnv+gMXYnVORei9jlrg== X-Google-Smtp-Source: AGHT+IECMlVCNNliaLrJyv1b6vOJDe1JgRIEws+tVRase672uqkrY4NQZQKTztricFAMyUqWgHNv X-Received: by 2002:a17:906:b42:b0:a38:1f86:9451 with SMTP id v2-20020a1709060b4200b00a381f869451mr6266388ejg.30.1707400400192; Thu, 08 Feb 2024 05:53:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400400; cv=pass; d=google.com; s=arc-20160816; b=WyKSj6G/JH3ufADZn8Qz3h1E60axfEt2BcdLROBzl7qI42uLtC0yddjNRemL/5kwqS woqv5h4To1o0Q3/GZPnVgyI23B5B5KlSeHR37usRwWZctyXLXJ+3q39eVMpp9cuXPJt/ Emr/mbTYZcgSlmUXkc0z/JZLny+pCzzZPWjj7zscFUKqcBSctjg24vWkWvskDsoGQOUD c6pFj1tlU8CUs8poPraUqqCLN9a3fNUr9q/1I0X90GTr0VxYrrn7rMGfpLOmevnLeW4l wp3NJBBZSuf+zzM5d1E2iJSWn8eOuHh7gifbw9SaQipDNdhbQu9x/XaC/NtNx4wFUv++ jCZA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TbvKAanWHb5NHCc78DYWj3IudYbRJBQeeD4twXOiMjs=; fh=ohuutxxKBDDOrgAtd8sLSHgL8WLljgHconkOCWTMxV0=; b=d6BbTEeCKHgVjEDQmIjLrMvlY8Zx2aylHTS5sSATRUymTbYweImUZzU/iDw7D50iV2 hA4azfmKgi4ZsbnTe/fPbdDAGJL2tQmULzZbi31EYzTw4ki/Dwzt8L+oBQ+0a0nHcGe8 qs9ViMwNLXQwYiB0S91mitAeiGA1kjvhPkhhbxWfeiWyF3c86ba/mMBOz3hhuPJ7OkSf 1iiQDR56zVMHp2UafWc11BuUWCq+l4zSPp2IRVRxkCQSr8Qb02u57ZTAgEHevClG/KG/ 4nJmFRgV+uevEwV9YAz33FjJEc+228UTuJHC20/gbHWzeLRwOAnAz5iuSNuPFCZNTG2D O47g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zC6yuWek; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58182-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58182-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCVTzrACeNEf4vB/Cw2BoWol73Wm9TTr5w1YE1GMnN8g5rBGCCTMS140v/KLnWx12LjdI/K+EMp1QU7VfY1Sqr89FwkbdQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:58 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 07/12] spi: s3c64xx: let the SPI core determine the bus number Date: Thu, 8 Feb 2024 13:50:40 +0000 Message-ID: <20240208135045.3728927-8-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339082195472140 X-GMAIL-MSGID: 1790339082195472140 Let the core determine the bus number, either by getting the alias ID (as the driver forces now), or by allocating a dynamic bus number when the alias is absent. Prepare the driver to allow dt aliases to be absent. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 68f95c04d092..ac47755beb02 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1279,7 +1279,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->rx_dma.direction = DMA_DEV_TO_MEM; host->dev.of_node = pdev->dev.of_node; - host->bus_num = sdd->port_id; + host->bus_num = -1; host->setup = s3c64xx_spi_setup; host->cleanup = s3c64xx_spi_cleanup; host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; @@ -1360,7 +1360,7 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) } dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", - sdd->port_id, host->num_chipselect); + host->bus_num, host->num_chipselect); dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", mem_res, sdd->fifo_depth); From patchwork Thu Feb 8 13:50:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198424 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179882dyd; Thu, 8 Feb 2024 05:54:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IFdlI/4fYI46JiP9BvYwmXSCsTg7w5/gDxqEAwLGdR9TGDtAwb4EHKB6F63FVmTpEjkJtHd X-Received: by 2002:a05:6830:22ed:b0:6e0:cd09:47a4 with SMTP id t13-20020a05683022ed00b006e0cd0947a4mr9353315otc.35.1707400448951; Thu, 08 Feb 2024 05:54:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400448; cv=pass; d=google.com; s=arc-20160816; b=Va8E//gk6wDJ3aB2CsPqgURJ/sRb12olS4fuAY+v3UpOeZDshiPWGk2XUDK3/ZCd1z /1wt8Xoh/FHWjyGszuzH21uTlPci07OnnKz8+E/L/IaN/PqUOpjehnZLIJIO9QzB9KzY edF8j4p2OoZ/+mFgsW8twnHW+IpZs8zHjYAJjA+dEZZpyN79JIa8IaU/yqK+2+hLho8Q DWPSI4YwZEc7xBU8B3177VAyKFokAcxHf88Lvc469HTJlnY/q3+NrWxoSMI1IgHYuHkl 0OrTT4gWYjFOVE2n0hRIHvZstOag/L7hy/PcwA7lXZFe/NAyKQ3+2iCOR3xXdprCMUDW 5EdQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=OTrzZqM2Ss1d3JLf/TDWyYpLJTs2h0kZukw/0ZYCnhU=; fh=pIR6n5j+qy2MKmGNiCObfE6bFXRs+8lrfULdvg/n8IY=; b=zfkBzWpli/6qf3T9+5JJT3+Hdvxmp40hohUOx2JWsj8uABQF9gZmJoG/VozhoRBSiq KSxI4cnfsKNAq4mW0IirC3BOXIpCvOaWuN3gojwKoRmkMo2uD3w49B9U3FgB75Ddtl5G Gapbi1Kav89ORloSQla5LPzGNbwMR5vIv6OxK8SFaLtLLm3A+tu4iTsBb1MgdsNRf1p1 Wow/VGHxnxQrMzX7IOYneU0IRJ3gYctAXjDwA23jJsZ0IVoqijaZZUUwbVnfPdas9ry7 PK5mdIU4m1Bl4xYBFkQdZUYgdnZY/XW33EQ0Bw8DYiY2DBKyj+C47yjjLDOB9oVfb/2Y n0CQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AOWFEBKt; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58183-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58183-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCX/KjmDQ81KhNca7sFy38DZs//U+k6F2vcWYNa266L8jK3/XRaXdRw+BD3EeFAe7/yp86w31RntnyQgAg+8eqswo01l/w== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:50:59 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 08/12] spi: s3c64xx: introduce s3c64xx_spi_set_port_id() Date: Thu, 8 Feb 2024 13:50:41 +0000 Message-ID: <20240208135045.3728927-9-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339132794782501 X-GMAIL-MSGID: 1790339132794782501 Prepare driver to get rid of the of alias ID dependency. Split the port_id logic into a dedicated method. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 37 +++++++++++++++++++++++++------------ 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index ac47755beb02..40de325bd094 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1200,6 +1200,27 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; } +static int s3c64xx_spi_set_port_id(struct platform_device *pdev, + struct s3c64xx_spi_driver_data *sdd) +{ + int ret; + + if (pdev->dev.of_node) { + ret = of_alias_get_id(pdev->dev.of_node, "spi"); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "Failed to get alias id\n"); + sdd->port_id = ret; + } else { + if (pdev->id < 0) + return dev_err_probe(&pdev->dev, -EINVAL, + "Negative platform ID is not allowed\n"); + sdd->port_id = pdev->id; + } + + return 0; +} + static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) { const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; @@ -1252,18 +1273,10 @@ static int s3c64xx_spi_probe(struct platform_device *pdev) sdd->host = host; sdd->cntrlr_info = sci; sdd->pdev = pdev; - if (pdev->dev.of_node) { - ret = of_alias_get_id(pdev->dev.of_node, "spi"); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "Failed to get alias id\n"); - sdd->port_id = ret; - } else { - if (pdev->id < 0) - return dev_err_probe(&pdev->dev, -EINVAL, - "Negative platform ID is not allowed\n"); - sdd->port_id = pdev->id; - } + + ret = s3c64xx_spi_set_port_id(pdev, sdd); + if (ret) + return ret; if (sdd->port_conf->fifo_depth) sdd->fifo_depth = sdd->port_conf->fifo_depth; From patchwork Thu Feb 8 13:50:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198423 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179704dyd; Thu, 8 Feb 2024 05:53:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IEWt3+IEQ0CAT83VzbHyvkB1e2OdPY7AXvdqCgFL4CW5yYdMxCAHig8lhkBSW8r0E76hnDK X-Received: by 2002:a17:906:314a:b0:a38:35c5:76f0 with SMTP id e10-20020a170906314a00b00a3835c576f0mr5937401eje.11.1707400426509; Thu, 08 Feb 2024 05:53:46 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400426; cv=pass; d=google.com; s=arc-20160816; b=sZFdCeKEoRb9PQ/4zb+H0wHqz8mqly3ZSfsh93xGJTf/39XNpdYG2txiqBI9G3ibf0 1Y++/OV0zhHAvKyJJDjhY9wsw9NCKm3vkKRXY48WFUtuxB5vg9/B5XJYVeoU/hKA4A+J Uan0+ivBGKb837aWfNxg6GKhaRDip6yRalm/yE789TRptx0wihbt++LrEfrPpdIoq+4A Ikaa2fFEXohfQF7l3d/5C+0tgu9Jp7E6sZzN0XmXZS8mVVwDC+bXFzy2vDSw8B1rKEJe tLcke4b0Id2owYMWOIK6EV+0lOZdxERXmSpp2LZG2VSZTqWLQ5eND1MA5FgtGdfEwzgU oZNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=mLhU5Fpjpt+G1J97uCF7eZiB9eQQAYSw34EErx851iQ=; fh=V6E4HoLMqOSdEJDhRfLpkuV8LFNO6uh31Fcac4gxLhs=; b=C/WjYOGrodNvLdE2h8W24M9RHznc9kBHXIf/DWE4xRCwF5PbbA8sjOzUDEz8AA/xym I05tUGMZ0wTcTRKWVIebD7w6epR2pAbU+99owQEVH4eArL20/1QTmH6418dY9I7C0pku jcW5NYyMwqhh+6EiLsxRyS8NLLcpNfb24UntvHqqpxVmwSnBD+tWNz0nhoVu6GkaaSd1 xXskWwTDHwXVIwvrsTQhbLM8Q62Epbob8d7qxWYHxyvrqQLvW8kT2vlcDvqGcHLjR1Th VBZA9xV8sZLeTKBnTqyFYjQpI+KX6kK0WAY+k3O9jMn9DEI5NS7Vcgvlb/uFCEAgkULp 4tfA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=cl0h5BjN; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58184-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58184-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWWDjLLZWAzRiKZ6yLDuZFObnDf6obIA8jeB7Ua8CpDCmJXACfmCnzFE/gnibEIasI5ccOfymHio418b13oKpq4cH0IjQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:51:01 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 09/12] spi: s3c64xx: get rid of the OF alias ID dependency Date: Thu, 8 Feb 2024 13:50:42 +0000 Message-ID: <20240208135045.3728927-10-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339109667540430 X-GMAIL-MSGID: 1790339109667540430 Compatibles that set ``port_conf->{rx, tx}_fifomask`` are now safe to get rid of the OF alias ID dependency. Let the driver probe even without the alias for these. With this we also protect the FIFO_LVL_MASK calls from s3c64xx_spi_set_fifomask(). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 40de325bd094..d2d1c9767145 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1203,8 +1203,12 @@ static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( static int s3c64xx_spi_set_port_id(struct platform_device *pdev, struct s3c64xx_spi_driver_data *sdd) { + const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; int ret; + if (port_conf->rx_fifomask && port_conf->tx_fifomask) + return 0; + if (pdev->dev.of_node) { ret = of_alias_get_id(pdev->dev.of_node, "spi"); if (ret < 0) From patchwork Thu Feb 8 13:50:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198425 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179904dyd; Thu, 8 Feb 2024 05:54:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IE3x9z2YqSTfo91BE/JZbjBCYJX48htsPkKgtDL4ShBMwrBSe5VgaGQCAqTR5kTxWr2e50n X-Received: by 2002:a05:6808:23d2:b0:3bf:d786:2771 with SMTP id bq18-20020a05680823d200b003bfd7862771mr9413851oib.12.1707400450628; Thu, 08 Feb 2024 05:54:10 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400450; cv=pass; d=google.com; s=arc-20160816; b=hRoXj4h4rrtESOnOMd5YlZR2a0n/BieezCpClmPAe1HSRNaK91cVyS6obxttg8gcaW e7Mn63tNAs8waEVXCuaW9E84X06iyucLHznoyKbx0XqKR8c1Tjha/edRNSv8UQrut+sa TX0DVFrj8sit1PUXdrtkQ9F8+KtRT098urtAQI8DKMhM7FZ5Skt6Ydt8Pnr5FzdSLz0C fqtEGu6lSIrUMibteJj5Yugt10toFoyeDhlVcMlwsNFs6wQGaAvk4hANLnnbKSW+I1bK NiZANHGL4BeGW7A37fc+9+QKOww9dDQV6E09MYPznmJzXkQf0K+X6dugeZizL2xFRY02 Oa5A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=fm5OjWDCnevgUex+kbg78oFWzlDeXhj9v/6Ap/z4iAc=; fh=8zJnEUl3j3akj1THVmpkDNp7wqX1WTfV/KvJ1wHCUkE=; b=h7qN6xYeJ6d+fnhoYlmKXKkjpN9QTESFZnMOta298noBub8H7XlML/4YmxDhy9Pmrs T95vi/WeDmEIxUp9qpG2gadXbGXVgrYax9yCGLmAFQudRh6+rBL4daBSwHnWLgIrqL9G kxxVXbm4rakM1NfH1cjC07e2/TRwBj8WJ9A+f9Py1sndrXhmsPb5hhYJfQBAr1i/pkQp r6hoCrgei1PCKYnh8UqvAH1HEoLgL1IgUvaBdPalBh31k211yPGOa0Rc66lq5uuf3D/N AhZw6qHKT751CHN9y/412cP9uBHioMY1lkcWEtu4C95cMMThsA5TC15rA+79296Sio1h EMvQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="WUHc5/oq"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58185-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58185-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCUsQOHUipQOnJYPayM7QBXukpHMsoD7gs2EU6/rUGylUkUOlwgoQmQM9LAemc04gXlv1F17jD1AbhkiD8DFk7fLy8Tv0Q== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:51:02 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 10/12] spi: s3c64xx: deprecate fifo_lvl_mask, rx_lvl_offset and port_id Date: Thu, 8 Feb 2024 13:50:43 +0000 Message-ID: <20240208135045.3728927-11-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339135177348437 X-GMAIL-MSGID: 1790339135177348437 Deprecate fifo_lvl_mask, rx_lvl_offset and port_id. One shall use {rx, tx}_fifomask instead. Add messages to each port configuration. Suggested-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index d2d1c9767145..128f4a7c4bd9 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -135,8 +135,8 @@ struct s3c64xx_spi_dma_data { /** * struct s3c64xx_spi_port_config - SPI Controller hardware info - * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register. - * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter. + * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. + * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -192,7 +192,7 @@ struct s3c64xx_spi_port_config { * @rx_dma: Local receive DMA data (e.g. chan and direction) * @tx_dma: Local transmit DMA data (e.g. chan and direction) * @port_conf: Local SPI port configuration data - * @port_id: Port identification number + * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. * @fifo_depth: depth of the FIFO. * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's * length and position. @@ -1508,7 +1508,9 @@ static const struct dev_pm_ops s3c64xx_spi_pm = { }; static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, @@ -1516,14 +1518,18 @@ static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { }; static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 13, .tx_st_done = 21, .clk_div = 2, }; static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1531,7 +1537,9 @@ static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1541,7 +1549,9 @@ static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1551,7 +1561,9 @@ static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1562,7 +1574,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1573,8 +1587,10 @@ static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, @@ -1586,7 +1602,9 @@ static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { }; static const struct s3c64xx_spi_port_config fsd_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 2, @@ -1597,8 +1615,10 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ .rx_lvl_offset = 15, .tx_st_done = 25, .clk_div = 4, From patchwork Thu Feb 8 13:50:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 198426 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp179928dyd; Thu, 8 Feb 2024 05:54:12 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVF6zksgzteV/b7rp9X0Xl6GZ3Pg51vP1mfKikh0f2CNomNWYNdSAGP2d5H4R4NSxZhD8hAGW4rBmqCAm/RCY+BJuWUOg== X-Google-Smtp-Source: AGHT+IFgh3RnO3hu5ZedPL/Q60EAPxST6CkzbQlVNQurGa9uIgBESZuo9hQKG2deit92cwcBSr/F X-Received: by 2002:ac8:480c:0:b0:42c:4214:8eca with SMTP id g12-20020ac8480c000000b0042c42148ecamr4294549qtq.53.1707400452451; Thu, 08 Feb 2024 05:54:12 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707400452; cv=pass; d=google.com; s=arc-20160816; b=jcpUjOm+eNuagCUOkvA6zWjBXfMvjRumcnMhDzMf9SWy7sIrHzrhImNbFu3s/cXTuC d11JvghiWcW8Uo9rhWhWiXXUMnlZNoVrzoyUpWfdXYKxZBMioSxkyjfGxbUWvEf8+LiG OqXKCCKoV71KlO9v/A1HqO7XbuO7mo6coppw5BLHBFL4s3vh0a3r15CG9mcNKNzLoHee +vsu9sI2/HOKhq8jc3JdbkJc/TR0xolYcUhUg1YTGYiCT/tMYdEmgYk215tFis7c9Cjz 3d2V0u3Qm6dKTXgUVbDPYmiZvdCmofppyG9hUCG9cJc/Hi8YiemGLdE4ARtG4xCNzbR4 HaoA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Br70UdzJ66zrd4gMWvBDaI29gJMy6u4vau427MAZ/bI=; fh=NIk7sIsweVbcBGQXqW9/gvxIjvsa32p3mM3i+L80sic=; b=xkESmlq0QTy0UMCrXFXNx62fGKiQ5kA73mtI4ckUe9Y2ZOkEXEIK/lcXrbBAFYVxC9 eT/zH3Vy6dllZmu2c1PYO21wsCJ/rf2DllQzFtt71UiYDBt1h/xGDZGu51wCUZS4VcGe IQwofEekdi+kl5esl323vtcLeJi7F2rDgY2MTmGHBAOximApSeuQ6BUGmybzz4b7tLsy kiNVRzURGLYZxmCSgo6ZXPEtmif+uHeLF0FijUmjXbJr2ixlkm3Cm8JM70TtSVSDPq77 LXQV7r7TqZz758L5wFwmx8CycS07sbm6QNG/ZdKAq6SqrzvcXbs350Wkgp9ZMbvPVegU NGDA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=TMYBUom7; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-58186-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58186-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCWYtrCbOPrHZx3liZIp+jdX5b41bY9YjR55mjuvLfP/xLFZ57l/V3440ASwkMYiebsL4Ch3Mz1Ctg02IJQB6P4DpBHvvQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:51:03 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 11/12] spi: s3c64xx: switch gs101 to new port config data Date: Thu, 8 Feb 2024 13:50:44 +0000 Message-ID: <20240208135045.3728927-12-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339136892256138 X-GMAIL-MSGID: 1790339136892256138 Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. S3C64XX_SPI_ST_TX_FIFO_RDY_V2 was defined based on the USI's SPI_VERSION.USI_IP_VERSION register field, which has value 2 at reset. MAX_SPI_PORTS is updated to reflect the maximum number of ports for the rest of the compatibles. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 128f4a7c4bd9..784786407d2e 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -20,7 +20,7 @@ #include #include -#define MAX_SPI_PORTS 16 +#define MAX_SPI_PORTS 12 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -79,6 +79,8 @@ #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) +#define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) +#define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) @@ -1615,11 +1617,9 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { }; static const struct s3c64xx_spi_port_config gs101_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, - 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, - /* rx_lvl_offset is deprecated. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id m20-20020a056000181400b0033b43a5f53csm3618820wrh.103.2024.02.08.05.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Feb 2024 05:51:04 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, robh@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, conor+dt@kernel.org, devicetree@vger.kernel.org, arnd@arndb.de, Tudor Ambarus Subject: [PATCH 12/12] spi: s3c64xx: switch exynos850 to new port config data Date: Thu, 8 Feb 2024 13:50:45 +0000 Message-ID: <20240208135045.3728927-13-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240208135045.3728927-1-tudor.ambarus@linaro.org> References: <20240208135045.3728927-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790339142059586106 X-GMAIL-MSGID: 1790339142059586106 Exynos850 has the same version of USI SPI (v2.1) as GS101. Drop the fifo_lvl_mask and rx_lvl_offset and switch to the new port config data. Backward compatibility with DT is not broken because when alises are set: - the SPI core will set the bus number according to the alias ID - the FIFO depth is always the same size for exynos850 (64 bytes) no matter the alias ID number. Advantages of the change: - drop dependency on the OF alias ID. - FIFO depth is inferred from the compatible. Exynos850 integrates 3 SPI IPs, all with 64 bytes FIFO depths. - use full mask for SPI_STATUS.{RX, TX}_FIFO_LVL fields. Using partial masks is misleading and can hide problems of the driver logic. Just compiled tested. Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 784786407d2e..9fcbe040cb2f 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -1576,10 +1576,9 @@ static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { }; static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { - /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ - .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f }, - /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ - .rx_lvl_offset = 15, + .fifo_depth = 64, + .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, + .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, .tx_st_done = 25, .clk_div = 4, .high_speed = true,