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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1I074789; Thu, 8 Feb 2024 06:32:39 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Thu, 8 Feb 2024 18:02:25 +0530 Message-ID: <20240208123233.391115-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334048014159816 X-GMAIL-MSGID: 1790334048014159816 CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with schematics. .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 361365bb5523..5631735c9b7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; From patchwork Thu Feb 8 12:32:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198367 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp130940dyd; Thu, 8 Feb 2024 04:33:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFB7ea082JwI86a2WxKmVUxMTr0fbVGAh6QwWzX95AhPGgsJ/9n/nfzSRiOFwve7rfbYIye X-Received: by 2002:a05:620a:4ad0:b0:783:9999:85 with SMTP id sq16-20020a05620a4ad000b0078399990085mr9018091qkn.42.1707395622560; Thu, 08 Feb 2024 04:33:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707395622; cv=pass; d=google.com; s=arc-20160816; b=WUQL8p8cMOMQWiRcmHeSywEKhWNqHLpx6JU8mCGx9l9/SzuNtbGGd4BB3Lvf6vCap8 HyFshuqhM06/JDMJ+1O7koTtD7kGIiTD5uFao3kJjIxCvv9k3x8NBx8ofGC+/6M3VDDH JHMAQXiYdF9GPmDKiy1P6OX3M/BqyJIK4KPbzNOslg7Sr/Bxk18crj1wEX2+qsiAyebD bUGld62JMX+t4rY8Tt0GMWtVctiW5OEkJU/y2YlLWoSaCL7KGm+1iJSnFjEXOJPhvMWW zg2BLpTuEGheTx5BRc1Vbsk33K+3CP8jZ8YZfz1g4WgXhgljTiZEKiBW7S/y8YeThgw8 r+kw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vFJTReo+YvdgCPMOvXasBur05DlcLCv9EjXrvlB3Fhc=; fh=jlTjFAdsZhfoUkx6jy1j7HMpO0p9yqZMkvi7bl3Mh0A=; b=ADrwE+GDeJCIrkd6Rqr/iFit7Bqf7oF2tCQoLWeGF4MAxjXOvsSSTtNZP3hLyQvKEq yEN77zyxljgz+IVtlYGRmD4+23knF8A3GvFWiUctyxwbA56e/MNTWplkJ2/kHqXfeDbY m4iA6yfgGjCK7F0aGnMEec2113dzIjphEwZzcTaKwV3lI7p1NYt31H45zd7l1sNmV2UC jXhG5F2VkRl0u9uzJ2xuJEw9V0pl4aSg/ydGZeTHx1TNo0laTARN11WSBz4NZWtKvZQs JmVea8lqIj3VAH8j9SmcsOpjE25Ezppu6mC1Zijt0snYxkxPF/j2h7gECOG+ZvlMGr8O ZIOw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=GLWJM4Tw; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-58056-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58056-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCVFnjw4jAlcJ7e2MrA6CkV1V6JDIfPZ6vflaJ5n5L5Ik4RZDWLaBBHhAE1kLz9bdurUcIAOEXgagNgl4G3Nv3pmRMqOLw== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1J074789; Thu, 8 Feb 2024 06:32:43 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Thu, 8 Feb 2024 18:02:26 +0530 Message-ID: <20240208123233.391115-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334072426614017 X-GMAIL-MSGID: 1790334072426614017 CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 57e7cb8ea2b8..bb2558b68381 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -297,6 +297,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -761,6 +768,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 8 12:32:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198368 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp130980dyd; Thu, 8 Feb 2024 04:33:47 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXInTSTk+WEujQIywvDgVRKzFtDdyc1a/nTOiyPnaZsUtqeJxBKZxNRfIIhICm2c1XDhMrUcXI4CjmruRYzaxgIka0H4A== X-Google-Smtp-Source: AGHT+IGvYHwTMHy1B0yCIBlM4iGjg/xDLgpWT7nyh3n55hMphdoZ4+jwZKTRd5mycVZeC/H0WB51 X-Received: by 2002:a05:6870:14d0:b0:219:3054:3ea5 with SMTP id l16-20020a05687014d000b0021930543ea5mr9707474oab.45.1707395626979; Thu, 08 Feb 2024 04:33:46 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707395626; cv=pass; d=google.com; s=arc-20160816; b=iriN/Q610/LDUvui9/CYtMJ/2I4dNqbNvePRyM9Al2rr+8lH7WtZVVHQBixTP10LmG N5/mA/9A7JUdYNQhnsX2aEo9yd6jACQHl6Rlw/RCpubmpyoi75yA8zhPR5Z8Wqfar3ls nqzehHYrllphFJzEn/qn6SrEwH7GCyFLn9evxUkj4xYGHJ/ko6vw4i7Y9vS3lkplH0Z2 1wA4fkQ+aYZCXQqmjbaORDTra/mdx74YeUL5ZJi1ByGeMVhW8VNZ2/DvcuGu5xJpr4yD CpA1f1zoqFyzrWDO0RjEUvhXvcZeaeZjgc0WARz433k30QbxDqdDSccKpITD1FciGV2Y sDGA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TWrJ8V/kuL2/rmJgQ1VQBzvBtGtixOdca6bzZEIm5eM=; fh=/q0sVz46mqWDkKzJKrvsWYD2ACx6e5hoQpTuib4OP7U=; b=HrQAdeo/uomezUhKoyYAxHWjVtRyfWnK/JTXNBAq99OJN0lEa2nGa0WLfnTtTMfVeR /Lyg6r/rDKcWLKAcSq0zeACBK8WZt/SnLP6A+FCpPKgETDAUetr7SgqKKeuV7MTPhCDf swv9rz401fQPVZUY6g4PcaB5t8WfOnQXnOl0YDwN2QwOPKwfhYuPmsx7clb8q1IJK6g5 k/mpwdg8emuADtOa097vG0zPwc1xfZ4zp579+KWoJQPJhLokcwUuBQwETKTF/770Tl7u 9FskCG1k3cEN/9/4HT7fpZJQPyaaEEy9rylw9LMEsxG1YTEMvkLubZPCtDB0CRuqEkFu K8Yg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=neBGMqua; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-58057-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58057-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCWLMp1Z8HqiuQJHZ9oX6dICXXp7rtmYh6Y2xnrpl6JNRthhrLcHAJLoa2AKqbg8nGP3S6BuhDPV8NcIw+khUU+taBlOQQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1K074789; Thu, 8 Feb 2024 06:32:47 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Thu, 8 Feb 2024 18:02:27 +0530 Message-ID: <20240208123233.391115-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334076634325157 X-GMAIL-MSGID: 1790334076634325157 CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with schematics. .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index f48155dd16a3..d743f023cdd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; From patchwork Thu Feb 8 12:32:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198371 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp132038dyd; Thu, 8 Feb 2024 04:35:43 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCUVWz3pCBDqy3zNhiTV86AaCx2GTHlNuMAnJhxE3FrAHpa/2/OADwS1/+oq+kqcOkyCiSGg3nRxOCB25IJhJsTIr45z5Q== X-Google-Smtp-Source: AGHT+IEI8XQLpYAQLFoOsfXytZSymZ9/OXJe5+8A8yXnE9t0x+G06j7NWD6lo4nXL7HFkygv3ZhE X-Received: by 2002:a9d:4d14:0:b0:6e2:811e:a27a with SMTP id n20-20020a9d4d14000000b006e2811ea27amr9607598otf.31.1707395743333; Thu, 08 Feb 2024 04:35:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707395743; cv=pass; d=google.com; s=arc-20160816; b=LEJQvAPABQcwsReIRUkUUA2LpvfkKvsY2dLLvIoWGGPV3m/5CY0+0d1n1nUfLHLovq aLdqQ32h/ApfWbei/7VuQqaF1oma4bNTDjZ/hXLNzusxnHMcMniEYMnPHgj/RJOdPcaO sx2h12guKl78ta/wc7jwLUjGeoUImVguNcHjblEC/ykij3OoxpCYek3r5DzPwDvoomPN KclU1hQ5lGvp6tipWPgiUJWS1ZqKhk/dLTHmXqSAtLZnjRbct1fKQwuoPpDXreVKpqzS fPBm11A6yeJiHru0FC299ghyN7kx6iJyQTV1SbqQWjgjTcLORrux1RBnFO6c07p6H2B6 fGcQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=HbwTy/Equm1dvSIRmZiHY0g2j43SR0K1HVBL+ZJPY6c=; fh=F4L0QTP6asK3N71dyAtRFIYhOutE2ZGrwyWpNhON4EA=; b=QuVd8ixqRMBetJ4bIHrg0r5RbxtWUZadWdRpBJLI3pnCg80i8pbtWvvDGeri3ExUpe ODSXHVCMyGDO0Q70a2HRdCNK9AZ3Ucfjntfmasa03OSjOYSdIqgtRM8GdAs0wmKQEJ2v MY/eqqO0p4jZB7AByBAr/1UGMTdarNnKDDKZDbgXaOi38nSdlxsfzqh8u2EyQT6rgg5x dDTXK5lUU+tiCzujNwKaHBn/6Iyg3cwJrjiPke8RCS37AlWiwLtEk4hO5dOVLqQCmcOD bSedbUF8uoTBgcPq7t2qbdqF38HQeriKN2yDmxoigjkubvLZcaVSQGzKoKZd9VXqqXNv MzRg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=n1j7GNhs; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-58058-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58058-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCVPuPK6251vSzvWAfE0+6Pbow7eSZvQXQJdC0f9TC+8j5F+xusa1ST4bmGs74K6l1sPeCx2rb8L+4RG46l18N4bj8ZF/Q== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1L074789; Thu, 8 Feb 2024 06:32:51 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Thu, 8 Feb 2024 18:02:28 +0530 Message-ID: <20240208123233.391115-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334199205012307 X-GMAIL-MSGID: 1790334199205012307 CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 5f0a43a69333..46cf90bb3eb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -322,6 +322,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + }; &main_pmx0 { @@ -341,6 +349,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -775,6 +790,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 8 12:32:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198372 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp132082dyd; Thu, 8 Feb 2024 04:35:48 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWfgcAffd3n4k/4lV7kXhndFFhSRzbaNQQsAoEiHBrmpvrqZSU20Iiv1zs6e00DNf42oz3sTCvlHNqJdHv9YmJYIgSwDg== X-Google-Smtp-Source: AGHT+IEsorpRS1cOnr11kNWoD3ijuvegwldIbaxXhkzGAC+uzJsGWZkWk4K4/CHfq9PCtb5f2+jM X-Received: by 2002:a17:90a:f3c1:b0:296:25d0:3bf2 with SMTP id ha1-20020a17090af3c100b0029625d03bf2mr5755602pjb.6.1707395748240; Thu, 08 Feb 2024 04:35:48 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707395748; cv=pass; d=google.com; s=arc-20160816; b=OVAqdhSvbk7SmCiU2RVFVcOg54+0hIKUXWuvPs0l3Y9Z0VOvOpPHUFFd8SRMW2a7HY dTd9bBxe8wLtgVLzjF4XAh+xvJeLQXgNSRKdy/lJCEJ7eMbpuCK1OrNwMdthnQSlABjE 7g2oD05cHNMCIAlxxYDf8cG3WnPKxz0wvM9LabKuIoS5iD+1aOQG0eFYc5kPf7VhwOB3 fTFX0rpae1irvthUm9AdT9bfTEtO2gWM/7FhV5v+qlw/44gcEobpookA5Dt+MBnUiNh5 Oeupxt2qEb3lNY5WYNHCUdzQwutQKpzDbaMeLH4XVMMGOvcwJ2rAo7I1YG+XCtTxbZK+ RDLw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=DKc02HWWYR0dDZx5Q7Pl0JplrS5pqsrVKOK5fBskcAI=; fh=kwkABOGviSBXssygSOPXmau7hwNW76StNofKDA3bpgo=; b=NH30mreQcJeH9divrOU5oAr0fw56GMcTa3a+DbPp5Ndb1i9RD6Kc7cCVB6jypIp4Wm vwmphzL47qayFZ7j4yL86cA6PjyASR/UuNwnyi5iUaWzn8GwYNdvwWBlHmtgUZUWISCU BTv2gqj4mIXTBw0163uf44QnSVW5+6/lV6lWgQ6abtSw+UDalYVz99Hc0VMe89wkb09N 0WBwq7TTSn13It+fWtNhUtqH1agLSWmAdcYzrkp2YVWQv4I9KV8OqwgmMN9mrrh8sAdM DzFbtetEcDu7PltLid+n5bTwYPeW86rjsQ0NPPaQSnTG1ScCuTgppPBAZwQsUBg1SwDc j+ig==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=FzsTaQP1; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-58059-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58059-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCX9fsxViEL5fg1jYv97iDp8PSyqAjmAZwqKWP8PqnaIM1NbTbW6GW/QmIsYEo/j3fysm48C53fWXgaU3nY+NmvY8jzhwA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1M074789; Thu, 8 Feb 2024 06:32:56 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Thu, 8 Feb 2024 18:02:29 +0530 Message-ID: <20240208123233.391115-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334203818217415 X-GMAIL-MSGID: 1790334203818217415 J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 6950b1ff124f..5dbc85bc5038 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; From patchwork Thu Feb 8 12:32:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198369 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp131373dyd; Thu, 8 Feb 2024 04:34:29 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXs8BLEJBOox/St1KfNVg4Dw8iYLPA/Id0XBga/NViH+isLMhYNuxOAATx0TJ38P2k2UngyU36Ap9lJcS/F23ovJI7q/w== X-Google-Smtp-Source: AGHT+IEE2xK9YSj+OJ5fFZWYcUnbIRhc9CbzydOb5GIe/1yApidT49q6F38rwXp9FS4RBzWxhMqU X-Received: by 2002:a17:906:6608:b0:a36:741e:a5 with SMTP id b8-20020a170906660800b00a36741e00a5mr7226699ejp.70.1707395669616; Thu, 08 Feb 2024 04:34:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707395669; cv=pass; d=google.com; s=arc-20160816; b=fCO6M2icf/K+kxYiCe8iX4Fcw7j/BlZiJoCQD++12LdQ78Mnm4eq4d+DD9+4jsOSWw 2ORQPLn8me/UU9T51Lvo2Ff5z61LDRoWiV2INTJ4MdmTGJ/NK7WS7habHptuqFSs/ZqU Ja/uGHjFLIl0vzd6T1goPGbn9vntaIXmZEJEnhSRpWlJDg5em54+1zUovqvKqzBblDGh GIoOn/BZtIddEBr6xvIu95nNrnHKTRS7vW7dt2Zh6eyV1oPIw30ndwtzthQu8ElhyG3M x6DqX338o0+yw7dIDgQbukUazkMYWUFM4Pz5VF5jzLAsak8OSGSlOxgxu6pXn6z55Kyv KAWQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=hCCOXa05ODAH1a822OcuHgt/RJjrEsz2rIxEHyk9pHc=; fh=JEse7nTpX5IqNvJCWr7UG4pU39dYuKpKWA5MjCqINXI=; b=VURoaTdSmM4jhsWr4gfXiToYDDGlRTw4ugNIgRhopZ/Q+s0jcc6pW0OxiHHPIamGRp i18OjIkLSLZf2v87J+wgMNDINKFdrNZn0p3amNOjRH1cZGqUm3i539nVplwazTo5IKNz nqC2hBVAAz/GEST+mHM+ysNkDBcMMnqEHFjhdiLVeDPas7kX9E+n6LOX26waRDOPl3fC OX5TQRl/6u9ulBLKJTgZDvkvHQjZMBPGUfzopTPeNoiB6TgRt0y1/+yp0A+/PQM2BZbk pJFHw1X8whF4SpgPnx5Wv1jF7wvN7WiR4+jyM05WmUqOJYc0+7957I37fCDIrrttrSE7 mtqQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="HXx8JDz/"; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-58060-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-58060-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCWuvZ76KOzcGryYXHhedYWwmd16v7TAnxMUzBmGQS7fR/2Kea6hRPNweQvLsGYGGySszGUKNTad5lUINAGf7fCJVzi3Kw== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1N074789; Thu, 8 Feb 2024 06:33:00 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 18:02:30 +0530 Message-ID: <20240208123233.391115-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334121821678217 X-GMAIL-MSGID: 1790334121821678217 J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath Reviewed-By: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 062a6fca5a31..841752d20de1 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4500000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x0 0x4510000 0x0 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 148 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5000000 { compatible = "ti,j721e-wiz-16g"; #address-cells = <1>; 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1O074789; Thu, 8 Feb 2024 06:33:04 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 18:02:31 +0530 Message-ID: <20240208123233.391115-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334229315172548 X-GMAIL-MSGID: 1790334229315172548 J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by: Vaishnav Achath Reviewed-By: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index dcaa4da0d678..9063aa609993 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1P074789; Thu, 8 Feb 2024 06:33:08 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 18:02:32 +0530 Message-ID: <20240208123233.391115-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334245748209043 X-GMAIL-MSGID: 1790334245748209043 J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath Reviewed-By: Jai Luthra --- V2->V3: Fix order of properties as per dts coding style. V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3cb964982792..42e4ca1d0b65 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04500000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04510000 0x00 0x1000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + reg = <0x00 0x04520000 0x00 0x00001000>; + ranges; + #address-cells = <2>; + #size-cells = <2>; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { From patchwork Thu Feb 8 12:32:33 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198370 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp131773dyd; Thu, 8 Feb 2024 04:35:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHfgqdlhKP24FjTYGjovIOwNGErtgwFD11GEu/v98slVj5iA3hApVSsb9Wdp/zp7pnRrYo4 X-Received: by 2002:a17:906:a412:b0:a2f:d73d:e99c with SMTP id l18-20020a170906a41200b00a2fd73de99cmr6063068ejz.14.1707395713056; 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([10.24.69.142]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 418CWY1Q074789; Thu, 8 Feb 2024 06:33:12 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v3 9/9] arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 Date: Thu, 8 Feb 2024 18:02:33 +0530 Message-ID: <20240208123233.391115-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208123233.391115-1-vaishnav.a@ti.com> References: <20240208123233.391115-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790334167671726699 X-GMAIL-MSGID: 1790334167671726699 RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Reviewed-by: Jai Luthra Signed-off-by: Vaishnav Achath --- V1->V2: * Rename overlays to indicate first platform (j721e-sk) supported and dual camera. * Add missed build test, fix missing newline. arch/arm64/boot/dts/ti/Makefile | 13 ++ .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 125 ++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4a570dffb638..e019efd3ce94 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb @@ -106,8 +107,14 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -122,7 +129,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ + k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb # Enable support for device-tree overlays @@ -132,5 +142,8 @@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-am68-sk-base-board += -@ +DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 000000000000..65d7cefb6063 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219_0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219_1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +};