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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshL097884; Thu, 8 Feb 2024 02:42:59 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 1/9] arm64: dts: ti: k3-j721s2-common-proc-board: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:46 +0530 Message-ID: <20240208084254.295289-2-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319732653820381 X-GMAIL-MSGID: 1790319732653820381 CSI cameras are controlled using I2C. On J721S2 Common Processor Board, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. Common Processor Board schematics: https://www.ti.com/lit/zip/sprr411 J721S2 SoM schematics: https://www.ti.com/lit/zip/sprr439 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../dts/ti/k3-j721s2-common-proc-board.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index 361365bb5523..5631735c9b7a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -147,6 +147,13 @@ J721S2_IOPAD(0x060, PIN_INPUT_PULLUP, 13) /* (AC27) MCASP2_AXR1.I2C3_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x01c, PIN_INPUT, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ + J721S2_IOPAD(0x018, PIN_INPUT, 8) /* (W23) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -356,6 +363,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO2", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { /* eMMC */ status = "okay"; From patchwork Thu Feb 8 08:42:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198211 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp27696dyd; Thu, 8 Feb 2024 00:44:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IFsnH7iP3tuGolc47SS381scJRTgB8VWxB+6OkKuXIN3CSsJhMnn0UtLRqwm9x+rk1VHNNf X-Received: by 2002:a17:906:31d4:b0:a38:4eae:b12b with SMTP id f20-20020a17090631d400b00a384eaeb12bmr3685202ejf.60.1707381842633; Thu, 08 Feb 2024 00:44:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707381842; cv=pass; d=google.com; s=arc-20160816; b=A7E+evRXRbE810JFFq3c4O8sWu+g5bK7lHhHX4ghF6E7xKKPDj0Mk/EF5BCl0cw2x4 wNC0At8IXOv3JUpMRLgQ7K/+G06awdBGCwdPWBI2fRlpQ19RjY+/L0U7pT48kP5DG4he zdnWOKH7sL3QG8ZjIlNcnCZKsDC5JvQzfL+dWtTz7bjxJWSV9X2xGUbWu+g3B1VmCPza +McMrlK2+c5eZT3Pw4DDx54786ms6SPSTjbs+cNIyFyCzOGWha7T7EZgK5A/pOyCwNgs jvA7gCfFLW0d8IoJxWrZ6gkr7R7ffs3tN1i/KVZ3Fh1YZ8OMuuNagovMYVSu5xzgrMUn 5PGg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Ja71EasRRzr/RjhKuh+9EXL1qoKYEN0T/N6Ly83yc8U=; fh=gOcMbMtM495FGXBajQtRaTFoHeiKxV9L/zgFqQWcKg0=; b=Vc2Kg/bYGHQ/+5bBsG+DMKMcB+jJOx3B5DlUGryi9fSkGDnfGCrEZizNvgDre8gXvL P9mrnz3jC8p94QCqzvOvA53oHskZ4hWernmve2Ire7KsWOXPtvLYjnEi1C+eOfmIlHD8 G9PM3h0Slt+Qm8fQpGzXKolsqNOYr1ie34aerEfq338FEjrKcE03BRujqBLlb1ntMujr YLObeFi/mfgXLWeZfha8+nahaetNXqAk9zCvsZhIS8G4t2ISJe72hgGG4u5ZPHKSU9WN uQ1EWQ0peAeKe9IU0GXEePSbf1UnohKpjZvRnXNjw7Hfi24YnCjZsVjbVgQs0TWzOUwC 5XLQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ODsLE5yD; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57633-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57633-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCXDtJw05g+txS930vR5XY4frafqFCeSBKiQenympbiwhEiA8fyoPTN8gLpwmxZTxyn0rn2daZ/n+RvDtqcUtEDnnYageQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshM097884; Thu, 8 Feb 2024 02:43:04 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 2/9] arm64: dts: ti: k3-j784s4-evm: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:47 +0530 Message-ID: <20240208084254.295289-3-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319622906913463 X-GMAIL-MSGID: 1790319622906913463 CSI cameras are controlled using I2C. On J784S4 EVM, this is routed to I2C-5, so enable the instance and the TCA6408 GPIO expander on the bus. J784S4 EVM schematics: https://www.ti.com/lit/zip/sprr458 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 25 ++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 57e7cb8ea2b8..bb2558b68381 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -297,6 +297,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c5_pins_default: main-i2c5-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ + J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -761,6 +768,24 @@ exp2: gpio@22 { }; }; +&main_i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c5_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp5: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", + "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", + "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", + "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 8 08:42:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198216 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp28707dyd; Thu, 8 Feb 2024 00:46:27 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXGlW2+2tFOF+u/RcBvfkNMRiJn9L+4+hCc3fBpr0Bu0g7h9hKqs+QK7/CQ2+agt5SRlq2lOYqUfQMnvkc4PU5vFWqKag== X-Google-Smtp-Source: AGHT+IGHQt8hnICIp3i2ohaiW4M49gCG4/HKZa+tOyZjTWRriuQnuvN1/qBPEzNne1QfQv7tyvTz X-Received: by 2002:a05:6402:1b0f:b0:55d:30b2:983e with SMTP id by15-20020a0564021b0f00b0055d30b2983emr6650064edb.4.1707381987303; Thu, 08 Feb 2024 00:46:27 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707381987; cv=pass; d=google.com; s=arc-20160816; b=T1deQpi3kwrrYan87z44d0B2SO4RiIlyuwrS58XFsXTGKwm+5ttbmkA3kRiJhRm9xd kIo1a+6Qqpxj72znrbQOsDtiBGIlJie20iGD75TyzlQhk2BWO2ACqps+xC7/+l+zmwq4 Ubi9vALMpt3bxbE7b6enIh145OFd59NVY9pq+QPKjLDo3SHOBVEMFt7070WbwbRvf2Sb XbOvE5vYAf8oOZiA4Eb8vZyHfcqV7lILUXWnoX+XRaVu//xrOItdNHygNbYPJ22m5Mw/ yPvETuoKi4WGQq3QKsiVDXycIjelnaPDO2NFVYYcF7PcCC9y85LWER+gY41WvZp6WaHZ PYkQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=4A4Z/qpcZA8AC33ULipWc2n/UZEdk4NC/YctUo/j1+g=; fh=UdIKU3Gz3aynm2yqZClNvrQTnQ+yR1iFOTlO5UCetF4=; b=lxsooYdgDi4++GBx5pXXgh4zu+39tv58n8BHQAJo/9U9I5ogqeks2ymtbINoJ5jIMO jlX25s3xyx1mihoik/Avb681anw3rgt8tmXI7PDq4tkILjnpgZ4grWGedZgQUBVnO7lC Xnyh9i9jrqdsSmyQWAA7pi0/QzIkHC+bvR6mv33SELSQhWWvogVM/bO6OkhuEpUeIIK8 9DJeLIyx5cqWuPYnH7G8AhKKYTv0F4F8Un62+vADrqVrnjXtaBR+wEpvuPj57u1prl5V yZsjjSIj+mIPhmF7Lh20ed+H6sFmrAes75Dd+V/ybl+N9t+3yZi+EyAQGz2PcIA5P5e0 sbeg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=Vz7PWxx5; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57641-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57641-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCVo8LKIVK47R4/gsRojxCEDmaLUiCFdrKmqOyXK1E0pFQVToFWKgL1hdH5Uw04aCVcpGFAg27VLM5pEUqdsQ2JnIvuDwA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshN097884; Thu, 8 Feb 2024 02:43:08 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 3/9] arm64: dts: ti: k3-am68-sk-base-board: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:48 +0530 Message-ID: <20240208084254.295289-4-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319774298175916 X-GMAIL-MSGID: 1790319774298175916 CSI cameras are controlled using I2C. On AM68 Starter Kit, this is routed to I2C-1, so enable the instance and the TCA9543 I2C switch on the bus. AM68 SK schematics: https://www.ti.com/lit/zip/sprr463 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. .../boot/dts/ti/k3-am68-sk-base-board.dts | 50 +++++++++++++++++++ 1 file changed, 50 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts index f48155dd16a3..d743f023cdd9 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -169,6 +169,13 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp3 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; }; &main_pmx0 { @@ -186,6 +193,13 @@ J721S2_IOPAD(0x0e4, PIN_INPUT, 0) /* (AE24) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J721S2_IOPAD(0x0ac, PIN_INPUT, 13) /* (AC25) MCASP0_AXR15.I2C1_SCL */ + J721S2_IOPAD(0x0b0, PIN_INPUT, 13) /* (AD26) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { pinctrl-single,pins = < J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ @@ -431,6 +445,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + status = "okay"; + + exp3: gpio@20 { + compatible = "ti,tca6408"; + reg = <0x20>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_SEL_FPC_EXPn", + "IO_EXP_CSI2_EXP_RSTz","CSI0_B_GPIO1", + "CSI1_B_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_i2c4 { status = "okay"; pinctrl-names = "default"; From patchwork Thu Feb 8 08:42:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198213 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp28189dyd; Thu, 8 Feb 2024 00:45:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIJcRjFmAL4U0MYTcVipBHThP15PGG5UAadhN+2EAbhz4CXcKMVhdg3yleGmMgUvnJsn2v X-Received: by 2002:a05:6870:41ce:b0:215:68:65c7 with SMTP id z14-20020a05687041ce00b00215006865c7mr8635180oac.12.1707381921915; Thu, 08 Feb 2024 00:45:21 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707381921; cv=pass; d=google.com; s=arc-20160816; b=ecj9JqY9W4AGr7cRWhZcXprXt4hse9zTgLBeBhzj9+vfyL4V2oSH71SBH1fVSZmdcu Pqj/AI5maA23pUcLvfMFMoLLn6o6Waxdn+76hytVgria4eaU2kZ+rgUm+327tbQ6LjpK toR5C11WtfAhMu+sMRDOcqf2Mi/4df7l98VzbHWmbShogQsMIcmfrTLpQtpeT/FIagea ZYMXdPu4+UI+gNVyvr/KeOfWVxhKWxaslkUd2GJfqJBylci08cmaZF5qc+dhwvYKtFuC fxOeja5DNAFHZcBHOhjuszsdNxDwodoUlHkh2jdQkRxtq+uwQiK8YelMzXmGnjTY6D6L yKXw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=XYSJWaZbQUZ4rWgrWFja9l/jgfj6GB45OK068onqk5E=; fh=FQDPSaimRe4eCMIbShxm9gxp916YiNs8KjyKOB34JnQ=; b=ZlbZt01VEGJARYrzvD++VTL/yczFmtnK6oDoMjUG6yqlWfXWxJis5ptq6Jarvrp3RQ 4xoxBDv7GpU5q7HY5WThuTvBp3MdgVB4LBC5AvNg0n1BDOUo2Nrmr3wevdyhAZRzvGQp 447C/JLcw8hm/vFVRqJCQHfeDoypzRdECm/ojU1bfcT1ZGYXv6/lIWutc5j8+UsBikPn 6c+/k5tJ8YDOBi11iUBJWQY+4OHg5b3gCzoYQFThIzaRmNHYtkCauGqMo85UrZOCfHfB Laawal90u+HV2yCxXaVHljr0eGJZskPbuGmqcCBdIuGvwMbbKLkYcEQzQhf5wgakgu/l GkFA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=jGlVQg1v; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57634-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57634-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCVUM98/Ziqrfa+EP41xVmrmCyAjrC2Ue3/vNREHP9Gr599ILlFqbQRnkFzY6bhHN6x9M1s2ZTuJ7I1fddigtTTN4mp5Dg== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshO097884; Thu, 8 Feb 2024 02:43:12 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 4/9] arm64: dts: ti: k3-am69-sk: Enable camera peripherals Date: Thu, 8 Feb 2024 14:12:49 +0530 Message-ID: <20240208084254.295289-5-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319706094926801 X-GMAIL-MSGID: 1790319706094926801 CSI cameras are controlled using I2C. On AM69 Starter Kit, this is routed to I2C-1, so enable the instance, TCA9543 I2C switch and the TCA6408 GPIO expander on the bus. AM69 SK has the CSI2RX routed to a MIPI CSI connector and to 22-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. AM69 SK schematics: https://www.ti.com/lit/zip/sprr466 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-am69-sk.dts | 51 +++++++++++++++++++++++++++ 1 file changed, 51 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 5f0a43a69333..46cf90bb3eb8 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -322,6 +322,14 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&exp2 1 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + }; + }; &main_pmx0 { @@ -341,6 +349,13 @@ J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ >; }; + main_i2c1_pins_default: main-i2c1-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0ac, PIN_INPUT_PULLUP, 13) /* (AE34) MCASP0_AXR15.I2C1_SCL */ + J784S4_IOPAD(0x0b0, PIN_INPUT_PULLUP, 13) /* (AL33) MCASP1_AXR3.I2C1_SDA */ + >; + }; + main_mmc1_pins_default: main-mmc1-default-pins { bootph-all; pinctrl-single,pins = < @@ -775,6 +790,42 @@ exp1: gpio@21 { }; }; +&main_i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&main_i2c1_pins_default>; + clock-frequency = <400000>; + status = "okay"; + + exp2: gpio@21 { + compatible = "ti,tca6408"; + reg = <0x21>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "CSI_VIO_SEL", "CSI_MUX_SEL_2", "CSI2_RSTz", + "IO_EXP_CAM0_GPIO1", "IO_EXP_CAM1_GPIO1"; + }; + + i2c-mux@70 { + compatible = "nxp,pca9543"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x70>; + + cam0_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + cam1_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + }; +}; + &main_sdhci0 { bootph-all; /* eMMC */ From patchwork Thu Feb 8 08:42:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198210 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp27680dyd; Thu, 8 Feb 2024 00:43:58 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCU2nGSk/sRb6SddYqJI5uh5yn93XsYdTPevf00p6vkfpQEmI8oHdsk/wNSyYgxfZwJpsMHPL+lybpoHsmSNlOq3Xf1e7g== X-Google-Smtp-Source: AGHT+IHfWgfKJit9kp/Kk07+/BqZ30GtYtevUhxdVLn+uMlIeeVBmINRkzmGw2TwajKOJftYkn26 X-Received: by 2002:a05:620a:223:b0:785:445f:41e9 with SMTP id u3-20020a05620a022300b00785445f41e9mr8667160qkm.14.1707381838010; Thu, 08 Feb 2024 00:43:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707381837; cv=pass; d=google.com; s=arc-20160816; b=AU+xY00yRqbrYcuun36dns7x5GLNl7Gf9taPc24Px1D6P9UPV022PjzFedsUVOsoKI uxhOgLlcaSDOaY0uMc9qQsWz0pNeI2iyB6AEQGy4FCMXPKjlT5fL85qYKST8dlxt7M+K AIPdEgtzz+ilCq7KQ5p3vsOgqjcL3/uy7CnH3gr5QviGwhKMprPQOSC2mVi5UeXjUa2f gMkkUJ4U+aPfvaKJem3zXqWxVVx6ATkbFa9MhMEOkxIpn/e6fzP4+mHOIP/W8CEWQJGX pHDFQPy6LJF/ggdlqIXkw1qGUKecwJojfd3IA8aVnSD+mbnj1EQ2dg2fDOcGGva+xzFX gTzQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=CM6cjKv4l0J1fKXCqPw6lqdbgZjYConNlvuzN5ok03E=; fh=FVh7WCl9kA4yuyugZl37cB1oeSLM3uVFqEnOxWdGQXk=; b=NQu+DoZurdEMc9OuCsIMCaUd2P1w3Z7HGetHoyWVKxYlzCdstJr7PfCjAZctyRzM0N vd4VCKaujik6tvEz6PL0IFr9CJWMtGvgCIGFozo65TQ878M1bKC6JASIMsphMKFCK+R8 ro4tvrTYUf0UWorV7guu2fTJ6tZam9+VFp5Vy9SRS4Dn1iteGLrNKUQUZaDrZBHiDRI6 i3tAw49X/VojOY2jAr9Fv+/81LcwP3NLNWBGvYhxDwGDXaP+LT/abaPHBsR4DmT3JCfj G07IiQoXy5mI8zoSadEiwiN5eU38WgqjP+Z3pCqUihhmtG0UUDr4rDJHhxKgWmDhgINB OlJw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=H4jkpW+T; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57632-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57632-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCWVgFZe0/+p0XVuhANKG2knGyy93yY1Rkp1g0EmNpmsmC/mFgCCWWumKVl+itwmBP2sUGVRqof2V0s32R0qTpIXKWnGgg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshP097884; Thu, 8 Feb 2024 02:43:16 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 5/9] arm64: dts: ti: k3-j721e-sk: Model CSI2RX connector mux Date: Thu, 8 Feb 2024 14:12:50 +0530 Message-ID: <20240208084254.295289-6-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319618182333179 X-GMAIL-MSGID: 1790319618182333179 J721E SK has the CSI2RX routed to a MIPI CSI connector and to 15-pin RPi camera connector through an analog mux with GPIO control, model that so that an overlay can control the mux state according to connected cameras. Also provide labels to the I2C mux bus instances so that a generic overlay can be used across multiple platforms. J721E SK schematics: https://www.ti.com/lit/zip/sprr438 Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: Update commit message with schematics. arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index 6950b1ff124f..5dbc85bc5038 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -286,6 +286,15 @@ tfp410_out: endpoint { }; }; }; + + csi_mux: mux-controller { + compatible = "gpio-mux"; + #mux-state-cells = <1>; + mux-gpios = <&main_gpio0 88 GPIO_ACTIVE_HIGH>; + idle-state = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&main_csi_mux_sel_pins_default>; + }; }; &main_pmx0 { @@ -352,6 +361,12 @@ J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */ >; }; + main_csi_mux_sel_pins_default: main-csi-mux-sel-default-pins { + pinctrl-single,pins = < + J721E_IOPAD(0x164, PIN_OUTPUT, 7) /* (V29) RGMII5_TD2 */ + >; + }; + dp0_pins_default: dp0-default-pins { pinctrl-single,pins = < J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ @@ -858,14 +873,14 @@ i2c-mux@70 { reg = <0x70>; /* CSI0 I2C */ - i2c@0 { + cam0_i2c: i2c@0 { #address-cells = <1>; #size-cells = <0>; reg = <0>; }; /* CSI1 I2C */ - i2c@1 { + cam1_i2c: i2c@1 { #address-cells = <1>; #size-cells = <0>; reg = <1>; From patchwork Thu Feb 8 08:42:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198212 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp28036dyd; Thu, 8 Feb 2024 00:44:59 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWUnmYdEf5t8YsEhar1DtPzEuOuTQMI2rzLT++krcVtcFiWgJLktDwWAl5kUfFHFQrPooKAGUBEvNmrryoSHxQCoDR9Eg== X-Google-Smtp-Source: AGHT+IEHaqvEtMkmb1pOjJK0i9VdtvITBEq22BsdbaT4bHYnbT6kWh4QHEbssOv094y/xsBvH95u X-Received: by 2002:a05:620a:4713:b0:783:ccc5:b2b4 with SMTP id bs19-20020a05620a471300b00783ccc5b2b4mr10866392qkb.71.1707381899025; Thu, 08 Feb 2024 00:44:59 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707381899; cv=pass; d=google.com; s=arc-20160816; b=OfzydFbEKzJzgw89dTLPtWKP8MkVnI6EPPkXr4zE0NB9S6Ce2M0vftzTjGN76LeGnP qi0dc/JM10j2Djy97jtoRPTUe5w8BkzME/tuVkp+qGN979qxEwtJMhhnQfDLod9PDLLU zXv1/mi3mAAAfDQ/Jx69IdE4oxwuM3vggMhXsnw4FzM0uFefD2FGeXdDWIddp2FdH9VS OBZUoctK8yu+inX8ZxOHmYvpYeWSApwzXvjeInvTo0tilQjNYwD+fE2VJqXMk1WjQ8Oi IZjGnQm3v6cpOgnxHZ3u4OLoedlpaJqk2kB7q2knORAoj9PYxiYQb7D9emmtDtJudyEo BYYg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7NqTnmRuEDsngPYCgeUqJWoO/hJRFSV+RfPuV9yubqw=; fh=XwAg6qpR08GpmNXaXdW5DO3BLlLbyQ+mOhwGEQuSA44=; b=EUbT0uVk3mrK6fCyhxGiBBBic5vvVG6yGmxQREc9nygiRALElb5ApTpRUsw/uq8cei TS8JHIrvce+GjLgFo/N3wTRpHVyQLCcKqyqYnAbUxqT8HfLisAlftpkkAY/1/JZRq1ck daOCH9Ye4+M1Co0FU6VD5VIhe1Kk6mNGiFNKC14qhSxStj3NmjxZ2EaeoqgmOTTxxn5n xVqEI1YKfcO9BByEi4ky84pby0UrI1hNusJSgztc//PsJdtL/XsrIDfq9XqrQGjxqMuH ltxw95G7n2hiEHyr/RaJF5xB7cdaFDlZ8gcJxRtDom/13NvR/RJ9uR9uAQaUL8PZiSAp o1sg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=xUC+M93Z; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-57635-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57635-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=2; AJvYcCUU1EtwBagqk3c+K9eFP9QYy6GXlo2sKW+ku8mFsK2kzKWak/QMsD8qpFlOzBwcKYNONHGLIpgWsU/r5pwab7tPBU07Aw== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshQ097884; Thu, 8 Feb 2024 02:43:21 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 6/9] arm64: dts: ti: k3-j721e-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:51 +0530 Message-ID: <20240208084254.295289-7-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319681952088648 X-GMAIL-MSGID: 1790319681952088648 J721E has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721E TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruil1 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 122 ++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 062a6fca5a31..8df1eed80996 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -572,6 +572,128 @@ main_timerio_output: pinctrl@104280 { pinctrl-single,function-mask = <0x0000001f>; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_udmap 0x4940>; + dma-names = "rx0"; + reg = <0x0 0x4500000 0x0 0x1000>; + power-domains = <&k3_pds 26 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4504000 0x0 0x1000>; + clocks = <&k3_clks 26 2>, <&k3_clks 26 0>, <&k3_clks 26 2>, + <&k3_clks 26 2>, <&k3_clks 26 3>, <&k3_clks 26 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_udmap 0x4960>; + dma-names = "rx0"; + reg = <0x0 0x4510000 0x0 0x1000>; + power-domains = <&k3_pds 27 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x0 0x4514000 0x0 0x1000>; + clocks = <&k3_clks 27 2>, <&k3_clks 27 0>, <&k3_clks 27 2>, + <&k3_clks 27 2>, <&k3_clks 27 3>, <&k3_clks 27 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4580000 0x0 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 147 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x0 0x4590000 0x0 0x1100>; + #phy-cells = <0>; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshR097884; Thu, 8 Feb 2024 02:43:25 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 7/9] arm64: dts: ti: k3-j721s2-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:52 +0530 Message-ID: <20240208084254.295289-8-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319796698092149 X-GMAIL-MSGID: 1790319796698092149 J721S2 has two CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J721S2 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J721S2 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj28 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 123 ++++++++++++++++++++- 1 file changed, 122 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi index dcaa4da0d678..a401e84a2eb2 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi @@ -1122,7 +1122,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <225>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { @@ -1233,6 +1232,128 @@ usb0: usb@6000000 { }; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + reg = <0x00 0x04500000 0x00 0x1000>; + power-domains = <&k3_pds 38 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x1000>; + clocks = <&k3_clks 38 3>, <&k3_clks 38 1>, <&k3_clks 38 3>, + <&k3_clks 38 3>, <&k3_clks 38 4>, <&k3_clks 38 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + reg = <0x00 0x04510000 0x00 0x1000>; + power-domains = <&k3_pds 39 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x1000>; + clocks = <&k3_clks 39 3>, <&k3_clks 39 1>, <&k3_clks 39 3>, + <&k3_clks 39 3>, <&k3_clks 39 4>, <&k3_clks 39 4>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 152 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x1100>; + #phy-cells = <0>; + power-domains = <&k3_pds 153 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + serdes_wiz0: wiz@5060000 { compatible = "ti,j721s2-wiz-10g"; #address-cells = <1>; From patchwork Thu Feb 8 08:42:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp28666dyd; Thu, 8 Feb 2024 00:46:23 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWQB5r3Fw1EVlg2tGm4tg9RdGS4zzEaHpWwxAdspK1TX1ywWBKhef2aIPIasaQBVuW9AA4x51TQk8JJhcXekSJrbRgDFw== X-Google-Smtp-Source: AGHT+IF270vurFaO1tje6KDqHCp819Fs6sNTMVMWodTiccL48oiEQ3UriEn51owxh6wzFETD1ptx X-Received: by 2002:a05:6359:1005:b0:178:fcd3:c316 with SMTP id ib5-20020a056359100500b00178fcd3c316mr5774576rwb.19.1707381983155; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshS097884; Thu, 8 Feb 2024 02:43:29 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 8/9] arm64: dts: ti: k3-j784s4-main: Add CSI2RX capture nodes Date: Thu, 8 Feb 2024 14:12:53 +0530 Message-ID: <20240208084254.295289-9-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790319770367792291 X-GMAIL-MSGID: 1790319770367792291 J784S4 has three CSI2RX capture subsystem featuring Cadence CSI2RX, DPHY and TI's pixel grabbing wrapper. Add nodes for the same and keep them disabled by default. J784S4 uses a dedicated BCDMA instance for CSI-RX traffic, so enable that as well. J784S4 TRM (Section 12.7 Camera Subsystem): https://www.ti.com/lit/zip/spruj52 Signed-off-by: Vaishnav Achath --- V1->V2: Update commit message with TRM. arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 183 ++++++++++++++++++++- 1 file changed, 182 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 3cb964982792..e3820ee52dbb 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -662,6 +662,188 @@ main_i2c6: i2c@2060000 { status = "disabled"; }; + ti_csi2rx0: ticsi2rx@4500000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x4940 0>; + dma-names = "rx0"; + reg = <0x00 0x04500000 0x00 0x00001000>; + power-domains = <&k3_pds 72 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx0: csi-bridge@4504000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04504000 0x00 0x00001000>; + clocks = <&k3_clks 72 2>, <&k3_clks 72 0>, <&k3_clks 72 2>, + <&k3_clks 72 2>, <&k3_clks 72 3>, <&k3_clks 72 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy0>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi0_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi0_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi0_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi0_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx1: ticsi2rx@4510000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x4960 0>; + dma-names = "rx0"; + reg = <0x00 0x04510000 0x00 0x1000>; + power-domains = <&k3_pds 73 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx1: csi-bridge@4514000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04514000 0x00 0x00001000>; + clocks = <&k3_clks 73 2>, <&k3_clks 73 0>, <&k3_clks 73 2>, + <&k3_clks 73 2>, <&k3_clks 73 3>, <&k3_clks 73 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy1>; + phy-names = "dphy"; + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi1_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi1_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi1_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi1_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + ti_csi2rx2: ticsi2rx@4520000 { + compatible = "ti,j721e-csi2rx-shim"; + dmas = <&main_bcdma_csi 0 0x4980 0>; + dma-names = "rx0"; + reg = <0x00 0x04520000 0x00 0x00001000>; + power-domains = <&k3_pds 74 TI_SCI_PD_EXCLUSIVE>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + cdns_csi2rx2: csi-bridge@4524000 { + compatible = "ti,j721e-csi2rx", "cdns,csi2rx"; + reg = <0x00 0x04524000 0x00 0x00001000>; + clocks = <&k3_clks 74 2>, <&k3_clks 74 0>, <&k3_clks 74 2>, + <&k3_clks 74 2>, <&k3_clks 74 3>, <&k3_clks 74 3>; + clock-names = "sys_clk", "p_clk", "pixel_if0_clk", + "pixel_if1_clk", "pixel_if2_clk", "pixel_if3_clk"; + phys = <&dphy2>; + phy-names = "dphy"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi2_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + csi2_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + csi2_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + csi2_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + csi2_port4: port@4 { + reg = <4>; + status = "disabled"; + }; + }; + }; + }; + + dphy0: phy@4580000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04580000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 212 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy1: phy@4590000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x04590000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 213 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + + dphy2: phy@45a0000 { + compatible = "cdns,dphy-rx"; + reg = <0x00 0x045a0000 0x00 0x00001100>; + #phy-cells = <0>; + power-domains = <&k3_pds 214 TI_SCI_PD_EXCLUSIVE>; + status = "disabled"; + }; + main_sdhci0: mmc@4f80000 { compatible = "ti,j721e-sdhci-8bit"; reg = <0x00 0x04f80000 0x00 0x1000>, @@ -1224,7 +1406,6 @@ main_bcdma_csi: dma-controller@311a0000 { ti,sci-dev-id = <281>; ti,sci-rm-range-rchan = <0x21>; ti,sci-rm-range-tchan = <0x22>; - status = "disabled"; }; cpts@310d0000 { From patchwork Thu Feb 8 08:42:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaishnav Achath X-Patchwork-Id: 198229 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp31210dyd; Thu, 8 Feb 2024 00:53:31 -0800 (PST) X-Forwarded-Encrypted: i=3; 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([10.24.69.142]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 4188gshT097884; Thu, 8 Feb 2024 02:43:33 -0600 From: Vaishnav Achath To: , , , , , CC: , , , , , , , , Subject: [PATCH v2 9/9] arm64: dts: ti: k3-j721e-sk: Add overlay for IMX219 Date: Thu, 8 Feb 2024 14:12:54 +0530 Message-ID: <20240208084254.295289-10-vaishnav.a@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240208084254.295289-1-vaishnav.a@ti.com> References: <20240208084254.295289-1-vaishnav.a@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790320219687134854 X-GMAIL-MSGID: 1790320219687134854 RPi v2 Camera (IMX219) is an 8MP camera that can be used with SK-AM69, J721E SK, and AM68 SK through the 22-pin CSI-RX connector. Add a reference overlay for dual IMX219 RPI camera v2 modules which can be used across AM68 SK, AM69 SK, TDA4VM SK boards that have a 15/22-pin FFC connector. Also enable build testing and symbols for all the three platforms. Signed-off-by: Vaishnav Achath Reviewed-by: Jai Luthra --- V1->V2: * Rename overlays to indicate first platform (j721e-sk) supported and dual camera. * Add missed build test, fix missing newline. arch/arm64/boot/dts/ti/Makefile | 13 ++ .../dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso | 125 ++++++++++++++++++ 2 files changed, 138 insertions(+) create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 4a570dffb638..e019efd3ce94 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -69,6 +69,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-gesi-exp-board.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-evm-pcie0-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j721e-sk-csi2-dual-imx219.dtbo # Boards with J721s2 SoC dtb-$(CONFIG_ARCH_K3) += k3-am68-sk-base-board.dtb @@ -106,8 +107,14 @@ k3-am642-tqma64xxl-mbax4xxl-sdcard-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-sdcard.dtbo k3-am642-tqma64xxl-mbax4xxl-wlan-dtbs := \ k3-am642-tqma64xxl-mbax4xxl.dtb k3-am64-tqma64xxl-mbax4xxl-wlan.dtbo +k3-am68-sk-base-board-csi2-dual-imx219-dtbs := k3-am68-sk-base-board.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo +k3-am69-sk-csi2-dual-imx219-dtbs := k3-am69-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo +k3-j721e-sk-csi2-dual-imx219-dtbs := k3-j721e-sk.dtb \ + k3-j721e-sk-csi2-dual-imx219.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ @@ -122,7 +129,10 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am62a7-sk-hdmi-audio.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ + k3-am68-sk-base-board-csi2-dual-imx219-dtbs \ + k3-am69-sk-csi2-dual-imx219-dtbs \ k3-j721e-evm-pcie0-ep.dtb \ + k3-j721e-sk-csi2-dual-imx219-dtbs \ k3-j721s2-evm-pcie1-ep.dtb # Enable support for device-tree overlays @@ -132,5 +142,8 @@ DTC_FLAGS_k3-am62-lp-sk += -@ DTC_FLAGS_k3-am62a7-sk += -@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ +DTC_FLAGS_k3-am68-sk-base-board += -@ +DTC_FLAGS_k3-am69-sk += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ +DTC_FLAGS_k3-j721e-sk += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso new file mode 100644 index 000000000000..65d7cefb6063 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk-csi2-dual-imx219.dtso @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT +/** + * DT Overlay for dual RPi Camera V2.1 (Sony IMX219) interfaced with CSI2 + * on J721E SK, AM68 SK or AM69-SK board. + * https://datasheets.raspberrypi.org/camera/camera-v2-schematic.pdf + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include "k3-pinctrl.h" + +&{/} { + clk_imx219_fixed: imx219-xclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; +}; + +&csi_mux { + idle-state = <1>; +}; + +/* CAM0 I2C */ +&cam0_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_0: imx219_0@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam0: endpoint { + remote-endpoint = <&csi2rx0_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +/* CAM1 I2C */ +&cam1_i2c { + #address-cells = <1>; + #size-cells = <0>; + imx219_1: imx219_1@10 { + compatible = "sony,imx219"; + reg = <0x10>; + + clocks = <&clk_imx219_fixed>; + clock-names = "xclk"; + + port { + csi2_cam1: endpoint { + remote-endpoint = <&csi2rx1_in_sensor>; + link-frequencies = /bits/ 64 <456000000>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + + +&cdns_csi2rx0 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi0_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx0_in_sensor: endpoint { + remote-endpoint = <&csi2_cam0>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&dphy0 { + status = "okay"; +}; + +&ti_csi2rx0 { + status = "okay"; +}; + +&cdns_csi2rx1 { + ports { + #address-cells = <1>; + #size-cells = <0>; + + csi1_port0: port@0 { + reg = <0>; + status = "okay"; + + csi2rx1_in_sensor: endpoint { + remote-endpoint = <&csi2_cam1>; + bus-type = <4>; /* CSI2 DPHY. */ + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&dphy1 { + status = "okay"; +}; + +&ti_csi2rx1 { + status = "okay"; +};