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bh=l4UY2L4RJrFs6qSEBykdb5P7iOGl7l18XZf5QdzVkjg=; b=DOXG+Ul7caOJfG1bn08wNRiVNZ0BmKy8siQayh8vL7aeed4QuFWIT06Z Vkd+h083Tn1i+leDuQ0T42oWZZgnEUK1qeYiEUQO+VuoUwCE2hcNdxCju 5SmtjfWryCOryBlAL2rq2S4n1bJT1bVf2CjanGynH3kfPNMDGHAY2yTgc o3DvIG+VxrvNtfKRpNY0+I1rnzMqnRBbhgP25OKxwskzdXnd4Ux/Ly9qp AgaxtBSgkyxSWEopE1TTAQbx1r+1lYOoueFgcwnsrkGajKocqJmy14eNu FHgtwZnkxmPS33MigpZBQRlVrESontfdt6+LvFE7lrezrqXK6Yr/EGA/D A==; X-IronPort-AV: E=McAfee;i="6600,9927,10977"; a="12242635" X-IronPort-AV: E=Sophos;i="6.05,252,1701158400"; d="scan'208";a="12242635" Received: from fmviesa003.fm.intel.com ([10.60.135.143]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2024 23:45:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,252,1701158400"; d="scan'208";a="6195648" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by fmviesa003-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 07 Feb 2024 23:45:16 -0800 From: Lucas De Marchi To: Yury Norov Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andy Shevchenko , Jani Nikula , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Lucas De Marchi , Jani Nikula Subject: [PATCH v3 1/3] bits: introduce fixed-type genmasks Date: Wed, 7 Feb 2024 23:45:19 -0800 Message-ID: <20240208074521.577076-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240208074521.577076-1-lucas.demarchi@intel.com> References: <20240208074521.577076-1-lucas.demarchi@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790316015819607114 X-GMAIL-MSGID: 1790316015819607114 From: Yury Norov Generalize __GENMASK() to support different types, and implement fixed-types versions of GENMASK() based on it. The fixed-type version allows more strict checks to the min/max values accepted, which is useful for defining registers like implemented by i915 and xe drivers with their REG_GENMASK*() macros. The strict checks rely on shift-count-overflow compiler check to fail the build if a number outside of the range allowed is passed. Example: #define FOO_MASK GENMASK_U32(33, 4) will generate a warning like: ../include/linux/bits.h:41:31: error: left shift count >= width of type [-Werror=shift-count-overflow] 41 | (((t)~0ULL - ((t)(1) << (l)) + 1) & \ | ^~ Signed-off-by: Yury Norov Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula Reviewed-by: Andi Shyti Signed-off-by: Yury Norov Acked-by: Jani Nikula Reviewed-by: Andi Shyti Signed-off-by: Lucas De Marchi --- include/linux/bitops.h | 1 - include/linux/bits.h | 32 ++++++++++++++++++++++---------- 2 files changed, 22 insertions(+), 11 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 2ba557e067fe..1db50c69cfdb 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -15,7 +15,6 @@ # define aligned_byte_mask(n) (~0xffUL << (BITS_PER_LONG - 8 - 8*(n))) #endif -#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) #define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64)) #define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32)) diff --git a/include/linux/bits.h b/include/linux/bits.h index 7c0cf5031abe..bd56f32de44e 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -6,6 +6,8 @@ #include #include +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) + #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) @@ -30,16 +32,26 @@ #define GENMASK_INPUT_CHECK(h, l) 0 #endif -#define __GENMASK(h, l) \ - (((~UL(0)) - (UL(1) << (l)) + 1) & \ - (~UL(0) >> (BITS_PER_LONG - 1 - (h)))) -#define GENMASK(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) +/* + * Generate a mask for the specified type @t. Additional checks are made to + * guarantee the value returned fits in that type, relying on + * shift-count-overflow compiler check to detect incompatible arguments. + * For example, all these create build errors or warnings: + * + * - GENMASK(15, 20): wrong argument order + * - GENMASK(72, 15): doesn't fit unsigned long + * - GENMASK_U32(33, 15): doesn't fit in a u32 + */ +#define __GENMASK(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) + \ + (((t)~0ULL - ((t)(1) << (l)) + 1) & \ + ((t)~0ULL >> (BITS_PER_TYPE(t) - 1 - (h))))) -#define __GENMASK_ULL(h, l) \ - (((~ULL(0)) - (ULL(1) << (l)) + 1) & \ - (~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h)))) -#define GENMASK_ULL(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) +#define GENMASK(h, l) __GENMASK(unsigned long, h, l) +#define GENMASK_ULL(h, l) __GENMASK(unsigned long long, h, l) +#define GENMASK_U8(h, l) __GENMASK(u8, h, l) +#define GENMASK_U16(h, l) __GENMASK(u16, h, l) +#define GENMASK_U32(h, l) __GENMASK(u32, h, l) +#define GENMASK_U64(h, l) __GENMASK(u64, h, l) #endif /* __LINUX_BITS_H */ From patchwork Thu Feb 8 07:45:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 198193 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp6890dyd; Wed, 7 Feb 2024 23:46:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnNMRERVh83XloDhNo8nuecFwzxcs02B/Q2dG8ig/0svGMgNLHdSPTPXFdpI9zj+u388dH X-Received: by 2002:a17:90a:8a88:b0:296:1127:ceca with SMTP id x8-20020a17090a8a8800b002961127cecamr5237170pjn.6.1707378402059; Wed, 07 Feb 2024 23:46:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707378402; cv=pass; d=google.com; s=arc-20160816; b=olgTG6n5wMhivPm0603LPkQRq66o+fX/EqiO9R6kmgKkwnWXvK/TIX6CjmWgfGuIgP FdTL8p0KfA8bniqCjiaESw4F6PkBLzishtSbxyUeJRulSpCQEuGIx2EJ9W/530AGN1eG bz3d6s0rnJ4+Ynsq1Q5oAI2QG8cm12bkn4MS2EMGtHpJaneSM6wjg/J6Df5lUkcMgACs CN/qFrzyaRCXSFmM+rc9FFsHQwYPyz6ICgUYdq9VfowiFO4SPkTkDXkuBWTgLFVCC3Q0 SvhhUTWaD9VHPH+fa5QHzdaY90IefK6kd/DDC4mxCqqlD07xtt1bMZv/lRsyMJnSOcXH Y+AQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=LNrr4e6yhnS9cHI63uaNXQu15/R9jLdZ9pZ5uJAIDSs=; fh=wzK+0GodD50Az3W5DvrQGlq3EZ4ZY83B0nV13NnBn9s=; b=gBcc75my2GwV9RBX7WfDgLKLjdI4qaK5Tiv3dXIyefdUO1re23cVirBbJb47XfNvQl ckOhyggAwY5R6zHI2ZWq6NEpit450AsvBuoVPtoxw40u4PT1wD6LLB5+otteOQ2txlkg 4V6vix37YFLJKv7doftcdISDHefIe6LofabVKY2EC56O1IZ4xmWCORIA0NGlg1a5CDS5 NN3JynjjHsrzcSxaxGCXE+uVNNQdafVXkKMXtY+SOUiWEpFfmjrDkJwhfYxZU5ZqcC2P cSKL9SwjTDp/BLpSkQvqXY9I3bSVaHVvEn8wKoQnrXQPhV9uSm1dC+kDctUS7vV00J0a CzsQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="JIjCUp/O"; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-57569-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57569-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCXcLEaqFZpoM8/0CCY4I5Xevs71ZVCteRRGysL2SQ1yK0NNiMsLmW0msyrFpnIfcp1mPyePuQbwKld/UEzbt+ZTapE0sA== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula --- include/linux/bits.h | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/include/linux/bits.h b/include/linux/bits.h index bd56f32de44e..811846ce110e 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -24,12 +24,16 @@ #define GENMASK_INPUT_CHECK(h, l) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ __is_constexpr((l) > (h)), (l) > (h), 0))) +#define BIT_INPUT_CHECK(type, b) \ + ((BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ + __is_constexpr(b), (b) >= BITS_PER_TYPE(type), 0)))) #else /* * BUILD_BUG_ON_ZERO is not available in h files included from asm files, * disable the input check if that is the case. */ #define GENMASK_INPUT_CHECK(h, l) 0 +#define BIT_INPUT_CHECK(type, b) 0 #endif /* @@ -54,4 +58,17 @@ #define GENMASK_U32(h, l) __GENMASK(u32, h, l) #define GENMASK_U64(h, l) __GENMASK(u64, h, l) +/* + * Fixed-type variants of BIT(), with additional checks like __GENMASK(). The + * following examples generate compiler warnings due to shift-count-overflow: + * + * - BIT_U8(8) + * - BIT_U32(-1) + * - BIT_U32(40) + */ +#define BIT_U8(b) ((u8)(BIT_INPUT_CHECK(u8, b) + BIT(b))) +#define BIT_U16(b) ((u16)(BIT_INPUT_CHECK(u16, b) + BIT(b))) +#define BIT_U32(b) ((u32)(BIT_INPUT_CHECK(u32, b) + BIT(b))) +#define BIT_U64(b) ((u64)(BIT_INPUT_CHECK(u64, b) + BIT(b))) + #endif /* __LINUX_BITS_H */ From patchwork Thu Feb 8 07:45:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 198195 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:50ea:b0:106:860b:bbdd with SMTP id r10csp7013dyd; Wed, 7 Feb 2024 23:47:04 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCXuCX+5iq+cGaWxuqgPmPx6FawtcxSiBrvb9taSFgGc/JNsrYCETpE6tFJSGX4jDrzNeJavlmX4vqhHdF3lvLDzKAutAQ== X-Google-Smtp-Source: AGHT+IEK/wBG448KFlRx0Phg+Gd16qkZpVb2WRclzKz7VZ1YlXV+DAdNb/FGitIJ32l05jC1BJXo X-Received: by 2002:a17:902:e74b:b0:1d7:17e6:44fb with SMTP id p11-20020a170902e74b00b001d717e644fbmr3332267plf.32.1707378424718; Wed, 07 Feb 2024 23:47:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707378424; cv=pass; d=google.com; s=arc-20160816; b=urYDHy4nH4lHpSlgW218tLAzgZleb8GEvjCe3kuSiUaFJNNE0ZE2dccdvzgtENy52e TqRw3nwTKHj8f5hL3OJ8YQYiHfptPPKnvolwxLkS2CDzQpr5pDuK/1Rx2cnIm8o1Gjmo g4dHd+KBD4UL0Ak/z/h9tDI3OLXfOEQoS7m9Hy3rpJZ3KOm44+O6FH8/ootfLmgo11u7 Z4dpweZ1zH8OJsO305Kjlhy6qWellGMiArfn8NWeZgQuYraP6WqpjkVhXQoNSYWXOulI h7nf6rdmJeoOn7A/8Av8BDLh2KObFO/FVN0wy6GXgBukl7yMQ4fEHTZH7mtqrhZrcQdJ 30yg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=uF3Fd/RSbvck3SuZVx8V+VyC1oX8TF3WaEcygWdN9nY=; fh=bb2kkUd8ZiLpx8uNyCTKnXvB8HPC//sFjy6DF9ACoJU=; b=LPHS/9QnVy2JT/oqNLut16uPW97FmpbrzDz/q3wVCsPNNfBEAT7TxHqgpp5qunoE5x Ofce/PQznowMsx1/NJY9IXgQv1K/GX21qHqhP+LvzV+NC7R0z6Vp3zFx6z2UnawuqsM/ 708WcXcBhCD22PEi+GEjP5YjnGMohePOw8Z8ps3mJTpV25GXJeMC9lrr1GPtPjuS0oqH Tly4PCgGt5LS/R8LZ9Yo9T9Bavw6jWROy6v6FclwP/lbS4KDHywspFXtqWrqOjHv/CFz +rbvLLnaBZDgPuufvfaWMW2OF/9bVnpSYJw/bGtJ8lonSeVumusWIEXNvjmNWk6bcJaz msNg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=mPo6Y5O1; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-57570-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-57570-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCVtb361fh/duGjKC8LiSRjsE5iweS6feFRgOhPBQ5niLmwVKQF5/dYUS4iAQC9TtLLbY296kruS2ZF3DN8HFQ38pmuV/w== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Converting each driver to use the generic macros are left for later, when/if other driver-specific macros are also generalized. Signed-off-by: Lucas De Marchi Acked-by: Jani Nikula --- drivers/gpu/drm/i915/i915_reg_defs.h | 108 +++------------------------ 1 file changed, 11 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index a685db1e815d..52f99eb96f86 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -9,76 +9,19 @@ #include #include -/** - * REG_BIT() - Prepare a u32 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u32, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT(__n) \ - ((u32)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 31)))) - -/** - * REG_BIT8() - Prepare a u8 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u8, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT8(__n) \ - ((u8)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 7)))) - -/** - * REG_GENMASK() - Prepare a continuous u32 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u32, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK(__high, __low) \ - ((u32)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) - -/** - * REG_GENMASK64() - Prepare a continuous u64 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK_ULL() to force u64, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. +/* + * Wrappers over the generic BIT_* and GENMASK_* implementations, + * for compatibility reasons with previous implementation */ -#define REG_GENMASK64(__high, __low) \ - ((u64)(GENMASK_ULL(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 63 || (__low) > (__high))))) +#define REG_GENMASK(__high, __low) GENMASK_U32(__high, __low) +#define REG_GENMASK64(__high, __low) GENMASK_U64(__high, __low) +#define REG_GENMASK16(__high, __low) GENMASK_U16(__high, __low) +#define REG_GENMASK8(__high, __low) GENMASK_U8(__high, __low) -/** - * REG_GENMASK8() - Prepare a continuous u8 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u8, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK8(__high, __low) \ - ((u8)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 7 || (__low) > (__high))))) +#define REG_BIT(__n) BIT_U32(__n) +#define REG_BIT64(__n) BIT_U64(__n) +#define REG_BIT16(__n) BIT_U16(__n) +#define REG_BIT8(__n) BIT_U8(__n) /* * Local integer constant expression version of is_power_of_2(). @@ -143,35 +86,6 @@ */ #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) -/** - * REG_BIT16() - Prepare a u16 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u16, with compile time - * checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT16(__n) \ - ((u16)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 15)))) - -/** - * REG_GENMASK16() - Prepare a continuous u8 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u16, with compile time - * checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK16(__high, __low) \ - ((u16)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 15 || (__low) > (__high))))) /** * REG_FIELD_PREP16() - Prepare a u16 bitfield value