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Wed, 7 Feb 2024 09:04:37 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH02.marvell.com (10.69.176.39) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Feb 2024 09:04:37 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 79E575E6872; Wed, 7 Feb 2024 09:04:35 -0800 (PST) From: Elad Nachman To: , , , , CC: Subject: [PATCH 1/2] mmc: xenon: fix PHY init clock stability Date: Wed, 7 Feb 2024 19:04:24 +0200 Message-ID: <20240207170425.478558-2-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207170425.478558-1-enachman@marvell.com> References: <20240207170425.478558-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: eLsqMvuXhBdW4CBRLjB6D6IUbis2TMyX X-Proofpoint-GUID: eLsqMvuXhBdW4CBRLjB6D6IUbis2TMyX X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-07_08,2024-02-07_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790261934607153517 X-GMAIL-MSGID: 1790265341429238931 From: Elad Nachman Each time SD/mmc phy is initialized, at times, in some of the attempts, phy fails to completes its initialization which results into timeout error. Per the HW spec, it is a pre-requisite to ensure a stable SD clock before a phy initialization is attempted. Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index 8cf3a375de65..4e99197b62c3 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -216,6 +216,24 @@ static int xenon_alloc_emmc_phy(struct sdhci_host *host) return 0; } +static int xenon_check_stability_internal_clk(struct sdhci_host *host) +{ + u32 reg; + ktime_t timeout; + + /* Wait max 20 ms */ + timeout = ktime_add_ms(ktime_get(), 20); + while (!((reg = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) + & SDHCI_CLOCK_INT_STABLE)) { + if (ktime_after(ktime_get(), timeout)) { + dev_err(mmc_dev(host->mmc), "phy_init: Internal clock never stabilized.\n"); + return -ETIMEDOUT; + } + usleep_range(900, 1100); + } + return 0; +} + /* * eMMC 5.0/5.1 PHY init/re-init. * eMMC PHY init should be executed after: @@ -232,6 +250,11 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); struct xenon_emmc_phy_regs *phy_regs = priv->emmc_phy_regs; + int ret = xenon_check_stability_internal_clk(host); + + if (ret) + return ret; + reg = sdhci_readl(host, phy_regs->timing_adj); reg |= XENON_PHY_INITIALIZAION; sdhci_writel(host, reg, phy_regs->timing_adj); From patchwork Wed Feb 7 17:04:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Elad Nachman X-Patchwork-Id: 198093 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2498396dyb; Wed, 7 Feb 2024 12:54:56 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWq1y6nIX+xgwxsHQ0QnBrvz0N15oJ0IrikexRfcZYIbhXx5xIPwM7+ANx/DgqoB9obwdXh0iae9pZaEfE6gfsTvfAjhQ== X-Google-Smtp-Source: AGHT+IHvZUXmJ29Ipw4K3KuS3tEwxiYhNfs52NCC59gvKOKq0VSclKRyMoa1IGASSABvavNlkMSP X-Received: by 2002:a17:90a:e2d5:b0:28f:f249:3c4a with SMTP id fr21-20020a17090ae2d500b0028ff2493c4amr1045746pjb.19.1707339296690; Wed, 07 Feb 2024 12:54:56 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707339296; cv=pass; d=google.com; s=arc-20160816; b=hS9QyUbVGXMkMMlRzsTYP2q1Q4G0Xu0S2f/dYSlJkF9+VLdR7UJLtdEraseXquSfbp CVJ6XZ5o6HCO1PxbJpuje0UvQbPh9rYk/dGcf9Ox//7Cyt5xEysjmV0noN0iFMH72eTb FQ7o09PpTZ/am93k/st+6glbFlmNdZiybuwDYl4W0C/7NDaV/yQ5g1sUcS82KyAxQEVP 4ayt3HEu1IF0+yxUFA4UTaIVqbhlTRP8sGnZ+4TRuDthvT7DVZtmSniomaM2L51XrMo9 +hdLaRn8gkHsGv9dv1StYNIefzwweZwAIsI5sstHh4ZwI6/JMP2xawl4GmqR+TjcvbvR JTXA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Juhy42j2iKDK9LY7bpXPn8t4rHNyPP+bAYrPjTI7bDg=; fh=a6vblQwzbJZOG/gigMhf/zs2STQw/vZvSD3IH96O554=; b=ymIofRViRlD/zd+nTtOlSmuEO5xGb+bYFXTS4dGup86IFBlQE5q/xjrWPg3Z238u0Q 3Ah4mOfpxK+P4l4CgdU+VZkxeORWUyqhlKyCUaPPvtDkvnfPcNg7+AWxKbpQDm41PumL EsPzDM+hl2SeKrjw5zYfPiqo6b0ANbJ3ddzsVZzHKjd2KOJ7V8b1NeumE+nQsi2IQ7HQ 1+hWAay+dExuFiJKB3wRb0FuIM1HJXVwl0LKrAclmnubhMJxRiVbMD2hzP891F1Wobs5 lIdQFAoCyRgIE2ryiZwt5NC9/Hn/WYT2HVZU0ZVln5FJWlQgHMnx0uaR9DpDK7qbPakx kQdg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@marvell.com header.s=pfpt0220 header.b=jUCjXNXa; arc=pass (i=1 dkim=pass dkdomain=marvell.com dmarc=pass fromdomain=marvell.com); spf=pass (google.com: domain of linux-kernel+bounces-56800-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56800-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=REJECT dis=NONE) header.from=marvell.com X-Forwarded-Encrypted: i=2; AJvYcCUwMdxVYYMzArE2KnRW2LL27ITEMPQUWPpSrPSgzLU/EFPO/QeVHfowk0DtlndTRROfsZ2aZUwI6i9NIL8g/XKNdemnbQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 7 Feb 2024 09:04:39 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH01.marvell.com (10.69.176.38) with Microsoft SMTP Server id 15.0.1497.48 via Frontend Transport; Wed, 7 Feb 2024 09:04:39 -0800 Received: from dc3lp-swdev041.marvell.com (dc3lp-swdev041.marvell.com [10.6.60.191]) by maili.marvell.com (Postfix) with ESMTP id 813A85E6870; Wed, 7 Feb 2024 09:04:37 -0800 (PST) From: Elad Nachman To: , , , , CC: Subject: [PATCH 2/2] mmc: xenon: add timeout for PHY init complete Date: Wed, 7 Feb 2024 19:04:25 +0200 Message-ID: <20240207170425.478558-3-enachman@marvell.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207170425.478558-1-enachman@marvell.com> References: <20240207170425.478558-1-enachman@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Proofpoint-ORIG-GUID: 8eXC_kRdVYf-7b5cAH5nsEFoT0Z3Pd5W X-Proofpoint-GUID: 8eXC_kRdVYf-7b5cAH5nsEFoT0Z3Pd5W X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.1011,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-02-07_08,2024-02-07_01,2023-05-22_02 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790261862894477209 X-GMAIL-MSGID: 1790275010016338906 From: Elad Nachman AC5X spec says PHY init complete bit must be polled until zero. We see cases in which timeout can take longer than the standard calculation on AC5X, which is expected following the spec comment above. According to the spec, we must wait as long as it takes for that bit to toggle on AC5X. Cap that with 100 delay loops so we won't get stuck forever. Signed-off-by: Elad Nachman --- drivers/mmc/host/sdhci-xenon-phy.c | 31 ++++++++++++++++++++++++------ 1 file changed, 25 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-xenon-phy.c b/drivers/mmc/host/sdhci-xenon-phy.c index 4e99197b62c3..f551a9e31772 100644 --- a/drivers/mmc/host/sdhci-xenon-phy.c +++ b/drivers/mmc/host/sdhci-xenon-phy.c @@ -109,6 +109,8 @@ #define XENON_EMMC_PHY_LOGIC_TIMING_ADJUST (XENON_EMMC_PHY_REG_BASE + 0x18) #define XENON_LOGIC_TIMING_VALUE 0x00AA8977 +#define XENON_MAX_PHY_TIMEOUT_LOOPS 100 + /* * List offset of PHY registers and some special register values * in eMMC PHY 5.0 or eMMC PHY 5.1 @@ -244,7 +246,7 @@ static int xenon_check_stability_internal_clk(struct sdhci_host *host) */ static int xenon_emmc_phy_init(struct sdhci_host *host) { - u32 reg; + u32 reg, retry; u32 wait, clock; struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct xenon_priv *priv = sdhci_pltfm_priv(pltfm_host); @@ -282,14 +284,31 @@ static int xenon_emmc_phy_init(struct sdhci_host *host) /* get the wait time */ wait /= clock; wait++; - /* wait for host eMMC PHY init completes */ - udelay(wait); - reg = sdhci_readl(host, phy_regs->timing_adj); - reg &= XENON_PHY_INITIALIZAION; + /* + * AC5X spec says bit must be polled until zero. + * We see cases in which timeout can take longer + * than the standard calculation on AC5X, which is + * expected following the spec comment above. + * According to the spec, we must wait as long as + * it takes for that bit to toggle on AC5X. + * Cap that with 100 delay loops so we won't get + * stuck here forever: + */ + + retry = XENON_MAX_PHY_TIMEOUT_LOOPS; + + do { + /* wait for host eMMC PHY init completes */ + udelay(wait); + + reg = sdhci_readl(host, phy_regs->timing_adj); + reg &= XENON_PHY_INITIALIZAION; + } while (reg && retry--); + if (reg) { dev_err(mmc_dev(host->mmc), "eMMC PHY init cannot complete after %d us\n", - wait); + wait * XENON_MAX_PHY_TIMEOUT_LOOPS); return -ETIMEDOUT; }