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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b0040ec8330c8asm4983260wmq.39.2024.02.07.03.15.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:15:19 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v2 1/4] spi: dt-bindings: samsung: add google,gs101-spi compatible Date: Wed, 7 Feb 2024 11:15:13 +0000 Message-ID: <20240207111516.2563218-2-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240207111516.2563218-1-tudor.ambarus@linaro.org> References: <20240207111516.2563218-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790238635234408284 X-GMAIL-MSGID: 1790238635234408284 Add "google,gs101-spi" dedicated compatible for representing SPI of Google GS101 SoC. Reviewed-by: Sam Protsenko Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Acked-by: Andi Shyti Signed-off-by: Tudor Ambarus --- Documentation/devicetree/bindings/spi/samsung,spi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index f71099852653..2f0a0835ecfb 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -17,6 +17,7 @@ properties: compatible: oneOf: - enum: + - google,gs101-spi - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 From patchwork Wed Feb 7 11:15:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 197858 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2154453dyb; Wed, 7 Feb 2024 03:17:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IF3iD9kXwISjQp879BI6fVoLgwBA7xSU3y81shsoj049cfcvmZJhXgX2Gq9qwnQkB5dAyx/ X-Received: by 2002:a17:906:314a:b0:a38:35c5:76f0 with SMTP id e10-20020a170906314a00b00a3835c576f0mr3253366eje.11.1707304650992; Wed, 07 Feb 2024 03:17:30 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707304650; cv=pass; d=google.com; s=arc-20160816; b=aY5MIRSMRoLWE5Ry6p7y4k1pYOSMDpXlsaU5IQ4szo52Uun0VaiHymdP5CHvvcaXPK 1dB5hk/H+zNYIZ9wPU0ujYxJqsobMoYz+lwyEBpOmAtAP3iycdRgznT3FTffnzVJ4Tyc sA4Bwe+7lQzkRHg/iHYpO6ht49OUBDmma0JS/4+qwwldw61Li+Q50c8+6MlBrJkv3S2W RWDGlZc1egSUV31fQHkHCdW4kuJ3BCR2nDDJ/C2B2laOV7gwvy0Tdk6UxUQgklINJVJG wRy8CWX5xpOAtAJZoCsiw8sBR7y1SF/c7e2BlIlgx61MmTdf35kcmshS9x7zevhgloUg KYZA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=7t39Yf75iI8Zz7Da0gHWY0hS9D040rpkcEYE36N/CE8=; fh=MZtFA2qdN7MFC9PCItDbcFi8u18s7Xfw8vt9WXEBDVU=; b=IbFH6JRRSlUfod8bnJoSrRQ0VPD6zb2ejIRM2XGP9msbxV1WpvbE91FuCAhaHqKkp/ TZGXkkOLU2Z9HXQFuDDl8ozVUGQN/L4hkjjJzwTVZGvelquTOY+nD8q20zAtahpwuijM 1MwL3xfNsyAnq3s7+AzDl9FrsPqebgZ1chL8z1ysc/F2UaHvtBAFV+zHLNGXwTgwgh41 SKxBY1I7RUUImLDBwPrUofaewtcy3UagXM2vOLMurYS5naDUeQq4YWo/2A1tSv1z9NlX mkKbuN8wRm6jsDq1JHDZq1N/YQIpqV72Nf1g05WyUYkC+btO97W09re0PqJRumiLMXSk Zl5w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ltc5FP+e; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-56374-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56374-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCUrW8/VsmPvA+t8uBNfbee+35oToMq2JrdoKpybJPqN+QaPVQ6ETB636uxuZBgZDNvnc3icWRAXRuZKfV9w615UGyoFYA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b0040ec8330c8asm4983260wmq.39.2024.02.07.03.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:15:20 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v2 2/4] spi: s3c64xx: prepare for a different flavor of iowrite rep Date: Wed, 7 Feb 2024 11:15:14 +0000 Message-ID: <20240207111516.2563218-3-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240207111516.2563218-1-tudor.ambarus@linaro.org> References: <20240207111516.2563218-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790238681984572032 X-GMAIL-MSGID: 1790238681984572032 There are SoCs (gs101) that allow only 32 bit register accesses. As the requirement is rare enough, for those SoCs we'll open code in the driver some s3c64xx_iowrite{8,16}_32_rep() accessors. Prepare for such addition. Suggested-by: Sam Protsenko Signed-off-by: Tudor Ambarus Reviewed-by: Sam Protsenko --- drivers/spi/spi-s3c64xx.c | 35 +++++++++++++++++++++-------------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 7f7eb8f742e4..eb79c6e4f509 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -414,6 +414,26 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, } +static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, + struct spi_transfer *xfer) +{ + void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; + const void *buf = xfer->tx_buf; + unsigned int len = xfer->len; + + switch (sdd->cur_bpw) { + case 32: + iowrite32_rep(addr, buf, len / 4); + break; + case 16: + iowrite16_rep(addr, buf, len / 2); + break; + default: + iowrite8_rep(addr, buf, len); + break; + } +} + static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer, int dma_mode) { @@ -447,20 +467,7 @@ static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg); } else { - switch (sdd->cur_bpw) { - case 32: - iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 4); - break; - case 16: - iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len / 2); - break; - default: - iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, - xfer->tx_buf, xfer->len); - break; - } + s3c64xx_iowrite_rep(sdd, xfer); } } From patchwork Wed Feb 7 11:15:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 197857 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2154360dyb; Wed, 7 Feb 2024 03:17:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFnXrVazp167o3puEtQiHJlx1nBNN1CaHtKTt334ytwBvXVAqkdUq3gWTJzoYQ3MqKUO2/b X-Received: by 2002:a9d:6f19:0:b0:6e1:140d:2747 with SMTP id n25-20020a9d6f19000000b006e1140d2747mr5725673otq.21.1707304638403; Wed, 07 Feb 2024 03:17:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707304638; cv=pass; d=google.com; s=arc-20160816; b=zn7IVW8JudUK8Ovo4HzvBI/ThNR5T3oaYJbPwKRzchI9X+MmyW8cWphpVeligzqp0P vHx0B0wharXDyUpnYFzxQT7V4dBvUyNpTSaHLWxDsj7lTy5XTHH4IJM+C5rwOoydCXbt miX32lIhdwF5ObbkxnZLrdgc86bUZw3jta3UuFW6/MCe//5D7OK9sowKirDZNQZAcTUj hWLlDf3pxTOxsDl5gKW2BxgcZO6O5LHW17mVrMnhUuRgBTrALPhYt2y2Y5hNdYK6NfpS YFRAb+pPY2mgx1gLiLuPKZoFQhqhvjdedUCsoJ09JVeGwBFR+VNmOUy24TLFR4V3iVfv KnyQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=D8XcmWMrPCGgSQiW78AbqKZG3dzV30LWYZrn5ta2nWk=; fh=bcOkxk0XwfsrO0VuKBq0WSKefsG5IZ7pY/wZNYwr2vg=; b=k2Aku/jLurxeCsgxMMJRHLuzUTKVzGHo/6rK7h91BrL8twxtKcg6lpHVjKsVwAQbsz Kw7p3bD31nmQXiEmE+I4F3tlKwfs+9I/7KGf7Iue949kpBg0U4b4sdhZRe07T4xyp6yV D/h7m3ZOjx0R8pJWcDI7Swqt0dYNN91uNHFUnnI1BXq8UGmYaURkWkE76WCMY4EArYk2 Pl7gxMfvpyxwMD9hHUvx28x4mPdWjCKWJS5qqIHjbn3A7Y1pDWHWMuUAKQbIFyOz5fbK wb/IW6TrWJA2PLLhDuaOTw6+0XfcqmOpgoT9/UXnD0xl0ze2XBgAu4HXpNTDqcBbjetB NDHA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wJvdKYd8; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-56375-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56375-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCUdql0eMGS0ohixAqlaTDbNKZGj0Y+Z65MVIlQHv6DOl2KFhFWC8YJd65bb6UJJorkPpkIaoF6nkCK9HLnaDdkCeHU2NA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b0040ec8330c8asm4983260wmq.39.2024.02.07.03.15.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:15:20 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v2 3/4] spi: s3c64xx: add s3c64xx_iowrite{8,16}_32_rep accessors Date: Wed, 7 Feb 2024 11:15:15 +0000 Message-ID: <20240207111516.2563218-4-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240207111516.2563218-1-tudor.ambarus@linaro.org> References: <20240207111516.2563218-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790238668477306383 X-GMAIL-MSGID: 1790238668477306383 Allow SoCs that require 32 bits register accesses to write data in chunks of 8 or 16 bits. One SoC that requires 32 bit register accesses is the google gs101. The operation is rare, thus open code it in the driver rather than making it generic (through asm-generic/io.h). Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index eb79c6e4f509..014fcc933c90 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -142,6 +142,7 @@ struct s3c64xx_spi_dma_data { * prescaler unit. * @clk_ioclk: True if clock is present on this device * @has_loopback: True if loopback mode can be supported + * @use_32bit_io: True if the SoC allows only 32-bit register accesses. * * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but * differ in some aspects such as the size of the fifo and spi bus clock @@ -158,6 +159,7 @@ struct s3c64xx_spi_port_config { bool clk_from_cmu; bool clk_ioclk; bool has_loopback; + bool use_32bit_io; }; /** @@ -414,6 +416,30 @@ static bool s3c64xx_spi_can_dma(struct spi_controller *host, } +static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr, + const void *buffer, unsigned int count) +{ + if (count) { + const u8 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} + +static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr, + const void *buffer, unsigned int count) +{ + if (count) { + const u16 *buf = buffer; + + do { + __raw_writel(*buf++, addr); + } while (--count); + } +} + static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, struct spi_transfer *xfer) { @@ -426,10 +452,16 @@ static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, iowrite32_rep(addr, buf, len / 4); break; case 16: - iowrite16_rep(addr, buf, len / 2); + if (sdd->port_conf->use_32bit_io) + s3c64xx_iowrite16_32_rep(addr, buf, len / 2); + else + iowrite16_rep(addr, buf, len / 2); break; default: - iowrite8_rep(addr, buf, len); + if (sdd->port_conf->use_32bit_io) + s3c64xx_iowrite8_32_rep(addr, buf, len); + else + iowrite8_rep(addr, buf, len); break; } } From patchwork Wed Feb 7 11:15:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tudor Ambarus X-Patchwork-Id: 197859 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2154486dyb; Wed, 7 Feb 2024 03:17:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IG3el5SANyAUNES8OkgOfTno1Ct+BkDqm62t66o1Y7dz3Esukkis3E0zLuev5BiosZo78e5 X-Received: by 2002:a17:906:a445:b0:a36:7e17:8929 with SMTP id cb5-20020a170906a44500b00a367e178929mr3940629ejb.69.1707304655696; Wed, 07 Feb 2024 03:17:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707304655; cv=pass; d=google.com; s=arc-20160816; b=kKEiODKNLxZ7e0XTULYUMzGI92YKfrdg+2gv+6DLeANQ5C62f+plpamK0aXsxvoQ2T lVDj+Io9nmdvEKRM2YCi+ll2UbBycsIVKbMALOId5jAgzO/O3lsIeQBwpRMFS23YznKB 8QyI9dLu0cQMrNvIMhIGrU4QtuCtgY+k7oAlZI8iOEYrqMmjkkmeR6+Bx54a5vbGThLL pHyIVQ3usqljKn7M4yqL2SLUHU19LcBmOb9jYTDFUZ/NWzG4AeYKTgH6su4Av4dqcPhT Uj4Zm4gOFLIeefGRn0nzmZ4heBmuaHgT0eCAK/DiiLNWbgd2R5O+7sxefRDg2wGnUei7 ZLAQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Dn0uxZFDo6NWePr2qdwdP08ijlsAxDoEPw964FSIz1A=; fh=Z9JEDDw5PFSqb+przsdE/Muk6OYNP7p5viHR5slQ2a0=; b=HAe7HI6wj9ya6QKKTmyH6YgipkHGwpUHD3kMRnDlp+L+WEjY022PwKtDNYKw0lihBP t2Dqi+5TaC/tG84z0o6y6MryjD3kh/clu7RhtyR6twvI+s36Zn1/syktF2tQjPvDhWME emMbJ63uSnWZU1aCZFqE4v7gV6caVfhHLa2alrY7MbwKK54sALbYSW6C2G00/RbAoRKb M9W9TXlJqB0Vxh/2Dn7cFTnN1grN5UiW/rNQU0piNsLnKTJxUKmh+uyUjsC70mPGmqI+ ZDzEAN08Rxy9QR+bKBTnthR36yd9tfv313ZXwNrRDlZlr9hPB8NXOKsJO9da7Swrz5gq GUmg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=z7PjOecY; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-56376-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56376-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=2; AJvYcCXg4SiN04lx4nyIpf7W3SXauhKkOuTykYXLAP4rqGS+0sgAITbsaKsHaPGOC4YuGxd5IOuRz94SmSJChwJgtkjNcpvm+Q== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[35.195.168.105]) by smtp.gmail.com with ESMTPSA id l14-20020a05600c4f0e00b0040ec8330c8asm4983260wmq.39.2024.02.07.03.15.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:15:21 -0800 (PST) From: Tudor Ambarus To: broonie@kernel.org, andi.shyti@kernel.org, semen.protsenko@linaro.org Cc: krzysztof.kozlowski@linaro.org, alim.akhtar@samsung.com, linux-spi@vger.kernel.org, linux-samsung-soc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, peter.griffin@linaro.org, kernel-team@android.com, willmcvicker@google.com, robh+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, Tudor Ambarus Subject: [PATCH v2 4/4] spi: s3c64xx: add support for google,gs101-spi Date: Wed, 7 Feb 2024 11:15:16 +0000 Message-ID: <20240207111516.2563218-5-tudor.ambarus@linaro.org> X-Mailer: git-send-email 2.43.0.687.g38aa6559b0-goog In-Reply-To: <20240207111516.2563218-1-tudor.ambarus@linaro.org> References: <20240207111516.2563218-1-tudor.ambarus@linaro.org> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790139025572308570 X-GMAIL-MSGID: 1790238686807761808 Add support for GS101 SPI. GS101 integrates 16 SPI nodes, all with 64 bytes FIFOs. GS101 allows just 32 bit register accesses, otherwise a Serror Interrupt is raised. Do the write reg accesses in 32 bits. Reviewed-by: Sam Protsenko Signed-off-by: Tudor Ambarus --- drivers/spi/spi-s3c64xx.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c index 014fcc933c90..7ab3f3c2e9aa 100644 --- a/drivers/spi/spi-s3c64xx.c +++ b/drivers/spi/spi-s3c64xx.c @@ -17,7 +17,7 @@ #include -#define MAX_SPI_PORTS 12 +#define MAX_SPI_PORTS 16 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) #define AUTOSUSPEND_TIMEOUT 2000 @@ -1534,6 +1534,19 @@ static const struct s3c64xx_spi_port_config fsd_spi_port_config = { .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, }; +static const struct s3c64xx_spi_port_config gs101_spi_port_config = { + .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, + 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, + .rx_lvl_offset = 15, + .tx_st_done = 25, + .clk_div = 4, + .high_speed = true, + .clk_from_cmu = true, + .has_loopback = true, + .use_32bit_io = true, + .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, +}; + static const struct platform_device_id s3c64xx_spi_driver_ids[] = { { .name = "s3c2443-spi", @@ -1546,6 +1559,9 @@ static const struct platform_device_id s3c64xx_spi_driver_ids[] = { }; static const struct of_device_id s3c64xx_spi_dt_match[] = { + { .compatible = "google,gs101-spi", + .data = &gs101_spi_port_config, + }, { .compatible = "samsung,s3c2443-spi", .data = (void *)&s3c2443_spi_port_config, },