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Wed, 07 Feb 2024 03:13:53 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCUg/yi/uJnxEcXcmd+ClMWaL8fo5FJp0E7pxLW4vkdPZBq2tQuH3k264ISX7sYs/6PkEusBcLp0t8vxUU1nEdwp6+GcqrFv2vXIkJxrTB0JJcPoty+/55pKqExpwVbHzkGNCCg58NY/f/RUoZkCSr26jNWoAL+rGGxWBlA0WC4WnH0DaRpuZ0qfTjDsi7dpnN0MLDSSdzC91W1zuXT+KeUNea3scWS60so7bDtfaDhLjy5x872vL7GDVkg0i0YF80Va8OlQATzjAoqy76EzUDm0965k0HbemZgpZsZ7nIJaQcWYP5Wwv/THKdoKcCvm/uK/QMjiiIcVXYZG42O4O0KTui/0hYj9Or4+XymP7PtrCROpQIBNDjY= Received: from starnight.endlessm-sf.com ([123.51.167.56]) by smtp.googlemail.com with ESMTPSA id jv12-20020a170903058c00b001d9602f3dbesm1176957plb.24.2024.02.07.03.13.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:13:52 -0800 (PST) From: Jian-Hong Pan To: Bjorn Helgaas , Johan Hovold , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , David Box Cc: Mika Westerberg , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v3 1/3] PCI: vmd: Enable PCI PM's L1 substates of remapped PCIe Root Port and NVMe Date: Wed, 7 Feb 2024 19:08:43 +0800 Message-ID: <20240207110842.576091-2-jhp@endlessos.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790237980438522525 X-GMAIL-MSGID: 1790238474694868397 The remapped PCIe Root Port and NVMe have PCI PM L1 substates capability, but they are disabled originally. Here is a failed example on ASUS B1400CEAE: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ PortCommonModeRestoreTime=32us PortTPowerOnTime=10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=0us LTR1.2_Threshold=0ns L1SubCtl2: T_PwrOn=10us Power on all of the VMD remapped PCI devices before enable PCI-PM L1 PM Substates by following PCI Express Base Specification Revision 6.0, section 5.5.4. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 Signed-off-by: Jian-Hong Pan --- v2: - Power on the VMD remapped devices with pci_set_power_state_locked() - Prepare the PCIe LTR parameters before enable L1 Substates - Add note into the comments of both pci_enable_link_state() and pci_enable_link_state_locked() for kernel-doc. - The original patch set can be split as individual patches. v3: - Re-send for the missed version information. - Split drivers/pci/pcie/aspm.c modification into following patches. - Fix the comment for enasuring the PCI devices in D0. drivers/pci/controller/vmd.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/drivers/pci/controller/vmd.c b/drivers/pci/controller/vmd.c index 87b7856f375a..6aca3f77724c 100644 --- a/drivers/pci/controller/vmd.c +++ b/drivers/pci/controller/vmd.c @@ -751,11 +751,9 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) if (!(features & VMD_FEAT_BIOS_PM_QUIRK)) return 0; - pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); - pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_LTR); if (!pos) - return 0; + goto out_enable_link_state; /* * Skip if the max snoop LTR is non-zero, indicating BIOS has set it @@ -763,7 +761,7 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) */ pci_read_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, <r_reg); if (!!(ltr_reg & (PCI_LTR_VALUE_MASK | PCI_LTR_SCALE_MASK))) - return 0; + goto out_enable_link_state; /* * Set the default values to the maximum required by the platform to @@ -775,6 +773,13 @@ static int vmd_pm_enable_quirk(struct pci_dev *pdev, void *userdata) pci_write_config_dword(pdev, pos + PCI_LTR_MAX_SNOOP_LAT, ltr_reg); pci_info(pdev, "VMD: Default LTR value set by driver\n"); +out_enable_link_state: + /* + * Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + */ + pci_set_power_state_locked(pdev, PCI_D0); + pci_enable_link_state_locked(pdev, PCIE_LINK_STATE_ALL); return 0; } From patchwork Wed Feb 7 11:14:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian-Hong Pan X-Patchwork-Id: 197860 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2155213dyb; Wed, 7 Feb 2024 03:19:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IHrIMZTU3RxH8/a8QgUcv0zYpElkNySQWX0aVHYOtWr+iXVWDJqRgBUz3ej+vJNqKUKP3dS X-Received: by 2002:a17:907:7803:b0:a37:501c:9eab with SMTP id la3-20020a170907780300b00a37501c9eabmr3679679ejc.43.1707304744956; Wed, 07 Feb 2024 03:19:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707304744; cv=pass; d=google.com; s=arc-20160816; b=rnYntpIu2yZWNWMpFST6YdgWkVH4tKsX6MbH9EAnMsVK04Y1L8d8pXKwNJgj8+ni6i Y8TU7TQ4fku8FyKRh9gJmF9D113TvLg+oxc++fDsiG+mTQTMzxdAx2ITC0vg1fcDjbC2 NEJPMVJ8vNiwAoDR/jX59RHjgBvWx856VYqsPD6AvkvnpzPaw6mUqq7bCRtZBdiVfBRP nHT+A0RKc4YeyiEFyP05he+Wc6QH7PPKesBKsX7WENpGXsq5VI4+h1rHv6mAVFzVb3Pk 8eUmDNrH0C5n7Kq1aQcdlSG/G43y23Bkm7zYW7SG0Yo65KPBEpqPggNG/Sm8FfzlDIBi sO8Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=nIqTMBlwECCoaCjtSPu7GBMR63K3xYDhekgHdgyJ3Uw=; fh=9yFsuty8v467MY34L3KwlqjHiF5Pe2JZFbyJqkYssh4=; b=KOopJdV4nyLlu/ok0c/yfKJ2Sb83cN28PDlOMLHhpn53i1SvgkzdQouclhlaA1674j NmBeH78KRp3+Ao1UCN0WfGT2R0LCFQnHZ0IMUZcPQ6HqPVY1KlBkfGwQR1P+DkpqOQPq TfmWmF4gECBLzn2h8sRkwZJn22TWaIh4XU9jyf45L+bNZnUvUlkftrIe6mouhWLYqJVT 6475jPoxm0aCTCWz2zu29RbpFvYHzlJiUpT7i0emLQBPW+tTYfXv4X0z33RxacS2Yhi0 z8tZxK8wPaUjghyeopU1W8IsSknYctxEGfl7FsFV5eJi8CNvqEHkT7xv8MW1GJVQmgAS doxw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@endlessos.org header.s=google header.b=qENNfVFe; arc=pass (i=1 spf=pass spfdomain=endlessos.org dkim=pass dkdomain=endlessos.org dmarc=pass fromdomain=endlessos.org); spf=pass (google.com: domain of linux-kernel+bounces-56380-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56380-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=endlessos.org X-Forwarded-Encrypted: i=2; AJvYcCUB/8Yl336AtgmXmQ5NDzyBL26qg223Ayq5X7a46PonqNStNo9AdSCXOXfYKZdYQifMxaaLhXwRwV72CwZSbzL+d/FMxA== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Wed, 07 Feb 2024 03:18:44 -0800 (PST) X-Forwarded-Encrypted: i=1; AJvYcCXDBZCqcU/ecjQFFfP1Fws3n8TlrjNFryuwLPxlTqdCVYrMnCBBXxfUkyHK/WGAHh7R821tL1nBH0Krw1wdwFkcxI1TcgsdG0qVVMep+k4mNLwoC+1Rnuh5Nvc6N9B4Epa4BrMW7/qxCg2Xk9zXVp4+ruO8p9V9Rr2bez48P9wSQgfJ/xOCO51cgF6uYzt0FMMAGTurzzygILHrwjN960mB9/ca05xbqCGSlC/r8lIwq0JZMiGtMWhYybPCCvcOBIYDNecQM2QcYmz8Sx5DM9aozAcsQa8anjRJL2Q5SkDdOSCEr03LHMEyhbfJQ7VvJkgqOVBwdkp7EhXg+ZHD1GyhRp2KQMoTqOsosogCheDiR5XmXosLoKE= Received: from starnight.endlessm-sf.com ([123.51.167.56]) by smtp.googlemail.com with ESMTPSA id z6-20020a17090a468600b002961ccd55e4sm3492799pjf.31.2024.02.07.03.18.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Feb 2024 03:18:44 -0800 (PST) From: Jian-Hong Pan To: Bjorn Helgaas , Johan Hovold , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , David Box Cc: Mika Westerberg , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v3 2/3] PCI/ASPM: Add notes about enabling PCI-PM L1SS to pci_enable_link_state(_locked) Date: Wed, 7 Feb 2024 19:14:04 +0800 Message-ID: <20240207111402.576152-3-jhp@endlessos.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790238779793269624 X-GMAIL-MSGID: 1790238779793269624 According to PCI Express Base Specification Revision 6.0, Section 5.5.4: "If setting either or both of the enable bits for PCI-PM L1 PM Substates, both ports must be configured as described in this section while in D0." Add notes into pci_enable_link_state(_locked) for kernel-doc. Hope these notify callers ensuring the devices in D0, if PCI-PM L1 PM Substates are going to be enabled. Signed-off-by: Jian-Hong Pan --- v3: - Fix as readable comments drivers/pci/pcie/aspm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 7f1d674ff171..a39d2ee744cb 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1416,6 +1416,9 @@ static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked) * touch the LNKCTL register. Also note that this does not enable states * disabled by pci_disable_link_state(). Return 0 or a negative errno. * + * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + * * @pdev: PCI device * @state: Mask of ASPM link states to enable */ @@ -1432,6 +1435,9 @@ EXPORT_SYMBOL(pci_enable_link_state); * can't touch the LNKCTL register. Also note that this does not enable states * disabled by pci_disable_link_state(). Return 0 or a negative errno. * + * Note: Ensure devices are in D0 before enabling PCI-PM L1 PM Substates, per + * PCIe r6.0, sec 5.5.4. + * * @pdev: PCI device * @state: Mask of ASPM link states to enable * From patchwork Wed Feb 7 11:18:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jian-Hong Pan X-Patchwork-Id: 197862 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2158282dyb; Wed, 7 Feb 2024 03:26:02 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCVEsoFkAgmJ2nl04JsMki+u4Grdrjg2m59YDlOfUiSkpQ0haNcOToYnVLdZDZ7sZ1R/BgWu8NTsvb57d9trZZModyh2BA== X-Google-Smtp-Source: AGHT+IHnBOnORhBr348zEZrHY+AiNdIn2csnddp+0Uz8phwnzk3fELiQP/rXkyTCI3ksuIJKDtAg X-Received: by 2002:a05:6a21:3990:b0:19e:9ae1:a2ad with SMTP id ad16-20020a056a21399000b0019e9ae1a2admr4634639pzc.60.1707305162783; Wed, 07 Feb 2024 03:26:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707305162; cv=pass; d=google.com; s=arc-20160816; b=095nA/p0m24mOKLhOpKkVGQcHt5J1ExDet1Kv234FzrwMeBd+Hwy1Hfo3J1vPtZdYj h8kGfjLo7QOjpYp92gD3xi+rH6hMpR6NC9sv+iaDCeggynX5r0JmC540j6gSp96rBgZa LzqINplmoz226DpsWEMAAuwU/ffwPj+yPHcshXS4158b4m4PKrjwo48KmZrJE3FKtY3j x6pPi4+09OBOtNqhWI7oouFNGXjFvU8Hk6Mf646QHRh+lqI0RQNhXgbapsqwk1dCVnxl cbZRjh8TfzrmHFDyfM3SigZleyX6UoQrocxngimt8/Bmx3UHDulMiWv41vOYfjNNvQBU DmJA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:date:subject:cc:to :from:dkim-signature; bh=eW2spjim+pJByd3Mxg/0ijFrCYtfv6oEIqERAXXxYdQ=; fh=wv1jfnRH4/s/To6pbYV5HlFUfOJQBcqcOydwxrXBmE8=; b=A7uR+dQUdhpnILiO43MgMrOI8lPuq3Ksc7Gz11HkQ/2WkJgo6rRccwuHRVCybu9cQH 1Zz6hz0eZIehxQkvkOpaXbmKyOJ1oaB7tU7ECY7OaaClMbSA5XEGOYQhdiAOwM0GAl+f 399ob7G51urwQVHy7rbZa9QJ/U3ERiHZjDFnJe1X4AI/GtA35kfXnDKWup2b+xaPz67i 6GOKxdr+2pk+yiaj3ZI79CSo82HDHAN8SguuztdtNXeXvUuEe60T+CjdXet9M3ikX59W meq2d6TUU7iZmt5UZ8sMAyifZ9y9Vish4eEXvzawafqGrn26qwIOLZHY6LtM9G2s/0Rm hq6g==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@endlessos.org header.s=google header.b=eLNvsA3A; arc=pass (i=1 spf=pass spfdomain=endlessos.org dkim=pass dkdomain=endlessos.org dmarc=pass fromdomain=endlessos.org); spf=pass (google.com: domain of linux-kernel+bounces-56389-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56389-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=endlessos.org X-Forwarded-Encrypted: i=2; AJvYcCVeSZ1DXo1lKFkvpE0zLktaTIXRtFkwgH90cXR33xg5usTsC/SOFLL8iMfXBbOKdc76XGvMl+PDtEneZJlqS4qgnhFhaQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 07 Feb 2024 03:25:42 -0800 (PST) From: Jian-Hong Pan To: Bjorn Helgaas , Johan Hovold , =?utf-8?q?Ilpo_J=C3=A4rvinen?= , David Box Cc: Mika Westerberg , Nirmal Patel , Jonathan Derrick , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux@endlessos.org, Jian-Hong Pan Subject: [PATCH v3 3/3] PCI/ASPM: Fix L1SS parameters & only enable supported features when enable link state Date: Wed, 7 Feb 2024 19:18:55 +0800 Message-ID: <20240207111854.576402-2-jhp@endlessos.org> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790239218347071929 X-GMAIL-MSGID: 1790239218347071929 The original __pci_enable_link_state() configs the links directly without: * Check the L1 substates features which are supported, or not * Calculate & program related parameters for L1.2, such as T_POWER_ON, Common_Mode_Restore_Time, and LTR_L1.2_THRESHOLD This leads some supported L1 PM substates of the link between VMD remapped PCIe Root Port and NVMe get wrong configs when a caller tries to enabled them. Here is a failed example on ASUS B1400CEAE with enabled VMD: Capabilities: [900 v1] L1 PM Substates L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- L1_PM_Substates+ PortCommonModeRestoreTime=32us PortTPowerOnTime=10us L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2+ ASPM_L1.1- T_CommonMode=0us LTR1.2_Threshold=0ns L1SubCtl2: T_PwrOn=10us This patch initializes the link's L1 PM substates to get the supported features and programs relating paramters, if some of them are going to be enabled in __pci_enable_link_state(). Then, enables the L1 PM substates if the caller intends to enable them and they are supported. Link: https://bugzilla.kernel.org/show_bug.cgi?id=218394 Signed-off-by: Jian-Hong Pan --- v2: - Prepare the PCIe LTR parameters before enable L1 Substates v3: - Only enable supported features for the L1 Substates part drivers/pci/pcie/aspm.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index a39d2ee744cb..c866971cae70 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -1389,14 +1389,16 @@ static int __pci_enable_link_state(struct pci_dev *pdev, int state, bool locked) link->aspm_default |= ASPM_STATE_L0S; if (state & PCIE_LINK_STATE_L1) link->aspm_default |= ASPM_STATE_L1; - /* L1 PM substates require L1 */ - if (state & PCIE_LINK_STATE_L1_1) + if (state & ASPM_STATE_L1_2_MASK) + aspm_l1ss_init(link); + /* L1 PM substates require L1 and should be in supported list */ + if (state & link->aspm_support & PCIE_LINK_STATE_L1_1) link->aspm_default |= ASPM_STATE_L1_1 | ASPM_STATE_L1; - if (state & PCIE_LINK_STATE_L1_2) + if (state & link->aspm_support & PCIE_LINK_STATE_L1_2) link->aspm_default |= ASPM_STATE_L1_2 | ASPM_STATE_L1; - if (state & PCIE_LINK_STATE_L1_1_PCIPM) + if (state & link->aspm_support & PCIE_LINK_STATE_L1_1_PCIPM) link->aspm_default |= ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1; - if (state & PCIE_LINK_STATE_L1_2_PCIPM) + if (state & link->aspm_support & PCIE_LINK_STATE_L1_2_PCIPM) link->aspm_default |= ASPM_STATE_L1_2_PCIPM | ASPM_STATE_L1; pcie_config_aspm_link(link, policy_to_aspm_state(link));