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Wed, 7 Feb 2024 03:28:28 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 7 Feb 2024 03:28:16 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Rob Herring Subject: [PATCH v3 1/4] dt-bindings: display: bridge: add sam9x75-lvds compatible Date: Wed, 7 Feb 2024 15:57:59 +0530 Message-ID: <20240207102802.200220-2-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207102802.200220-1-dharma.b@microchip.com> References: <20240207102802.200220-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790235699871159846 X-GMAIL-MSGID: 1790235699871159846 Add the 'sam9x75-lvds' compatible binding, which describes the Low Voltage Differential Signaling (LVDS) Controller found on some Microchip's sam9x7 series System-on-Chip (SoC) devices. This binding will be used to define the properties and configuration for the LVDS Controller in DT. Signed-off-by: Dharma Balasubiramani Reviewed-by: Rob Herring --- Changelog v2 -> v3 - No changes. v1 -> v2 - Remove '|' in description, as there is no formatting to preserve. - Remove 'gclk' from clock-names as there is only one clock(pclk). - Remove the unused headers and include only used ones. - Change the compatible name specific to SoC (sam9x75) instead of entire series. - Change file name to match the compatible name. --- .../bridge/microchip,sam9x75-lvds.yaml | 55 +++++++++++++++++++ 1 file changed, 55 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml new file mode 100644 index 000000000000..862ef441ac9f --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/microchip,sam9x75-lvds.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/microchip,sam9x75-lvds.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip SAM9X75 LVDS Controller + +maintainers: + - Dharma Balasubiramani + +description: + The Low Voltage Differential Signaling Controller (LVDSC) manages data + format conversion from the LCD Controller internal DPI bus to OpenLDI + LVDS output signals. LVDSC functions include bit mapping, balanced mode + management, and serializer. + +properties: + compatible: + const: microchip,sam9x75-lvds + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral Bus Clock + + clock-names: + items: + - const: pclk + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include + #include + lvds-controller@f8060000 { + compatible = "microchip,sam9x75-lvds"; + reg = <0xf8060000 0x100>; + interrupts = <56 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 56>; + clock-names = "pclk"; + }; From patchwork Wed Feb 7 10:28:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 197844 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2133740dyb; Wed, 7 Feb 2024 02:30:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IE89xMj1cfGo7njX2iJYQx8xLqnKgoD+ZKgnsPCOz6CLPuUznRKmiP06tKiiNxAuPQVOwD2 X-Received: by 2002:a17:90a:ff05:b0:296:341b:a60 with SMTP id ce5-20020a17090aff0500b00296341b0a60mr2026465pjb.13.1707301814116; Wed, 07 Feb 2024 02:30:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707301814; cv=pass; d=google.com; s=arc-20160816; b=sAFsRB+3MlVf1vwbj8O/XbWaCWO/3NnLK3QGRIuq91Lk529EtIi83m3PUsfPDmnVpu sXFQm0cUWgieckKjpV0qc+CyJy1/BhVz9P0sOSjmR3U/wRD1nHvr7+KD9/Tsm/obvkEk sNke0dQvuZBqDsbAmOxLf5BY0zlpwhfaiYQzZK5NpT+QhTzLtKrSYsfvRivis/J4778U rcj4wBl5ctN7BL906yrjAixqgVUbIcL9O709B3AkmT7f81TsU+VMSmvw6gmS3zXTCBbe jW9ic6rMy98PCYxRAMgu0wKCoZbMm1cTEkx82ReXCB32khu+/fdhF3yo6hYFX2NdR6Sq K/yg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:to:from:dkim-signature; bh=BlUXV5+7Cd9Zf2nOHOwERhCM/Tgs542RJO+aTXanqLY=; fh=QLluRRjuy7m3goKzs9tE/P5XcnJdQevtI1nmb5X2WPc=; b=Fwoc7OPh69LuIBUOllHWcR5EhAP+fNhIcVtiH1xZ+scFgI9yy5YlaW3AHhQ4BPSAdn uRCS7Kxr5VnM/hau5m2YhnbYkENcOn/amWIoPBD0F8mj012qPKWDyRYy6Ad0N1399voc gB0YCMx2B9zBpKpRCAsMrakfi+pXm7oSios5qB02CtU+zyThHD90FBNIbcdTUPJSJStg K28FlLq1Ap6mCxmIMs8KX9KRSXdL6m/XEA+l5tKpEgqfbQ4UQ+39uy/legoVfjH47G7A tkQJgWTc61xwBOAk27ATajOSMcFIz6xgc4xodo/Isz0cCdlqgyKtm+zPhA2FuhJlr7JZ 7Yrw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=tuKCxYwK; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-56317-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56317-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com X-Forwarded-Encrypted: i=2; AJvYcCXt9/+lZ8R8EqGdrf9EInrwtkIlPA0jIJR9G9am08L9xnwUgXB0+mjQgS/a+w66lhXmQdxGgUrzChANFigMv65QVTSrTw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 7 Feb 2024 03:28:40 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 7 Feb 2024 03:28:28 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 2/4] drm/bridge: add lvds controller support for sam9x7 Date: Wed, 7 Feb 2024 15:58:00 +0530 Message-ID: <20240207102802.200220-3-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207102802.200220-1-dharma.b@microchip.com> References: <20240207102802.200220-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790235706795116056 X-GMAIL-MSGID: 1790235706795116056 Add a new LVDS controller driver for sam9x7 which does the following: - Prepares and enables the LVDS Peripheral clock - Defines its connector type as DRM_MODE_CONNECTOR_LVDS and adds itself to the global bridge list. - Identifies its output endpoint as panel and adds it to the encoder display pipeline - Enables the LVDS serializer Signed-off-by: Manikandan Muralidharan Signed-off-by: Dharma Balasubiramani --- Changelog v2 ->v3 - Correct Typo error "serializer". - Consolidate get() and prepare() functions and use devm_clk_get_prepared(). - Remove unused variable 'ret' in probe(). - Use devm_pm_runtime_enable() and drop the mchp_lvds_remove(). v1 -> v2 - Drop 'res' variable and combine two lines into one. - Handle deferred probe properly, use dev_err_probe(). - Don't print anything on deferred probe. Dropped print. - Remove the MODULE_ALIAS and add MODULE_DEVICE_TABLE(). - symbol 'mchp_lvds_driver' was not declared. It should be static. --- drivers/gpu/drm/bridge/Kconfig | 7 + drivers/gpu/drm/bridge/Makefile | 1 + drivers/gpu/drm/bridge/microchip-lvds.c | 228 ++++++++++++++++++++++++ 3 files changed, 236 insertions(+) create mode 100644 drivers/gpu/drm/bridge/microchip-lvds.c diff --git a/drivers/gpu/drm/bridge/Kconfig b/drivers/gpu/drm/bridge/Kconfig index 3e6a4e2044c0..74ca0edb4e0d 100644 --- a/drivers/gpu/drm/bridge/Kconfig +++ b/drivers/gpu/drm/bridge/Kconfig @@ -173,6 +173,13 @@ config DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW to DP++. This is used with the i.MX6 imx-ldb driver. You are likely to say N here. +config DRM_MICROCHIP_LVDS_SERIALIZER + tristate "Microchip LVDS serializer support" + depends on OF + depends on DRM_ATMEL_HLCDC + help + Support for Microchip's LVDS serializer. + config DRM_NWL_MIPI_DSI tristate "Northwest Logic MIPI DSI Host controller" depends on DRM diff --git a/drivers/gpu/drm/bridge/Makefile b/drivers/gpu/drm/bridge/Makefile index 2b892b7ed59e..e3804e93d324 100644 --- a/drivers/gpu/drm/bridge/Makefile +++ b/drivers/gpu/drm/bridge/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_DRM_LONTIUM_LT9611) += lontium-lt9611.o obj-$(CONFIG_DRM_LONTIUM_LT9611UXC) += lontium-lt9611uxc.o obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o +obj-$(CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER) += microchip-lvds.o obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o diff --git a/drivers/gpu/drm/bridge/microchip-lvds.c b/drivers/gpu/drm/bridge/microchip-lvds.c new file mode 100644 index 000000000000..d3fd9d722e36 --- /dev/null +++ b/drivers/gpu/drm/bridge/microchip-lvds.c @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries + * + * Author: Manikandan Muralidharan + * Author: Dharma Balasubiramani + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#define LVDS_POLL_TIMEOUT_MS 1000 + +/* LVDSC register offsets */ +#define LVDSC_CR 0x00 +#define LVDSC_CFGR 0x04 +#define LVDSC_SR 0x0C +#define LVDSC_WPMR 0xE4 + +/* Bitfields in LVDSC_CR (Control Register) */ +#define LVDSC_CR_SER_EN BIT(0) + +/* Bitfields in LVDSC_CFGR (Configuration Register) */ +#define LVDSC_CFGR_PIXSIZE_24BITS 0 +#define LVDSC_CFGR_DEN_POL_HIGH 0 +#define LVDSC_CFGR_DC_UNBALANCED 0 +#define LVDSC_CFGR_MAPPING_JEIDA BIT(6) + +/*Bitfields in LVDSC_SR */ +#define LVDSC_SR_CS BIT(0) + +/* Bitfields in LVDSC_WPMR (Write Protection Mode Register) */ +#define LVDSC_WPMR_WPKEY_MASK GENMASK(31, 8) +#define LVDSC_WPMR_WPKEY_PSSWD 0x4C5644 + +struct mchp_lvds { + struct device *dev; + void __iomem *regs; + struct clk *pclk; + int format; /* vesa or jeida format */ + struct drm_panel *panel; + struct drm_bridge bridge; + struct drm_bridge *panel_bridge; +}; + +static inline struct mchp_lvds *bridge_to_lvds(struct drm_bridge *bridge) +{ + return container_of(bridge, struct mchp_lvds, bridge); +} + +static inline u32 lvds_readl(struct mchp_lvds *lvds, u32 offset) +{ + return readl_relaxed(lvds->regs + offset); +} + +static inline void lvds_writel(struct mchp_lvds *lvds, u32 offset, u32 val) +{ + writel_relaxed(val, lvds->regs + offset); +} + +static void lvds_serialiser_on(struct mchp_lvds *lvds) +{ + unsigned long timeout = jiffies + msecs_to_jiffies(LVDS_POLL_TIMEOUT_MS); + + /* The LVDSC registers can only be written if WPEN is cleared */ + lvds_writel(lvds, LVDSC_WPMR, (LVDSC_WPMR_WPKEY_PSSWD & + LVDSC_WPMR_WPKEY_MASK)); + + /* Wait for the status of configuration registers to be changed */ + while (lvds_readl(lvds, LVDSC_SR) & LVDSC_SR_CS) { + if (time_after(jiffies, timeout)) { + dev_err(lvds->dev, "%s: timeout error\n", __func__); + return; + } + usleep_range(1000, 2000); + } + + /* Configure the LVDSC */ + lvds_writel(lvds, LVDSC_CFGR, (LVDSC_CFGR_MAPPING_JEIDA | + LVDSC_CFGR_DC_UNBALANCED | + LVDSC_CFGR_DEN_POL_HIGH | + LVDSC_CFGR_PIXSIZE_24BITS)); + + /* Enable the LVDS serializer */ + lvds_writel(lvds, LVDSC_CR, LVDSC_CR_SER_EN); +} + +static int mchp_lvds_attach(struct drm_bridge *bridge, + enum drm_bridge_attach_flags flags) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + + bridge->encoder->encoder_type = DRM_MODE_ENCODER_LVDS; + + return drm_bridge_attach(bridge->encoder, lvds->panel_bridge, + bridge, flags); +} + +static void mchp_lvds_enable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + int ret; + + ret = clk_enable(lvds->pclk); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to enable lvds pclk %d\n", ret); + return; + } + + ret = pm_runtime_get_sync(lvds->dev); + if (ret < 0) { + DRM_DEV_ERROR(lvds->dev, "failed to get pm runtime: %d\n", ret); + clk_disable(lvds->pclk); + return; + } + + lvds_serialiser_on(lvds); +} + +static void mchp_lvds_disable(struct drm_bridge *bridge) +{ + struct mchp_lvds *lvds = bridge_to_lvds(bridge); + + pm_runtime_put(lvds->dev); + clk_disable(lvds->pclk); +} + +static const struct drm_bridge_funcs mchp_lvds_bridge_funcs = { + .attach = mchp_lvds_attach, + .enable = mchp_lvds_enable, + .disable = mchp_lvds_disable, +}; + +static int mchp_lvds_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct mchp_lvds *lvds; + struct device_node *port; + + if (!dev->of_node) + return -ENODEV; + + lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL); + if (!lvds) + return -ENOMEM; + + lvds->dev = dev; + + lvds->regs = devm_ioremap_resource(lvds->dev, + platform_get_resource(pdev, IORESOURCE_MEM, 0)); + if (IS_ERR(lvds->regs)) + return PTR_ERR(lvds->regs); + + lvds->pclk = devm_clk_get_prepared(lvds->dev, "pclk"); + if (IS_ERR(lvds->pclk)) + return dev_err_probe(lvds->dev, PTR_ERR(lvds->pclk), + "could not get pclk_lvds prepared\n"); + + port = of_graph_get_remote_node(dev->of_node, 1, 0); + if (!port) { + DRM_DEV_ERROR(dev, + "can't find port point, please init lvds panel port!\n"); + return -EINVAL; + } + + lvds->panel = of_drm_find_panel(port); + of_node_put(port); + + if (IS_ERR(lvds->panel)) + return -EPROBE_DEFER; + + lvds->panel_bridge = devm_drm_panel_bridge_add(dev, lvds->panel); + + if (IS_ERR(lvds->panel_bridge)) + return PTR_ERR(lvds->panel_bridge); + + lvds->bridge.of_node = dev->of_node; + lvds->bridge.type = DRM_MODE_CONNECTOR_LVDS; + lvds->bridge.funcs = &mchp_lvds_bridge_funcs; + + dev_set_drvdata(dev, lvds); + devm_pm_runtime_enable(dev); + + drm_bridge_add(&lvds->bridge); + + return 0; +} + +static const struct of_device_id mchp_lvds_dt_ids[] = { + { + .compatible = "microchip,sam9x75-lvds", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, mchp_lvds_dt_ids); + +static struct platform_driver mchp_lvds_driver = { + .probe = mchp_lvds_probe, + .driver = { + .name = "microchip-lvds", + .of_match_table = mchp_lvds_dt_ids, + }, +}; +module_platform_driver(mchp_lvds_driver); + +MODULE_AUTHOR("Manikandan Muralidharan "); +MODULE_AUTHOR("Dharma Balasubiramani "); +MODULE_DESCRIPTION("Low Voltage Differential Signaling Controller Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 7 10:28:01 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 197845 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2133795dyb; Wed, 7 Feb 2024 02:30:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8349imRjeuRskR1gTH98aBdFM5ca6Bz2eAV3Z8CRaQW4o/ZTF6T9p4B9tJAjylvcp4gkD X-Received: by 2002:a17:902:dac2:b0:1d9:6fce:54f7 with SMTP id q2-20020a170902dac200b001d96fce54f7mr6699907plx.9.1707301822656; Wed, 07 Feb 2024 02:30:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707301822; cv=pass; d=google.com; s=arc-20160816; b=Hb7EZMGvVRLOrogNaAV3fxw1cBlLzJPlkx2Br3ys3qxfdlrFqbvkiiKQFGFH0unxtg 0tOY9WH+VTGlikfNdasCgsJ/Vvf6proAJnwmjYrGACvo3uWwT906kBrCr/37cVsZdyge 9sfmn3GT149n5qthnc8bjN6eizpwVEYmuR2Mhsfy5XuHAiSmMsKincS1mWbidOJ4Ipdd 6v35Jnu5ab0ftkSlMP/u8qB3s1n+VT5xAXjrknzGiNYn1ZJuJCNIXoYfyJZ3AU2LuTxz d7eKfLiNzP2mF7HsQiH3gIC4xs7DrTHkT2vG7rKioo8Ioaja0pl6d2fc9nY5Xtqh5/YA 0mGA== ARC-Message-Signature: i=2; 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Wed, 7 Feb 2024 03:28:51 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 7 Feb 2024 03:28:40 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v3 3/4] MAINTAINERS: add SAM9X7 SoC's LVDS controller Date: Wed, 7 Feb 2024 15:58:01 +0530 Message-ID: <20240207102802.200220-4-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207102802.200220-1-dharma.b@microchip.com> References: <20240207102802.200220-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790235716196263623 X-GMAIL-MSGID: 1790235716196263623 Add the newly added LVDS controller for the SAM9X7 SoC to the existing MAINTAINERS entry. Signed-off-by: Dharma Balasubiramani Reviewed-by: Neil Armstrong Acked-by: Nicolas Ferre --- Changelog v2 -> v3 - Move the entry before "MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER". v1 -> v2 - No Changes. --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index a7c4cf8201e0..ce592b6cf375 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14216,6 +14216,14 @@ S: Supported F: Documentation/devicetree/bindings/pwm/atmel,at91sam-pwm.yaml F: drivers/pwm/pwm-atmel.c +MICROCHIP SAM9x7-COMPATIBLE LVDS CONTROLLER +M: Manikandan Muralidharan +M: Dharma Balasubiramani +L: dri-devel@lists.freedesktop.org +S: Supported +F: Documentation/devicetree/bindings/display/bridge/microchip,sam9x7-lvds.yaml +F: drivers/gpu/drm/bridge/microchip-lvds.c + MICROCHIP SAMA5D2-COMPATIBLE ADC DRIVER M: Eugen Hristev L: linux-iio@vger.kernel.org From patchwork Wed Feb 7 10:28:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dharma Balasubiramani X-Patchwork-Id: 197846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2133869dyb; Wed, 7 Feb 2024 02:30:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IEvPFuvGXqJJldjlwY9ZkoRrPST0vybX7tJaioKAG/4vfQKrF/ze7Y4dW8Zx4uXTDFfXqdO X-Received: by 2002:a05:6a21:2d8c:b0:19e:a30e:7333 with SMTP id ty12-20020a056a212d8c00b0019ea30e7333mr2272812pzb.25.1707301832241; Wed, 07 Feb 2024 02:30:32 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707301832; cv=pass; d=google.com; s=arc-20160816; b=UnWzftiyeBl8c8WFmY6mDz2huDbYO3CreKQUdMTfDC2ypxESJWRssrQKQfjJ5N5kDR evvT0dMMj4QlOUb5hN6PbJ3XJw8Y0Amnsgzl+IvaWnn674dLVGTlUBIBcJWPpu8gnzZ+ 0GuN9R+oDWf1yvFNbsV2P64/Wqz2zKrZJTIVvNwreCycKUnPrOa+L4IZbYv9A5va449B gH4EceespblLZm0AI/y2MFsbv/PcKitBCNjGRnwi459YaD7Xw+BTE3kgbkvfP8RPDkV7 cbd33PVvCLZ7ji3CUXf+xiODi0s8sNrtxXuVw3epY10ys7D+vy+3yfHQjCrIRpY0yNmn oFkw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=PbWLZEhAQprBLNBQffTxCET8mVnxupxneNDXdC+H+iM=; fh=jT/3Hff0r1D2OGvlqA4CRLL93dZGQJDdle5K07VNN2U=; b=n5kq38Zix9gTq8lcAW4QaSzfQx2m/Kp1PiwJzJjtG2xoiytTXSi1q/K39kyzl3GXwJ pvzpadm18LHCWHMxw0DtpDQcjL5z1wjwrEPtpaKPRYIu+94RTtlp9m1b/QjPJInohsHr 1QL2j1u1lfn5Zrl/BnFHYEm/3anw61K1D8RGdJPqYKCI3B7DGPT/PqF+KXpflsZBEm0g IjRqduDE2vKcgmjrtLAAoJpNORwMvrdzR3pZgwoYu4NwBP2dUKBEGQpOcjC0/VJGXjlY 4k3jBIhXihpEjV4C/2IkzWIKia51BswTL7OGzFbcfU4pgd+w0iG9OQW3MKmGx7rRCKt0 saIw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@microchip.com header.s=mchp header.b=Rs13nRfU; arc=pass (i=1 spf=pass spfdomain=microchip.com dkim=pass dkdomain=microchip.com dmarc=pass fromdomain=microchip.com); spf=pass (google.com: domain of linux-kernel+bounces-56319-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56319-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=REJECT dis=NONE) header.from=microchip.com X-Forwarded-Encrypted: i=2; AJvYcCWHGO5ZeLKlWkAImSA5qndf89Vq919+3Sle0fJjWWzVgFjYbLuE4tqNTzC54C8YaAdX6WzFbMHNKZ9HbYF9CAnJuz7U8A== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 7 Feb 2024 03:29:03 -0700 Received: from che-lt-i70843lx.microchip.com (10.10.85.11) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.35 via Frontend Transport; Wed, 7 Feb 2024 03:28:51 -0700 From: Dharma Balasubiramani To: , , , , , , , , , , , , , , , , , , , , , , , , , , , , , CC: Hari Prasath Gujulan Elango Subject: [PATCH v3 4/4] ARM: configs: at91: Enable LVDS serializer support Date: Wed, 7 Feb 2024 15:58:02 +0530 Message-ID: <20240207102802.200220-5-dharma.b@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240207102802.200220-1-dharma.b@microchip.com> References: <20240207102802.200220-1-dharma.b@microchip.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790235726058302930 X-GMAIL-MSGID: 1790235726058302930 Enable LVDS serializer support for display pipeline. Signed-off-by: Dharma Balasubiramani Acked-by: Hari Prasath Gujulan Elango Acked-by: Nicolas Ferre --- Changelog v2 -> v3 - No Changes. --- arch/arm/configs/at91_dt_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/configs/at91_dt_defconfig b/arch/arm/configs/at91_dt_defconfig index 71b5acc78187..6a7714beb099 100644 --- a/arch/arm/configs/at91_dt_defconfig +++ b/arch/arm/configs/at91_dt_defconfig @@ -143,6 +143,7 @@ CONFIG_VIDEO_OV2640=m CONFIG_VIDEO_OV7740=m CONFIG_DRM=y CONFIG_DRM_ATMEL_HLCDC=y +CONFIG_DRM_MICROCHIP_LVDS_SERIALIZER=y CONFIG_DRM_PANEL_SIMPLE=y CONFIG_DRM_PANEL_EDP=y CONFIG_FB_ATMEL=y