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bh=F4hpxMA5+ygGVhpwcP2mZmSl/SjCpkScNtD4H29x7+g=; b=WKe3P8qOf4s3e5rVNAzH/YpRmEGYxd0kGTT8v+b45+SyVK9VLZmGyyE6 vbhwwrmRrP/NA5bXzGqMg/8s7w/uq1JfxGvbx/VfTnqhBnUL7TVvhQ+4v MPWHwR79zuuGu/a37lKu1b1fKDxTA9FcvN7yA2mcdYXwPkbnUdgZ+BqZE pOOpCdJyhRyF+Dqc3ZgHQ5yMu1/LYqnfF/00uVtYKCfC58cOjCLEiYNiG UufxajNJSqhk2ZtEWYDx+ad5I4ipbQ69AQCQtsW4lYI5HcRIAEsW0sBS+ qnPWR2ayH1ZnL0HrHhUmfYJrVeygQvfgIeUnYD8yvQTdiPxsWfOAkmErJ A==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436053923" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436053923" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:09:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849721" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:09:02 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 01/11] x86/tsc: Add base clock properties in clocksource structure Date: Wed, 7 Feb 2024 11:38:44 +0530 Message-Id: <20240207060854.6524-2-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219326953408757 X-GMAIL-MSGID: 1790219326953408757 From: Lakshmi Sowjanya D Add base clock hardware abstraction in clocksource structure. Add clocksource ID for x86 ART(Always Running Timer). Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- arch/x86/kernel/tsc.c | 43 ++++++++++++++++++--------------- include/linux/clocksource.h | 27 +++++++++++++++++++++ include/linux/clocksource_ids.h | 1 + 3 files changed, 52 insertions(+), 19 deletions(-) diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index a82c9bcc32a0..96a5c4c2c6ee 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -50,9 +50,9 @@ int tsc_clocksource_reliable; static int __read_mostly tsc_force_recalibrate; -static u32 art_to_tsc_numerator; -static u32 art_to_tsc_denominator; -static u64 art_to_tsc_offset; +static struct clocksource_base art_base_clk = { + .id = CSID_X86_ART, +}; static bool have_art; struct cyc2ns { @@ -1074,7 +1074,7 @@ core_initcall(cpufreq_register_tsc_scaling); */ static void __init detect_art(void) { - unsigned int unused[2]; + unsigned int unused; if (boot_cpu_data.cpuid_level < ART_CPUID_LEAF) return; @@ -1089,13 +1089,14 @@ static void __init detect_art(void) tsc_async_resets) return; - cpuid(ART_CPUID_LEAF, &art_to_tsc_denominator, - &art_to_tsc_numerator, unused, unused+1); + cpuid(ART_CPUID_LEAF, &art_base_clk.denominator, + &art_base_clk.numerator, &art_base_clk.freq_khz, &unused); - if (art_to_tsc_denominator < ART_MIN_DENOMINATOR) + art_base_clk.freq_khz /= KHZ; + if (art_base_clk.denominator < ART_MIN_DENOMINATOR) return; - rdmsrl(MSR_IA32_TSC_ADJUST, art_to_tsc_offset); + rdmsrl(MSR_IA32_TSC_ADJUST, art_base_clk.offset); /* Make this sticky over multiple CPU init calls */ setup_force_cpu_cap(X86_FEATURE_ART); @@ -1303,13 +1304,13 @@ struct system_counterval_t convert_art_to_tsc(u64 art) { u64 tmp, res, rem; - rem = do_div(art, art_to_tsc_denominator); + rem = do_div(art, art_base_clk.denominator); - res = art * art_to_tsc_numerator; - tmp = rem * art_to_tsc_numerator; + res = art * art_base_clk.numerator; + tmp = rem * art_base_clk.numerator; - do_div(tmp, art_to_tsc_denominator); - res += tmp + art_to_tsc_offset; + do_div(tmp, art_base_clk.denominator); + res += tmp + art_base_clk.offset; return (struct system_counterval_t) { .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, @@ -1346,7 +1347,6 @@ struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) do_div(tmp, USEC_PER_SEC); res += tmp; - return (struct system_counterval_t) { .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, .cycles = res @@ -1354,7 +1354,6 @@ struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) } EXPORT_SYMBOL(convert_art_ns_to_tsc); - static void tsc_refine_calibration_work(struct work_struct *work); static DECLARE_DELAYED_WORK(tsc_irqwork, tsc_refine_calibration_work); /** @@ -1456,8 +1455,10 @@ static void tsc_refine_calibration_work(struct work_struct *work) if (tsc_unstable) goto unreg; - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); unreg: clocksource_unregister(&clocksource_tsc_early); @@ -1482,8 +1483,10 @@ static int __init init_tsc_clocksource(void) * the refined calibration and directly register it as a clocksource. */ if (boot_cpu_has(X86_FEATURE_TSC_KNOWN_FREQ)) { - if (boot_cpu_has(X86_FEATURE_ART)) + if (boot_cpu_has(X86_FEATURE_ART)) { have_art = true; + clocksource_tsc.base = &art_base_clk; + } clocksource_register_khz(&clocksource_tsc, tsc_khz); clocksource_unregister(&clocksource_tsc_early); @@ -1507,10 +1510,12 @@ static bool __init determine_cpu_tsc_frequencies(bool early) if (early) { cpu_khz = x86_platform.calibrate_cpu(); - if (tsc_early_khz) + if (tsc_early_khz) { tsc_khz = tsc_early_khz; - else + } else { tsc_khz = x86_platform.calibrate_tsc(); + clocksource_tsc.freq_khz = tsc_khz; + } } else { /* We should not be here with non-native cpu calibration */ WARN_ON(x86_platform.calibrate_cpu != native_calibrate_cpu); diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h index 1d42d4b17327..0a1110a0e660 100644 --- a/include/linux/clocksource.h +++ b/include/linux/clocksource.h @@ -21,6 +21,7 @@ #include #include +struct clocksource_base; struct clocksource; struct module; @@ -48,6 +49,7 @@ struct module; * @archdata: Optional arch-specific data * @max_cycles: Maximum safe cycle value which won't overflow on * multiplication + * @freq_khz: Clocksource frequency in khz. * @name: Pointer to clocksource name * @list: List head for registration (internal) * @rating: Rating value for selection (higher is better) @@ -70,6 +72,8 @@ struct module; * validate the clocksource from which the snapshot was * taken. * @flags: Flags describing special properties + * @base: Hardware abstraction for clock on which a clocksource + * is based * @enable: Optional function to enable the clocksource * @disable: Optional function to disable the clocksource * @suspend: Optional suspend function for the clocksource @@ -105,12 +109,14 @@ struct clocksource { struct arch_clocksource_data archdata; #endif u64 max_cycles; + u32 freq_khz; const char *name; struct list_head list; int rating; enum clocksource_ids id; enum vdso_clock_mode vdso_clock_mode; unsigned long flags; + struct clocksource_base *base; int (*enable)(struct clocksource *cs); void (*disable)(struct clocksource *cs); @@ -294,4 +300,25 @@ static inline void timer_probe(void) {} extern ulong max_cswd_read_retries; void clocksource_verify_percpu(struct clocksource *cs); +/** + * struct clocksource_base - hardware abstraction for clock on which a clocksource + * is based + * @id: Defaults to CSID_GENERIC. The id value is used for conversion + * functions which require that the current clocksource is based + * on a clocksource_base with a particular ID in certain snapshot + * functions to allow callers to validate the clocksource from + * which the snapshot was taken. + * @freq_khz: Nominal frequency of the base clock in kHz + * @offset: Offset between the base clock and the clocksource + * @numerator: Numerator of the clock ratio between base clock and the clocksource + * @denominator: Denominator of the clock ratio between base clock and the clocksource + */ +struct clocksource_base { + enum clocksource_ids id; + u32 freq_khz; + u64 offset; + u32 numerator; + u32 denominator; +}; + #endif /* _LINUX_CLOCKSOURCE_H */ diff --git a/include/linux/clocksource_ids.h b/include/linux/clocksource_ids.h index a4fa3436940c..2bb4d8c2f1b0 100644 --- a/include/linux/clocksource_ids.h +++ b/include/linux/clocksource_ids.h @@ -9,6 +9,7 @@ enum clocksource_ids { CSID_X86_TSC_EARLY, CSID_X86_TSC, CSID_X86_KVM_CLK, + CSID_X86_ART, CSID_MAX, }; From patchwork Wed Feb 7 06:08:45 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197752 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2030840dyb; Tue, 6 Feb 2024 22:10:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IHM64XEbMTX1FaS+p3vBVlEdumSEBEnhjUyBwUmqnnqB5lJ3jlfIKQ9/mynytwefGNGJk+L X-Received: by 2002:a05:6512:3ca3:b0:511:62af:c54d with SMTP id h35-20020a0565123ca300b0051162afc54dmr1753582lfv.38.1707286220261; Tue, 06 Feb 2024 22:10:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286220; cv=pass; d=google.com; s=arc-20160816; b=S/v892RrHZZSrKmgZvbz88fUeafNWqFvFzu3sYEsNx1Muye0diN0y3Se6hX5Uc6JZv lKaFeB6ygG/P/vzkUMrkyuySJFhhsuEEjCXTGJJAWhuWqBxvL3VN91hLtz3eJ9qUrEMd MxHtSCWak9ACB682CthWKJziaPmo22A+43fhyxnKGd+Z+UYyHPI/KLzn5j4ZKTm4jten MATFfz8l/qq+mxDsMymP9uIoVpBddM0d1fgI4HmTQ+4JPEOiTii8MXqMcvE5DEGp/jaH x/Wy4vbIb+DM5W1NmyUqQIQad1Tb+NKAwO7yOdevOsUIeTYQWIXS0GXQJfC5p3I0Cr6m k4MA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=4SBcGPc9tr3dbMY79fPc40S7s9qN1/TGJml+OZxbuo4=; fh=/fC5hd86XuApJRSixLurCNgxnWGp5/yr4twi9IWBxBM=; b=kKM1B+ZWwpLzkR6IGyX4dDYcOstNlOZqw+iXqIzTrBXR+eIDCReaPKNUYXumixQIXj IoGRHDL2Y05CSFAv8boXuZZxjjc+YAXYWcp7MpGIS3pZay7VzERSiem9Y/LueUm4hehE mZy6q3dP3iSNEyjs794PVTcblGNU61yQZNnYEZb4x7YdcLMXkDm7HXeOZlW1UNfYOOfj ZuPIaJhrj3bj77RK1VeR9rOTGTNDq0uzld7OQqntVtutZJA7ozlqxIwJDhZpgayATjal hIc0vzKVe6Ze7yiV5+x+Sk3hKy33ZMuskVeCyRbw838j8fJCvNW31Q3AeWSVrUdf37R0 SpMw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=kzONTKUO; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-55994-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55994-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCVKe4RUxkAsESpkxHyHsjbajCBvI/Y6ZPOPOwqYyWo4jjifY89etRwYAU+VfljpctXhJrARCJ87t2M5Xq2wjaDCPUpEng== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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bh=Ime50F3RKb2m1VV+ZMtTLz8M9K+YfMpKUU6CJBgWeTE=; b=kzONTKUOi+Z17NPfYeq6Ad+PbLvIwjVnkHGn0EeWUnmaOi61sczXeW8x yIREfTbK86/U2Pw4xxkUAJ4E8fFdd9xAM/RqXYozWC0LVpKxU9XwT8ajs 4xJykyw3B5Y6s9ZwqNAkgmDF0T6ch9dWMAkcZf+sqqTaAIR65IJJjtPZH b/lJ5ULfOtVhQiZ4Wy5BhGiHCANegp6UchHL/yolCQq2Wb9F2rsV1LZiK GhJIgWYygLnQVYwFDcvdBSL0VOymx7KaAD4c2Gb1OexAIK6YyMKugPko/ Gm0F8zEbGTlhznUVpz4rW/SYRGpjQHurg9JFzjNZ20ENxBW3qwtvrs3rv A==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436053956" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436053956" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:09:15 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849731" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:09:09 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 02/11] timekeeping: Add function to convert realtime to base clock Date: Wed, 7 Feb 2024 11:38:45 +0530 Message-Id: <20240207060854.6524-3-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219355469405557 X-GMAIL-MSGID: 1790219355469405557 From: Lakshmi Sowjanya D Introduce an interface, ktime_real_to_base_clock() to convert realtime to base clock. Convert the base clock to the system clock using convert_base_to_cs() in get_device_system_crosststamp(). Add the helper function timekeeping_clocksource_has_base(), to check whether the current clocksource has the same base clock. Co-developed-by: Thomas Gleixner Signed-off-by: Thomas Gleixner Co-developed-by: Christopher S. Hall Signed-off-by: Christopher S. Hall Signed-off-by: Lakshmi Sowjanya D --- include/linux/timekeeping.h | 6 ++ kernel/time/timekeeping.c | 112 +++++++++++++++++++++++++++++++++++- 2 files changed, 116 insertions(+), 2 deletions(-) diff --git a/include/linux/timekeeping.h b/include/linux/timekeeping.h index 7e50cbd97f86..1b2a4a37bf93 100644 --- a/include/linux/timekeeping.h +++ b/include/linux/timekeeping.h @@ -275,12 +275,18 @@ struct system_device_crosststamp { * timekeeping code to verify comparability of two cycle values. * The default ID, CSID_GENERIC, does not identify a specific * clocksource. + * @nsecs: @cycles is in nanoseconds. */ struct system_counterval_t { u64 cycles; enum clocksource_ids cs_id; + bool nsecs; }; +extern bool ktime_real_to_base_clock(ktime_t treal, + enum clocksource_ids base_id, u64 *cycles); +extern bool timekeeping_clocksource_has_base(enum clocksource_ids id); + /* * Get cross timestamp between system clock and device clock */ diff --git a/kernel/time/timekeeping.c b/kernel/time/timekeeping.c index 0ff065c5d25b..e68ecd77ee34 100644 --- a/kernel/time/timekeeping.c +++ b/kernel/time/timekeeping.c @@ -1191,6 +1191,89 @@ static bool cycle_between(u64 before, u64 test, u64 after) return false; } +static bool convert_clock(u64 *val, u32 numerator, u32 denominator) +{ + u64 rem, res; + + if (numerator == 0 || denominator == 0) + return false; + + res = div64_u64_rem(*val, denominator, &rem) * numerator; + *val = res + div_u64(rem * numerator, denominator); + return true; +} + +static bool convert_base_to_cs(struct system_counterval_t *scv) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + + /* The timestamp was taken from the time keeper clock source */ + if (cs->id == scv->cs_id) + return true; + + /* Check whether cs_id matches the base clock */ + if (!base || base->id != scv->cs_id) + return false; + + /* Avoid conversion to a less precise clock */ + if (scv->nsecs && cs->freq_khz != 0 && base->freq_khz < cs->freq_khz) { + if (!convert_clock(&scv->cycles, cs->freq_khz, USEC_PER_SEC)) + return false; + } else { + if (scv->nsecs) { + if (!convert_clock(&scv->cycles, base->freq_khz, USEC_PER_SEC)) + return false; + } + if (!convert_clock(&scv->cycles, base->numerator, base->denominator)) + return false; + } + scv->cycles += base->offset; + return true; +} + +static bool convert_cs_to_base(u64 *cycles, enum clocksource_ids base_id) +{ + struct clocksource *cs = tk_core.timekeeper.tkr_mono.clock; + struct clocksource_base *base = cs->base; + + /* Check whether base_id matches the base clock */ + if (!base || base->id != base_id) + return false; + + *cycles -= base->offset; + if (!convert_clock(cycles, base->denominator, base->numerator)) + return false; + return true; +} + +static u64 convert_ns_to_cs(u64 delta) +{ + struct tk_read_base *tkr = &tk_core.timekeeper.tkr_mono; + + return div_u64((delta << tkr->shift) - tkr->xtime_nsec, tkr->mult); +} + +bool ktime_real_to_base_clock(ktime_t treal, enum clocksource_ids base_id, u64 *cycles) +{ + struct timekeeper *tk = &tk_core.timekeeper; + unsigned int seq; + u64 delta; + + do { + seq = read_seqcount_begin(&tk_core.seq); + delta = (u64)treal - tk->tkr_mono.base_real; + if (delta > tk->tkr_mono.clock->max_idle_ns) + return false; + *cycles = tk->tkr_mono.cycle_last + convert_ns_to_cs(delta); + if (!convert_cs_to_base(cycles, base_id)) + return false; + } while (read_seqcount_retry(&tk_core.seq, seq)); + + return true; +} +EXPORT_SYMBOL_GPL(ktime_real_to_base_clock); + /** * get_device_system_crosststamp - Synchronously capture system/device timestamp * @get_time_fn: Callback to get simultaneous device time and @@ -1236,8 +1319,7 @@ int get_device_system_crosststamp(int (*get_time_fn) * system counter value is the same as for the currently * installed timekeeper clocksource */ - if (system_counterval.cs_id == CSID_GENERIC || - tk->tkr_mono.clock->id != system_counterval.cs_id) + if (!convert_base_to_cs(&system_counterval)) return -ENODEV; cycles = system_counterval.cycles; @@ -1304,6 +1386,32 @@ int get_device_system_crosststamp(int (*get_time_fn) } EXPORT_SYMBOL_GPL(get_device_system_crosststamp); +/** + * timekeeping_clocksource_has_base - Check whether the current clocksource + * has a base clock + * @id: The clocksource ID to check for + * + * Note: The return value is a snapshot which can become invalid right + * after the function returns. + * + * Return: true if the timekeeper clocksource has a base clock with @id, + * false otherwise + */ +bool timekeeping_clocksource_has_base(enum clocksource_ids id) +{ + unsigned int seq; + bool ret; + + do { + seq = read_seqcount_begin(&tk_core.seq); + ret = tk_core.timekeeper.tkr_mono.clock->base ? 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bh=9bM3pFe73YGrSI7VbFylL5q703Z79WRvHVA5lUksMX4=; b=hMmfSPYNj2tJt+IwWSUPD9lj5ZcyZ/N2uA/1pg/Q+ZWXh9R9BMWSXquq K8sjeAZvectoQxu31DVcQ38K7QecgY65XgewFQn7a0SN+r3WfYcVfWzkn W4io4jILZb9/+mbS/bAKVIpPbxPwOYeH4UeizvvMKE39gdTWOeygGpmSA xwr7Xb8S3NvY0ti/u0CwCedDvgLI6YkCQ8tciSYRthPc/6GbPMAB50DbS 00BXo4KgFr8llMc+3VZf28jK3RjYdRNSAZiwGkc5wx4cGy3/RThMN51iZ yyr8q+vQRq5ctkpbALYhn/964oJREleMB2ZhDsKwb67kUbRDYs8mmSxSS A==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436053970" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436053970" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:09:22 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849741" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:09:16 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 03/11] e10002: remove convert_art_to_tsc() Date: Wed, 7 Feb 2024 11:38:46 +0530 Message-Id: <20240207060854.6524-4-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219431294837739 X-GMAIL-MSGID: 1790219431294837739 From: Thomas Gleixner Remove convert_art_to_tsc() function call, Pass system clock cycles and clocksource ID as input to get_device_system_crosststamp(). Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/e1000e/ptp.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/e1000e/ptp.c b/drivers/net/ethernet/intel/e1000e/ptp.c index bbcfd529399b..89d57dd911dc 100644 --- a/drivers/net/ethernet/intel/e1000e/ptp.c +++ b/drivers/net/ethernet/intel/e1000e/ptp.c @@ -124,7 +124,8 @@ static int e1000e_phc_get_syncdevicetime(ktime_t *device, sys_cycles = er32(PLTSTMPH); sys_cycles <<= 32; sys_cycles |= er32(PLTSTMPL); - *system = convert_art_to_tsc(sys_cycles); + system->cycles = sys_cycles; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Wed Feb 7 06:08:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031158dyb; Tue, 6 Feb 2024 22:11:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IHu6SKeuLAj196zcBKWG9AeRJdprY8qhkpxVmNtsPlBC2biMakCmmYfr9LaQ9u/uS9WlveY X-Received: by 2002:ac8:57d5:0:b0:42b:f5f2:e51a with SMTP id w21-20020ac857d5000000b0042bf5f2e51amr9748488qta.1.1707286275406; Tue, 06 Feb 2024 22:11:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286275; cv=pass; d=google.com; s=arc-20160816; b=njKn3NHojRlagirwnQp0GK5XXagNC4zG4eIURCYBd9iBc7El54CUK3w3xozV2OD4jM H8aAPuxvjufOq+aEEN9Lj3oVj6hHUJqjksOPZZ9xw7JI5j9uXXSnXwEhDyPKqo2EgzIO 4pQ+K73+yH8w9AVqev1QXqvy6YqvAoyqZ/lIZTzU+k5wkCcjUhQZqo9J7Ifcv1JWv1BM XMQGtnOj4M2vfpEQgn//fj0Sf7PiYyaxgpZvGuwJF92VPGuSsvP5aczZdt9FS2oPxjks uRSUEQSwdRLUsxgj6XWLMc6mfMhwm9/Rr4nNCaJNjc8gPpuZa6kBTSmXTtYQsZX7RdqW C/kw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ZMVsDlHEi/hhbc7fNNZPtLZD9sTr8uGUpT+Hx2HmiTk=; fh=sV+K451Mjujb069iLQeqdpMa2IkMLhVFKv7NllvY8vA=; b=pkLbxWBstIv0Xc/1Rg2pa9LZMn96Kvb1bRSVO0a0HDnB7PiYxmNNIgUTV6Mb6lhMx1 nkrKUTdXEb5CJJSZ+HMYsBHqGLB1eJJtLHZFL7u6HxA0pE+VsCoCvRig+WL5U8JoSVoD NRV9yyBBIHYS3rs1GBB11R0jzg/Vo8yZmE/nKHu52yPzDGC+slKhn4Tpoo8BxI8p3ki8 8bW8/gpVsc4bnudfmfMJxrnZ1UGxT9sKEkuhBUo/WqzA8B5h9nzvRVT6zaDWe2NQ+32L 44JmRflnqJ1Htsi5dCfffcW9IRjIhCcvTEhqcJB4R+NWWYbpXpYhNuYNMfxD9rC/hvwX r/Pg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="cRLhPJ/O"; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-55997-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55997-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCVVn7iYhxMKYmb2jeztFsQVex4m34ZLHKO97w3siVG8FDsDtxMJnUc5XeU930hunXkDOwAU0I3eCGDjz9bdNADi3avO2A== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/igc/igc_ptp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/igc/igc_ptp.c b/drivers/net/ethernet/intel/igc/igc_ptp.c index 885faaa7b9de..0f568fc4b902 100644 --- a/drivers/net/ethernet/intel/igc/igc_ptp.c +++ b/drivers/net/ethernet/intel/igc/igc_ptp.c @@ -901,7 +901,11 @@ static bool igc_is_crosststamp_supported(struct igc_adapter *adapter) static struct system_counterval_t igc_device_tstamp_to_system(u64 tstamp) { #if IS_ENABLED(CONFIG_X86_TSC) && !defined(CONFIG_UML) - return convert_art_ns_to_tsc(tstamp); + return (struct system_counterval_t) { + .cs_id = CSID_X86_ART, + .cycles = tstamp, + .nsecs = true, + }; #else return (struct system_counterval_t) { }; #endif From patchwork Wed Feb 7 06:08:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197757 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031581dyb; Tue, 6 Feb 2024 22:12:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IFsBdrf2rAKuW5z6B2j7n18Upy9X4nIuc/Y6xt1G8UHSTAWeon9ypgfbPl2oPrJfQuyh9P/ X-Received: by 2002:a05:6a21:920e:b0:19e:9c34:f369 with SMTP id tl14-20020a056a21920e00b0019e9c34f369mr3585231pzb.16.1707286348660; Tue, 06 Feb 2024 22:12:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286348; cv=pass; d=google.com; s=arc-20160816; b=sNS530mJfpFvuhZR2Q9h7mmm3siLr2koJOEZ8pmj2dxxzcDd6gVnJ3YQYi05nOWm9e Wb5TDGEp97zvi4VgFG2mkVv+GHV7HwKKkk0crVcIrTYjAqne8Xyn1I90Y52YOqEQgZon 0Tt7QcvZGXEbqdLxUARLVBFuCEHhHcB1A/gybQ5BGyKgSazWh5Q56t19OY+Fd5/JwgZQ PuvNNyw2pa4BV0JuTSFeG0Ib1pi/A1mJ9+HKLjDsWXNDaUgxd69rJeDGzNr3aPPY6jg7 TerMXr0pfVT59+Y8tKcVZ2+ai9gqa74Wclv/pqWx3wTs7gCy89m5IKM2UQECHURTxAgD Zbkw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=qbDf6mDOr5pUTTrGJy5r3HxwSzx5reuigJeU16xqtBs=; fh=cTf5hXDLUyErqXk6ZUX5pNE1MT7LG5qTTMaE4QySQNc=; b=Ch0lqefR7/x2R3uArnqAkoGrXTMOr9vHeqHi3eWuR5mg3ES/+sVUARJ8Ox5v+wIQLr tgApDZdX9TXoCV5pCBEgiu7biSKKgdkAzijdOVX5JQM4K4eDPCy+znnXyJ+WR/fTtjaI hBuBGuh+Js0/YJoQ2KeDWTlPrLebgs2KD94y35+hhzP1Rxgf13aYWuBurAUsYwmW4xg8 c20BZAjGEVS7gbeV/Q4KqT7oXIHb6w9xN5qROVk/VtSADphZUGvQloQ/uxxrrRZgRxqg bkiwKPTZfNNo3Lyt3CPejccBjxrbdMB8azL+iRcMLCgqT5k24gRPypv19jgcykGy6Ju7 EyHA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=Sz7nWrtd; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-55998-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55998-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCWSUwzPzrT4Sm5+7gfs2MIp0LGQZBLmb0MSic8apc38V5ym897AEIMOQPQgPsRxogxbDHS1aa0ml73mmG2k97By3K9H6w== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c index 60283543ffc8..e73fa34237d3 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c @@ -390,10 +390,11 @@ static int intel_crosststamp(ktime_t *device, *device = ns_to_ktime(ptp_time); read_unlock_irqrestore(&priv->ptp_lock, flags); get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); - *system = convert_art_to_tsc(art_time); + system->cycles = art_time; } system->cycles *= intel_priv->crossts_adj; + system->cs_id = CSID_X86_ART; priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; return 0; From patchwork Wed Feb 7 06:08:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197755 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031414dyb; Tue, 6 Feb 2024 22:11:57 -0800 (PST) X-Google-Smtp-Source: AGHT+IE4WYuG4swHu5q5En6xh+9a7da0R4g5snEUZPuVgLfJ5fu3ESxE3pTeT9fkILKDE0NnvpCD X-Received: by 2002:a17:90a:4383:b0:295:fbbc:6daa with SMTP id r3-20020a17090a438300b00295fbbc6daamr1660559pjg.19.1707286317149; Tue, 06 Feb 2024 22:11:57 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286317; cv=pass; d=google.com; s=arc-20160816; b=d6VH0iy8MXV/+yo7+stKA2bkNgri5N+DuUKTF8K0KEjRtF34XSa9CQ+6JWL7c/10oL sUSvwIpo+hldMtccbtu1hyTxq4g8f3mVdLilNxC3s9LmTKs+MZn1LPA/ZpDodBAosJyg OpoBSSAdaViMQF04numVpRBbfKgJ+G4yoLW5ZKTsWZJLilA/J/GunnK5YDX+zggNYMKs 6+in5zPGjjWNMIHRAhpai/UneLQZiURf/TV0/TFZ/I3sqOHK0g/9CaO0VasWXM2C7cb2 u9zvTbnDFhvj27E7GhNB97rDcg4YvX8tZCEfPSLIpxBAFXiDTnbc4SPAjgGzDltQbpd3 THFQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=3oqOWK4mlIlAwgo8wYo2agAGNTVZM1RQKGIq1lFPuXY=; fh=IoNZ6n42+DTag5bAAj43mhGnnMISSykcvyosTbbRkGg=; b=KpqwjGe9IHvxFsmse0GMP+VL2vZhk9doKuPCg0UnS/8fCpfBLDV5uFKv96+ZAaBEXn PEG+mC3oux8+u+aRzUtKrFbeDoBXeb/HvoOLVuSrsuYfSN4Yc3HrGGVjtPVaaCrguSNw ueKKNSbK3jIobIVAC+ji+oBPz6qwGrX9z24IZ+tVtu8OmUsJSMyDtQmwGOPI6buGaNlT H59t7cmtn5dnLKhG0CgmIfxF10AITtD9zVkFxu8g+/rBNK2W12q29LQGa0muiPXKsaR8 xX8kw/sDny2lSZ2f5KDcNggykyk8Avvgq+66wbTnKIBuvHfOnnDPlF/yCZMdNABIU2QS 8O2w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=KQ0raAcm; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-55999-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55999-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCVn+R8lzj61hDchRNg3SQ1gLeQ8wmlDPKy2YQ1aNiH8JokBIjUsifTv8WeLosc63MBWOyYFI8Z7Flvb7S4+ZSkzVMqnog== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- sound/pci/hda/hda_controller.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/sound/pci/hda/hda_controller.c b/sound/pci/hda/hda_controller.c index 3e7bfeee84fd..5206adedb000 100644 --- a/sound/pci/hda/hda_controller.c +++ b/sound/pci/hda/hda_controller.c @@ -455,7 +455,8 @@ static int azx_get_sync_time(ktime_t *device, *device = ktime_add_ns(*device, (wallclk_cycles * NSEC_PER_SEC) / ((HDA_MAX_CYCLE_VALUE + 1) * runtime->rate)); - *system = convert_art_to_tsc(tsc_counter); + system->cycles = tsc_counter; + system->cs_id = CSID_X86_ART; return 0; } From patchwork Wed Feb 7 06:08:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031536dyb; Tue, 6 Feb 2024 22:12:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFoaACt2Z2aidyIUvH7okGd1zgWl0XqXIeEeQQkhuHXPAWRShHBS/vS+x5S8NIZJzkk2Rhh X-Received: by 2002:a05:6358:528b:b0:176:40fb:e123 with SMTP id g11-20020a056358528b00b0017640fbe123mr1901422rwa.5.1707286338213; Tue, 06 Feb 2024 22:12:18 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286338; cv=pass; d=google.com; s=arc-20160816; b=hDMNX0fSz7iTsUuCSsePeY711zQ/tB6peiK786TrOTM9aJ8Re/PRbm+68yI5yWJ1pt Wu/IqhfYTiaKLgZzuj9stR9yUG5GH++LIhnubwCAB3m403F2CBWLU9DHzEtv8+D/0Efl 6zM3xSGsW2xOTrddt9AM7JSbHaBPeRAiULG8VO0bEl2Qe4BnDGtxlO1WbOT0UleUrHJO 2Tq2p1dhGL65mbcF2eKVFmNUr94VRHBHwXBQPXUnRy0JTti6NBzATHzgdTl5yz2nT5BY ny4dap87rPCrvdrM7ISuj/B+yf4uWzeS5Tu4yK7W63krCh9UGseY0eOyd+7qobvjUdQh EFqw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=T7N1fL6c3qpJ/euIKukZsyS6B5nxXU+Kxr4k1JyagBY=; fh=EuUh5F0SdLghCUIIUDtTEWWqedc7XOBGncbpNa1tU9w=; b=RQ6nlfDSv9Q3WJZ7t56tMN1zvWl/+Y3Wl5dG2Je4DXGwa9RXtf0lvCkYAzTtDDA9cs cF7LPJC7LT/RVgLW2RN3hPxicCVs2bxcCb0XsoFN1UEdlMMgvgI339u/1pm9Ai8ytSI6 Q9glp69pC2JN8krrvtEt3LSy5dbth2pGo7U1pauTGYT22Qa6PXIZ7BQE7K2mFKfeChU+ ZDRlZC2hA4e6gbCHBc2C25L1e0siUT30eDIYL4Ht2vkjWJYn6JpQ3x4X0/5H4jvMcmNW sFkmxgeIqYdRnhfKZqHUxB4jpdWO5T5QFhrRHTFj628RikrhtM2SXEtTCJKXnXRJSTjC zxYg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=h4qqeLTI; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-56000-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56000-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCV+VV7wwFcLLqWGd0FxagME7auUnP+LxHSG1t9SHhWyuvGtOxD0Z9HhmvQ2leNmq2cHyTiy/ULfDBQJfKhHmFEhDLVjqA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Thomas Gleixner Signed-off-by: Lakshmi Sowjanya D --- drivers/net/ethernet/intel/ice/ice_ptp.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/net/ethernet/intel/ice/ice_ptp.c b/drivers/net/ethernet/intel/ice/ice_ptp.c index 3b6605c8585e..104b3f7a7cfc 100644 --- a/drivers/net/ethernet/intel/ice/ice_ptp.c +++ b/drivers/net/ethernet/intel/ice/ice_ptp.c @@ -2101,7 +2101,7 @@ ice_ptp_get_syncdevicetime(ktime_t *device, hh_ts_lo = rd32(hw, GLHH_ART_TIME_L); hh_ts_hi = rd32(hw, GLHH_ART_TIME_H); hh_ts = ((u64)hh_ts_hi << 32) | hh_ts_lo; - *system = convert_art_ns_to_tsc(hh_ts); + system->cycles = hh_ts; /* Read Device source clock time */ hh_ts_lo = rd32(hw, GLTSYN_HHTIME_L(tmr_idx)); hh_ts_hi = rd32(hw, GLTSYN_HHTIME_H(tmr_idx)); From patchwork Wed Feb 7 06:08:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197758 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031687dyb; Tue, 6 Feb 2024 22:12:41 -0800 (PST) X-Forwarded-Encrypted: i=3; AJvYcCWDER2Vry5hILVLFqzBhUL+sI14oWbL0lLiOYPGiSEUiQvlAUMiy3AEyZA5X1P4anqI2lnwNRMFJIOPIrpx0j1Ux3ymwA== X-Google-Smtp-Source: AGHT+IG+mlOlaQ0F2Y1Cra6GMRo+NE57Pb23ASkK7R9j9UjyrrG6QGASgPV3n9DiNYcIivP5hr8G X-Received: by 2002:a2e:9b8f:0:b0:2d0:aae8:2297 with SMTP id z15-20020a2e9b8f000000b002d0aae82297mr3418089lji.5.1707286361316; Tue, 06 Feb 2024 22:12:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286361; cv=pass; d=google.com; s=arc-20160816; b=bhrK4o5hRrldMSdfgU5EJTK+hSVpZACRAxoSPlNIiZWxr0mdCAmDrV+UKLIn8WFO44 vMSPEksrnTcs7LpSV4pwUNUxukHG1a9p0RWv0RxMqk9eeyZNtfMDMlXuERens3SQ3mvC 8TJx9L4vP4dwGxPBB6YyJSZxD115LT3umyUhQEQlSjdiaPA7Is0Gtrfefro0O6fcyEBV eW0Lz+cgsrvLT4zYYtDxdPh0bbHPNGrsEz26o1USYHBiCxZnThKongYJ9tP+KywvtZNk whpfcRwiz2SKj3946MTDDrGbstf0fMh44s8eWcqtpzSHJABRFZqslXBNMtY+psuw9ofr 2tgw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=ywgSWWjzGSSZJLmzw5t9/86dBBZS8eMPYf1yOGQSY50=; fh=q8gByZClfBfq6wJ31YOG63AnOq1GzROpQWXlLhTOVWM=; b=eJ+idJfyfVClBmmOmRQTn12ttqAT9x13cS+yMgdsJdP7Woc9iHeOhHoUu2Q1F9S7Nz 9OVYE9MeWA0dgcG/SfrmhiscFtuqoiizUpyEeNiMJ1KzDrM84PF+2wN7TBXmI0f2LDPs /NO0fHu82yFYJxZUh6kN4QO8fN3pmFe6qTXhZNcXeMkZVx7nAsb5e7lMqoIc3ZO9ej7R UB4h4BeSndBu/elusYCVWTDU8VgxbE2Q/A7fHLBIusv+cMveWQNudRONVrJ/gM6CZ7Kg zS+MFlXkEvj2qUt2caWYwV3SNH9Yk39ZNcxaXY2OpDWexWGk7WZED797jFRPRS8hLlOK RqvQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=j+Xok4Yb; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-56001-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56001-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCVl6wfazWTGWo7m8cPXDtoeUEsmoaGDJjGK0chVpjKttOY0j206AsFA7dIwVO5pKDV6IGb2kIIiI33OLhVO1B6lScFWHg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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bh=t6cpcq7SdAhCh1eL4xC81g6usIlQlk83sietgrk1PRY=; b=j+Xok4YbiGYyrVjN3rFmLwJEthgCtr8XD3b99z7IYmTa88YWRmj5hORt mI/W5UCItN+/D4E13pNc8dQ5NlVKd7F/gEIurMTI2hRdKohQgi2EwEtqI 6wKLgVNDbJHW/5ujZO0KxAV5nPgsPSrQlfXl8P46Is5J4ozdUj5+NG3sV LlXKwH7Ted5giWcSZp1H48eKVahufOBa4YxaS56tAKB0OpUUuXQBNbZxN 2ms/PnYzXN340k8mJKWu03AIO3XcywnkEQCrk7sT+qlzbsogr6mye5I5a fN+Otl16NDqSFjqQr5HaO6cAZD6u/pTTTz7VaUznjmCuZQXrYr8wvtfmu Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436054054" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436054054" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:09:55 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849871" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:09:49 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 08/11] x86/tsc: Remove art to tsc conversion functions which are obsolete Date: Wed, 7 Feb 2024 11:38:51 +0530 Message-Id: <20240207060854.6524-9-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219503503849552 X-GMAIL-MSGID: 1790219503503849552 From: Lakshmi Sowjanya D The convert_art_to_tsc() and convert_art_ns_to_tsc() interfaces are no longer required. This conversion is internally done in get_device_system_crosststamp() using convert_base_to_cs(). Signed-off-by: Lakshmi Sowjanya D --- arch/x86/include/asm/tsc.h | 3 -- arch/x86/kernel/tsc.c | 57 -------------------------------------- 2 files changed, 60 deletions(-) diff --git a/arch/x86/include/asm/tsc.h b/arch/x86/include/asm/tsc.h index 594fce0ca744..5e36495cc821 100644 --- a/arch/x86/include/asm/tsc.h +++ b/arch/x86/include/asm/tsc.h @@ -27,9 +27,6 @@ static inline cycles_t get_cycles(void) } #define get_cycles get_cycles -extern struct system_counterval_t convert_art_to_tsc(u64 art); -extern struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns); - extern void tsc_early_init(void); extern void tsc_init(void); extern void mark_tsc_unstable(char *reason); diff --git a/arch/x86/kernel/tsc.c b/arch/x86/kernel/tsc.c index 96a5c4c2c6ee..646f716dc32a 100644 --- a/arch/x86/kernel/tsc.c +++ b/arch/x86/kernel/tsc.c @@ -1297,63 +1297,6 @@ int unsynchronized_tsc(void) return 0; } -/* - * Convert ART to TSC given numerator/denominator found in detect_art() - */ -struct system_counterval_t convert_art_to_tsc(u64 art) -{ - u64 tmp, res, rem; - - rem = do_div(art, art_base_clk.denominator); - - res = art * art_base_clk.numerator; - tmp = rem * art_base_clk.numerator; - - do_div(tmp, art_base_clk.denominator); - res += tmp + art_base_clk.offset; - - return (struct system_counterval_t) { - .cs_id = have_art ? CSID_X86_TSC : CSID_GENERIC, - .cycles = res - }; -} -EXPORT_SYMBOL(convert_art_to_tsc); - -/** - * convert_art_ns_to_tsc() - Convert ART in nanoseconds to TSC. - * @art_ns: ART (Always Running Timer) in unit of nanoseconds - * - * PTM requires all timestamps to be in units of nanoseconds. When user - * software requests a cross-timestamp, this function converts system timestamp - * to TSC. - * - * This is valid when CPU feature flag X86_FEATURE_TSC_KNOWN_FREQ is set - * indicating the tsc_khz is derived from CPUID[15H]. Drivers should check - * that this flag is set before conversion to TSC is attempted. - * - * Return: - * struct system_counterval_t - system counter value with the ID of the - * corresponding clocksource - */ - -struct system_counterval_t convert_art_ns_to_tsc(u64 art_ns) -{ - u64 tmp, res, rem; - - rem = do_div(art_ns, USEC_PER_SEC); - - res = art_ns * tsc_khz; - tmp = rem * tsc_khz; - - do_div(tmp, USEC_PER_SEC); - res += tmp; - return (struct system_counterval_t) { - .cs_id = have_art ? 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bh=vQX8zNWVTLYYy3JY3x1fHcqNprd6z6ajaQA72ST/yRk=; b=eiyzYDRAddYRckpH7NHd09t3IZwu7m+Ab4HzUefn8zMUgNX4OJPKQb+i OgiRtGKf1pG9SODbgLbTvWOB2OrGgpnswma/qrPwuwAwADoBUtfc/aHHe vnDe40PtAqsk5RlSYAU+rZk/w9ZHkcvTO2gtgeaF0z+UClq+9SQGzc9IJ 7sCJEU4Fy/UOd6rvjWBEhxx02Yt9Xx5av2JSxGZFGO88EYfF996cxXrP4 ZOV8OByxZAXTaPmVc/Vin4AUPGvLFeAHJ2dfkhVGhxvPKg8Ajc6jfXRkX nYxIVD7ydD0GWu1N34qoVHt2rVa6+c9Bm5MR8xrFlnkiaZUKzXZIn5tzv Q==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436054093" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436054093" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:10:03 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849905" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:09:56 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 09/11] pps: generators: Add PPS Generator TIO Driver Date: Wed, 7 Feb 2024 11:38:52 +0530 Message-Id: <20240207060854.6524-10-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219950976497618 X-GMAIL-MSGID: 1790219950976497618 From: Lakshmi Sowjanya D The Intel Timed IO PPS generator driver outputs a PPS signal using dedicated hardware that is more accurate than software actuated PPS. The Timed IO hardware generates output events using the ART timer. The ART timer period varies based on platform type, but is less than 100 nanoseconds for all current platforms. Timed IO output accuracy is within 1 ART period. PPS output is enabled by writing '1' the 'enable' sysfs attribute. The driver uses hrtimers to schedule a wake-up 10 ms before each event (edge) target time. At wakeup, the driver converts the target time in terms of CLOCK_REALTIME to ART trigger time and writes this to the Timed IO hardware. The Timed IO hardware generates an event precisely at the requested system time without software involvement. Co-developed-by: Christopher Hall Signed-off-by: Christopher Hall Co-developed-by: Pandith N Signed-off-by: Pandith N Co-developed-by: Thejesh Reddy T R Signed-off-by: Thejesh Reddy T R Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Eddie Dong Reviewed-by: Andy Shevchenko --- drivers/pps/generators/Kconfig | 16 ++ drivers/pps/generators/Makefile | 1 + drivers/pps/generators/pps_gen_tio.c | 245 +++++++++++++++++++++++++++ 3 files changed, 262 insertions(+) create mode 100644 drivers/pps/generators/pps_gen_tio.c diff --git a/drivers/pps/generators/Kconfig b/drivers/pps/generators/Kconfig index d615e640fcad..0f090932336f 100644 --- a/drivers/pps/generators/Kconfig +++ b/drivers/pps/generators/Kconfig @@ -12,3 +12,19 @@ config PPS_GENERATOR_PARPORT If you say yes here you get support for a PPS signal generator which utilizes STROBE pin of a parallel port to send PPS signals. It uses parport abstraction layer and hrtimers to precisely control the signal. + +config PPS_GENERATOR_TIO + tristate "TIO PPS signal generator" + depends on X86 && CPU_SUP_INTEL + help + If you say yes here you get support for a PPS TIO signal generator + which generates a pulse at a prescribed time based on the system clock. + It uses time translation and hrtimers to precisely generate a pulse. + This hardware is present on 2019 and newer Intel CPUs. However, this + driver is not useful without adding highly specialized hardware outside + the Linux system to observe these pulses. + + To compile this driver as a module, choose M here: the module + will be called pps_gen_tio. + + If unsure, say N. diff --git a/drivers/pps/generators/Makefile b/drivers/pps/generators/Makefile index 2d56dd0495d5..07004cfd3996 100644 --- a/drivers/pps/generators/Makefile +++ b/drivers/pps/generators/Makefile @@ -4,6 +4,7 @@ # obj-$(CONFIG_PPS_GENERATOR_PARPORT) += pps_gen_parport.o +obj-$(CONFIG_PPS_GENERATOR_TIO) += pps_gen_tio.o ifeq ($(CONFIG_PPS_DEBUG),y) EXTRA_CFLAGS += -DDEBUG diff --git a/drivers/pps/generators/pps_gen_tio.c b/drivers/pps/generators/pps_gen_tio.c new file mode 100644 index 000000000000..3ee271524482 --- /dev/null +++ b/drivers/pps/generators/pps_gen_tio.c @@ -0,0 +1,245 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Intel PPS signal Generator Driver + * + * Copyright (C) 2023 Intel Corporation + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#define TIOCTL 0x00 +#define TIOCOMPV 0x10 + +/* Control Register */ +#define TIOCTL_EN BIT(0) +#define TIOCTL_DIR BIT(1) +#define TIOCTL_EP GENMASK(3, 2) +#define TIOCTL_EP_RISING_EDGE FIELD_PREP(TIOCTL_EP, 0) +#define TIOCTL_EP_FALLING_EDGE FIELD_PREP(TIOCTL_EP, 1) +#define TIOCTL_EP_TOGGLE_EDGE FIELD_PREP(TIOCTL_EP, 2) + +#define SAFE_TIME_NS (10 * NSEC_PER_MSEC) /* Safety time to set hrtimer early */ +#define MAGIC_CONST (NSEC_PER_SEC - SAFE_TIME_NS) +#define ART_HW_DELAY_CYCLES 2 + +struct pps_tio { + struct hrtimer timer; + struct device *dev; + spinlock_t lock; + struct attribute_group attrs; + void __iomem *base; + bool enabled; +}; + +static inline u32 pps_ctl_read(struct pps_tio *tio) +{ + return readl(tio->base + TIOCTL); +} + +static inline void pps_ctl_write(struct pps_tio *tio, u32 value) +{ + writel(value, tio->base + TIOCTL); +} + +/* For COMPV register, It's safer to write higher 32-bit followed by lower 32-bit */ +static inline void pps_compv_write(struct pps_tio *tio, u64 value) +{ + hi_lo_writeq(value, tio->base + TIOCOMPV); +} + +static inline ktime_t first_event(struct pps_tio *tio) +{ + return ktime_set(ktime_get_real_seconds() + 1, MAGIC_CONST); +} + +static u32 pps_tio_disable(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_ctl_read(tio); + pps_compv_write(tio, 0); + + ctrl &= ~TIOCTL_EN; + pps_ctl_write(tio, ctrl); + + return ctrl; +} + +static void pps_tio_direction_output(struct pps_tio *tio) +{ + u32 ctrl; + + ctrl = pps_tio_disable(tio); + + /* We enable the device, be sure that the 'compare' value is invalid */ + pps_compv_write(tio, 0); + + ctrl &= ~(TIOCTL_DIR | TIOCTL_EP); + ctrl |= TIOCTL_EP_TOGGLE_EDGE; + pps_ctl_write(tio, ctrl); + + ctrl |= TIOCTL_EN; + pps_ctl_write(tio, ctrl); +} + +static bool pps_generate_next_pulse(struct pps_tio *tio, ktime_t expires) +{ + u64 art; + + if (!ktime_real_to_base_clock(expires, CSID_X86_ART, &art)) { + pps_tio_disable(tio); + return false; + } + + pps_compv_write(tio, art - ART_HW_DELAY_CYCLES); + return true; +} + +static enum hrtimer_restart hrtimer_callback(struct hrtimer *timer) +{ + struct pps_tio *tio = container_of(timer, struct pps_tio, timer); + ktime_t expires, now; + + guard(spinlock)(&tio->lock); + + expires = hrtimer_get_expires(timer); + now = ktime_get_real(); + + if (now - expires < SAFE_TIME_NS) { + if (!pps_generate_next_pulse(tio, expires + SAFE_TIME_NS)) + return HRTIMER_NORESTART; + } + + hrtimer_forward(timer, now, NSEC_PER_SEC / 2); + return HRTIMER_RESTART; +} + +static ssize_t enable_store(struct device *dev, struct device_attribute *attr, const char *buf, + size_t count) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + bool enable; + int err; + + err = kstrtobool(buf, &enable); + if (err) + return err; + + guard(spinlock_irqsave)(&tio->lock); + if (enable && !tio->enabled) { + if (!timekeeping_clocksource_has_base(CSID_X86_ART)) { + dev_err(tio->dev, "PPS cannot be started as clock is not related to ART"); + return -EPERM; + } + pps_tio_direction_output(tio); + hrtimer_start(&tio->timer, first_event(tio), HRTIMER_MODE_ABS); + tio->enabled = true; + } else if (!enable && tio->enabled) { + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + tio->enabled = false; + } + return count; +} + +static ssize_t enable_show(struct device *dev, struct device_attribute *devattr, char *buf) +{ + struct pps_tio *tio = dev_get_drvdata(dev); + u32 ctrl; + + ctrl = pps_ctl_read(tio); + ctrl &= TIOCTL_EN; + + return sysfs_emit(buf, "%u\n", ctrl); +} +static DEVICE_ATTR_RW(enable); + +static struct attribute *pps_tio_attrs[] = { + &dev_attr_enable.attr, + NULL +}; +ATTRIBUTE_GROUPS(pps_tio); + +static int pps_tio_probe(struct platform_device *pdev) +{ + struct pps_tio *tio; + + if (!(cpu_feature_enabled(X86_FEATURE_TSC_KNOWN_FREQ) && + cpu_feature_enabled(X86_FEATURE_ART))) { + dev_warn(&pdev->dev, "TSC/ART is not enabled"); + return -ENODEV; + } + + tio = devm_kzalloc(&pdev->dev, sizeof(*tio), GFP_KERNEL); + if (!tio) + return -ENOMEM; + + tio->dev = &pdev->dev; + tio->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(tio->base)) + return PTR_ERR(tio->base); + + pps_tio_disable(tio); + hrtimer_init(&tio->timer, CLOCK_REALTIME, HRTIMER_MODE_ABS); + tio->timer.function = hrtimer_callback; + spin_lock_init(&tio->lock); + tio->enabled = false; + platform_set_drvdata(pdev, tio); + + return 0; +} + +static int pps_tio_remove(struct platform_device *pdev) +{ + struct pps_tio *tio = platform_get_drvdata(pdev); + + hrtimer_cancel(&tio->timer); + pps_tio_disable(tio); + + return 0; +} + +static const struct acpi_device_id intel_pmc_tio_acpi_match[] = { + { "INTC1021" }, + { "INTC1022" }, + { "INTC1023" }, + { "INTC1024" }, + {} +}; +MODULE_DEVICE_TABLE(acpi, intel_pmc_tio_acpi_match); + +static struct platform_driver pps_tio_driver = { + .probe = pps_tio_probe, + .remove = pps_tio_remove, + .driver = { + .name = "intel-pps-generator", + .acpi_match_table = intel_pmc_tio_acpi_match, + .dev_groups = pps_tio_groups, + }, +}; +module_platform_driver(pps_tio_driver); + +MODULE_AUTHOR("Lakshmi Sowjanya D "); +MODULE_AUTHOR("Christopher Hall "); +MODULE_AUTHOR("Pandith N "); +MODULE_AUTHOR("Thejesh Reddy T R "); +MODULE_DESCRIPTION("Intel PMC Time-Aware IO Generator Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Feb 7 06:08:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197759 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2031964dyb; Tue, 6 Feb 2024 22:13:32 -0800 (PST) X-Google-Smtp-Source: AGHT+IGldXrWOa61VbvtwxkQchtBHT877VXw6UyDQciTa6nNqKvvqqaGCv2oB8iX4PzDh6SwbcRl X-Received: by 2002:a2e:9155:0:b0:2d0:5543:dcd3 with SMTP id q21-20020a2e9155000000b002d05543dcd3mr3605996ljg.3.1707286411930; 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bh=6PS4+2Ywv1DMIM5u9+tNfbsYVKa0PISW1H4pAS3IZH0=; b=hNBTfKVHiOQvJvGJmtLGzCRM+Z7ooOQVcC8L6+4jyuvlCKrPXAFpyDmD 7kLT032VSW9S+pZ8mPBBVkH7/Uot52VmmottkKGSHMHSzcH7QWH7gsJuD YXskFrgWrf+1OnrPL68iuRRa4aiYbwcbZArqGAEAkvRamGcGRGHWDGkuk rIZipmyKLLC2XHpFhrIHBUrw5SeCYHJfff2hnhZcxd5b3i+JLFKt+Eb+u X04ve7zoOU5Q6609wTCb0ZI7MF7u6gzvNdsvdTH/IQCZbBWTPPHyXOjsP zxeAkd5qekINTytSFBe9cl0g30ZJV1ymK6gBJFziAPiTemH7W8Wm866eP g==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436054098" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436054098" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:10:09 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849933" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:10:03 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 10/11] Documentation: driver-api: pps: Add Intel Timed I/O PPS generator Date: Wed, 7 Feb 2024 11:38:53 +0530 Message-Id: <20240207060854.6524-11-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219556709419413 X-GMAIL-MSGID: 1790219556709419413 From: Lakshmi Sowjanya D Add Intel Timed I/O PPS usage instructions. Co-developed-by: Pandith N Signed-off-by: Pandith N Signed-off-by: Lakshmi Sowjanya D Reviewed-by: Andy Shevchenko --- Documentation/driver-api/pps.rst | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/Documentation/driver-api/pps.rst b/Documentation/driver-api/pps.rst index 78dded03e5d8..52a6d5faf885 100644 --- a/Documentation/driver-api/pps.rst +++ b/Documentation/driver-api/pps.rst @@ -246,3 +246,25 @@ delay between assert and clear edge as small as possible to reduce system latencies. But if it is too small slave won't be able to capture clear edge transition. The default of 30us should be good enough in most situations. The delay can be selected using 'delay' pps_gen_parport module parameter. + + +Intel Timed I/O PPS signal generator +------------------------------------ + +Intel Timed I/O is a high precision device, present on 2019 and newer Intel +CPUs, that can generate PPS signals. + +Timed I/O and system time are both driven by same hardware clock. The signal +is generated with a precision of ~20 nanoseconds. The generated PPS signal +is used to synchronize an external device with system clock. For example, +share your clock with a device that receives PPS signal, generated by +Timed I/O device. There are dedicated Timed I/O pins to deliver the PPS signal +to an external device. + +Usage of Intel Timed I/O as PPS generator: + +Start generating PPS signal:: + $echo 1 > /sys/devices/platform/INTCxxxx\:00/enable + +Stop generating PPS signal:: + $echo 0 > /sys/devices/platform/INTCxxxx\:00/enable From patchwork Wed Feb 7 06:08:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "D, Lakshmi Sowjanya" X-Patchwork-Id: 197760 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp2032481dyb; Tue, 6 Feb 2024 22:15:11 -0800 (PST) X-Google-Smtp-Source: AGHT+IGukme6nlmhc0b6zRwA6NQ/owREI1gA30d/trYZgybmshb1Ynqf6pF2o9YjYPnvi/9EqOL3 X-Received: by 2002:a05:6808:13cb:b0:3be:3de9:68eb with SMTP id d11-20020a05680813cb00b003be3de968ebmr5732964oiw.39.1707286511623; Tue, 06 Feb 2024 22:15:11 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707286511; cv=pass; d=google.com; s=arc-20160816; b=azqQlsoV8BJp3/gU/bBQM1f44JM6eaKGKIlDEPtaRHZrk5QjY2K8fwclgDzB63a1tk nWeDwQPb3huqbGbuKy1h/ppbh6L7oEpQBFd8It83imSIQUJIwItXDHEyTxkNDKPhAjL/ W0gM4H19fFIoVFG8Kkt2tifwcG2VH4FFsg6e36UJi62L9eK+eIFkpRheQXyRa/robEV3 c7yXDL4NMT5JP8xbxd4HQu2YpW5CFKKEnMNeqtDyB3IbMcadp2XA4jdMCR08Jqm17ZFw lOdqnERZ5nMdC71nObJqQ6l7ugfzqVmUS0nQnQ2olNaHMzntsWNOwX72sN+RsKV3r52a pcyg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=r33J9aMWrdxvj7yikEyIW3ieQ3ddYEOcqyiZA1P6kTw=; fh=dUFWsMMV5y6m5CXBeEnnQEpt+78hjZsjcWaO9e/PYf0=; b=T3QwSB0w3d0cbZ0wq6frThHX1KuGQyutUrSZ29DID+j8hROPRv21bteqJewqKU9JMF pU2FPDuAuUWTq6sxL8aWgjfOE12/q4gGEJUjjlESNd5xLhko4/xFjM32Ey3MbdydO0eT vNt9gNyQ1Ouvt3A1DNKBacSnp/6oPS0hgOPHR//iF7SGLWqENtC1AMU6eBVbJKZWUtF+ syYIErB8ECjbg3YMXVxv1UhCLu7wfypOf7S9s3xkYnWiWbvyuaoR3CaCCtBNbX33EI08 fW/T2hfHp3ET7h1xTeFvy+6xmqC4RJp2XjYL14nbc6Vvhv5hlPXx8adEVGU4gqdOASo0 CpaA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="R/QGJuhJ"; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-56004-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-56004-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com X-Forwarded-Encrypted: i=2; AJvYcCXKVACrQJ/0JlvMtCDCPedkLpq2Yz5utQqZJFMHhoA/0vVBtciw27MHoQ2bcoqb3IPz1XvbO4u4biZVqZ9tWwOuuHPL9g== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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bh=h5RpRwAivJEkMgOQGPSE31O4QbdHWmr5WM+YPfbxP60=; b=R/QGJuhJeH6vyZzDlQ586EVPCWAifHvtjB3ViCDvQdJvr+nE3UZGUEbg /wXJhUxDRc7esyM9g+VUimKnfkL7SCywKNshUe5/1NElsmWQQmWri3nkp ItR+N7NyRrCWz4rxR+9QZgWgJjEG/I/dJeX51OLSUk5ihR/SUI3M7MNVh 5A/ex+jxK3XMKOyFs/0G2uGb/zJkn2MoZloonIkXAyjTR78zz0xrtoaYz NK7ABAdpHNJnK/6Fyv/ElElJ2o1gUr3DEi1nUtEokBvhmUaU5YJUhqgFy Hg+3RQtmJv+550p8TnFkrkKZ71hEI6CfvGjuy7WoD+J5lKVYYZ5MWNbIk g==; X-IronPort-AV: E=McAfee;i="6600,9927,10976"; a="436054113" X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="436054113" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2024 22:10:16 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.05,250,1701158400"; d="scan'208";a="5849952" Received: from inlubt0316.iind.intel.com ([10.191.20.213]) by fmviesa004.fm.intel.com with ESMTP; 06 Feb 2024 22:10:10 -0800 From: lakshmi.sowjanya.d@intel.com To: tglx@linutronix.de, jstultz@google.com, giometti@enneenne.com, corbet@lwn.net, linux-kernel@vger.kernel.org Cc: x86@kernel.org, netdev@vger.kernel.org, linux-doc@vger.kernel.org, intel-wired-lan@lists.osuosl.org, andriy.shevchenko@linux.intel.com, eddie.dong@intel.com, christopher.s.hall@intel.com, jesse.brandeburg@intel.com, davem@davemloft.net, alexandre.torgue@foss.st.com, joabreu@synopsys.com, mcoquelin.stm32@gmail.com, perex@perex.cz, linux-sound@vger.kernel.org, anthony.l.nguyen@intel.com, peter.hilber@opensynergy.com, pandith.n@intel.com, mallikarjunappa.sangannavar@intel.com, subramanian.mohan@intel.com, thejesh.reddy.t.r@intel.com, lakshmi.sowjanya.d@intel.com Subject: [PATCH v4 11/11] ABI: pps: Add ABI documentation for Intel TIO Date: Wed, 7 Feb 2024 11:38:54 +0530 Message-Id: <20240207060854.6524-12-lakshmi.sowjanya.d@intel.com> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> References: <20240207060854.6524-1-lakshmi.sowjanya.d@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790219660866904362 X-GMAIL-MSGID: 1790219660866904362 From: Lakshmi Sowjanya D Document sysfs interface for Intel Timed I/O PPS driver. Signed-off-by: Lakshmi Sowjanya D --- Documentation/ABI/testing/sysfs-platform-pps-tio | 7 +++++++ 1 file changed, 7 insertions(+) create mode 100644 Documentation/ABI/testing/sysfs-platform-pps-tio diff --git a/Documentation/ABI/testing/sysfs-platform-pps-tio b/Documentation/ABI/testing/sysfs-platform-pps-tio new file mode 100644 index 000000000000..b9b8c97a7840 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-platform-pps-tio @@ -0,0 +1,7 @@ +What: /sys/devices/platform/INTCxxxx/enable +Date: March 2024 +KernelVersion 6.9 +Contact: Lakshmi Sowjanya D +Description: + (RW) Enable or disable PPS TIO generator output, read to + see the status of hardware (Enabled/Disabled).