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Tue, 06 Feb 2024 06:57:35 -0800 (PST) From: Markus Schneider-Pargmann To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vignesh Raghavendra , Tero Kristo , "Rafael J . Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 1/3] dt-bindings: cpufreq: Add nvmem-cells for chip information Date: Tue, 6 Feb 2024 15:57:19 +0100 Message-ID: <20240206145721.2418893-2-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790162135783506636 X-GMAIL-MSGID: 1790162135783506636 Add nvmem-cells to describe chip information like chipvariant and chipspeed. If nvmem-cells are used, the syscon property is not necessary anymore. Signed-off-by: Markus Schneider-Pargmann Acked-by: Andrew Davis Reviewed-by: Krzysztof Kozlowski Reviewed-by: Dhruva Gole Nacked-by: Krzysztof Kozlowski --- .../bindings/opp/operating-points-v2-ti-cpu.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml index 02d1d2c17129..b1881a0834fe 100644 --- a/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/operating-points-v2-ti-cpu.yaml @@ -34,6 +34,14 @@ properties: points to syscon node representing the control module register space of the SoC. + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-array + + nvmem-cell-names: + items: + - const: chipvariant + - const: chipspeed + opp-shared: true patternProperties: @@ -55,7 +63,13 @@ patternProperties: required: - compatible - - syscon + +oneOf: + - required: + - syscon + - required: + - nvmem-cells + - nvmem-cell-names additionalProperties: false From patchwork Tue Feb 6 14:57:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 197478 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp1595489dyb; Tue, 6 Feb 2024 07:00:21 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMrU3j/+cjG9nIYgAOWvg2bnCaWjb4JbAQ24Ij5sxujPQXYf/xa2jMjhzavpHUqAJQiNWz X-Received: by 2002:a17:906:f59f:b0:a35:50c7:8b41 with SMTP id cm31-20020a170906f59f00b00a3550c78b41mr2111656ejd.72.1707231620912; Tue, 06 Feb 2024 07:00:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707231620; cv=pass; d=google.com; s=arc-20160816; b=ItyePfbebvVzfdsao5sYUK1otuaxS99jBt+SbZ3E64u56auL2jDU4aA/AdZlmK9J36 UfP9CqsvyRMaKlMBQhsfWiTloLPzxMG3jx2W6C+QIzc8AHzAgHM4QdX0p/ZnxhNIMB9H v7L00M6TuQGGUHzrPjM8/gmJP3mdK7OG23/L/Yxu4EwFnaKJ1LbPq820+Cgew4ta7p9t jPEMkCVdoLoA09Ov7ZlmN6EVu7TqZUhrO4eUAZ1p7izpHy8JkPGnqXgJHkuk1GWHnYZI 8f5C+wvC7B+Efos862dVV9wdSr8WOoi6iJrDOZYmmsQIwFBAFN6qFXrpher+7jYoZoK8 +efg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=XdH/MMRBTUfqayVAnmhejns1JtGutpHRzA8LTWcgILQ=; fh=S2+HNHohv7Y5cBcTW4ukyC+Kf2k0rl5EfNjEGOunuIk=; b=woHnPiQZRsklW5Ok/6MoaZccuQBprQciM8PlLz4Baubn9zMtTp0nrA4AabK0ue0qZi I0hMA9v6FegIVFJoeuiSkKKIzlceKUFQ7FGxK55nH/tR/1NOz2W13RGxezt6/OXWZXq6 GNiS42toXB4Xve5PMl3K4VsoS/4SVIWnN66R/+7tPVuWh9RV/149D0XUOgC1KE22vUny ClZ33PHG5aVBTdL5ilh9SUDRM+fDrq0IPGCIJ48SrG56tuQkilq5g8UTBu0OPll3uoSk pZRs1uvACNsWlKEtqFS2Hv1hacOTBaOX/UhIkNw0n1j4uPcDRgqbuh4G5j+dj0ILf7Bs T/Xg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=RBHswoEn; arc=pass (i=1 spf=pass spfdomain=baylibre.com dkim=pass dkdomain=baylibre-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-55160-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55160-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=1; AJvYcCUTFuL8FtreQpdxFPI/1FHyRSzsnmeKZbv2XQlaaxS1WY0lpWBQ5c6r2fl1BDBc5wKGpfho+ZF9lZYloBxzAWylKsz0hg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Tue, 06 Feb 2024 06:57:36 -0800 (PST) From: Markus Schneider-Pargmann To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vignesh Raghavendra , Tero Kristo , "Rafael J . Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 2/3] cpufreq: ti-cpufreq: Support nvmem for chip version Date: Tue, 6 Feb 2024 15:57:20 +0100 Message-ID: <20240206145721.2418893-3-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790162104213758016 X-GMAIL-MSGID: 1790162104213758016 Support using nvmem-cells 'chipvariant' and 'chipspeed' instead of syscon. This makes it more flexible and moves more configuration into the devicetree. If nvmem-cells are present, probing will fail if the configuration of these cells is broken. If nvmem-cells is not present syscon will be used. Signed-off-by: Markus Schneider-Pargmann Reviewed-by: Dhruva Gole --- drivers/cpufreq/ti-cpufreq.c | 105 ++++++++++++++++++++++------------- 1 file changed, 66 insertions(+), 39 deletions(-) diff --git a/drivers/cpufreq/ti-cpufreq.c b/drivers/cpufreq/ti-cpufreq.c index 46c41e2ca727..3ee72b1309f0 100644 --- a/drivers/cpufreq/ti-cpufreq.c +++ b/drivers/cpufreq/ti-cpufreq.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -65,6 +66,7 @@ struct ti_cpufreq_soc_data { struct ti_cpufreq_data { struct device *cpu_dev; + struct device *dev; struct device_node *opp_node; struct regmap *syscon; const struct ti_cpufreq_soc_data *soc_data; @@ -244,31 +246,40 @@ static struct ti_cpufreq_soc_data am625_soc_data = { static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, u32 *efuse_value) { + struct device_node *np = opp_data->opp_node; struct device *dev = opp_data->cpu_dev; u32 efuse; int ret; - ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, - &efuse); - if (ret == -EIO) { - /* not a syscon register! */ - void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->efuse_offset, 4); - - if (!regs) - return -ENOMEM; - efuse = readl(regs); - iounmap(regs); + ret = nvmem_cell_read_u32(opp_data->dev, "chipspeed", &efuse); + if (ret && (ret != -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipspeed': %pe", + ERR_PTR(ret)); + + if (ret) { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->efuse_offset, + &efuse); + if (ret == -EIO) { + /* not a syscon register! */ + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->efuse_offset, 4); + + if (!regs) + return -ENOMEM; + efuse = readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the efuse value from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the efuse value from syscon: %d\n", - ret); - return ret; - } - efuse = (efuse & opp_data->soc_data->efuse_mask); - efuse >>= opp_data->soc_data->efuse_shift; + efuse = (efuse & opp_data->soc_data->efuse_mask); + efuse >>= opp_data->soc_data->efuse_shift; + } *efuse_value = opp_data->soc_data->efuse_xlate(opp_data, efuse); @@ -285,30 +296,41 @@ static int ti_cpufreq_get_efuse(struct ti_cpufreq_data *opp_data, static int ti_cpufreq_get_rev(struct ti_cpufreq_data *opp_data, u32 *revision_value) { + struct device_node *np = opp_data->opp_node; struct device *dev = opp_data->cpu_dev; u32 revision; int ret; - ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, - &revision); - if (ret == -EIO) { - /* not a syscon register! */ - void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + - opp_data->soc_data->rev_offset, 4); - - if (!regs) - return -ENOMEM; - revision = readl(regs); - iounmap(regs); + ret = nvmem_cell_read_u32(opp_data->dev, "chipvariant", &revision); + if (ret && (ret != -ENOENT || !opp_data->syscon)) + return dev_err_probe(dev, ret, + "Failed to read nvmem cell 'chipvariant': %pe", + ERR_PTR(ret)); + + if (ret) { + ret = regmap_read(opp_data->syscon, opp_data->soc_data->rev_offset, + &revision); + if (ret == -EIO) { + /* not a syscon register! */ + void __iomem *regs = ioremap(OMAP3_SYSCON_BASE + + opp_data->soc_data->rev_offset, 4); + + if (!regs) + return -ENOMEM; + revision = readl(regs); + iounmap(regs); + } + else if (ret) { + dev_err(dev, + "Failed to read the revision number from syscon: %d\n", + ret); + return ret; } - else if (ret) { - dev_err(dev, - "Failed to read the revision number from syscon: %d\n", - ret); - return ret; + + revision = (revision >> REVISION_SHIFT) & REVISION_MASK; } - *revision_value = BIT((revision >> REVISION_SHIFT) & REVISION_MASK); + *revision_value = BIT(revision); return 0; } @@ -392,9 +414,14 @@ static int ti_cpufreq_probe(struct platform_device *pdev) goto register_cpufreq_dt; } - ret = ti_cpufreq_setup_syscon_register(opp_data); - if (ret) - goto fail_put_node; + opp_data->dev = &pdev->dev; + opp_data->dev->of_node = opp_data->opp_node; + + if (!of_property_read_bool(opp_data->opp_node, "nvmem-cells")) { + ret = ti_cpufreq_setup_syscon_register(opp_data); + if (ret) + goto fail_put_node; + } /* * OPPs determine whether or not they are supported based on From patchwork Tue Feb 6 14:57:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Markus Schneider-Pargmann X-Patchwork-Id: 197480 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp1596505dyb; Tue, 6 Feb 2024 07:01:22 -0800 (PST) X-Google-Smtp-Source: AGHT+IEPiC7Np71JUJJgxoOjykrmrK3MekW03b4Ruzx7B/TOVmZ/dSXjPCbLd8uVqZ3teA0FO0K0 X-Received: by 2002:a05:6a21:670d:b0:19e:9c98:b63d with SMTP id wh13-20020a056a21670d00b0019e9c98b63dmr698735pzb.41.1707231682656; Tue, 06 Feb 2024 07:01:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707231682; cv=pass; d=google.com; s=arc-20160816; b=N6qBkCs4EivvRGd5WywFEZ6czSQPorE3S4HZGvZxq0tPEao1rXOkTHC3KzuQg5fBKq soM6SI/vuVWZ+sUDxbbpTV1RLmgMOf3l45u4qqbpF6jFhqBzyy/XUa02kGfKhtZqAB2r rqr1E3BVorfvIvbubMprA8rSxL0BvVTpQNdMvRrCNaG9VXgALgC7RqKs8HXi7lGZo+ZT 9UErDIUcLPlkhCEQkJH9B3HOjgYAr0EydUInzwPBw+87ZF/i1piTC6I7flJFF8T+ia7j /9xi4E13EvZCsxRPC7jn/J+AfmkCiFqnn9hbYV+0+n8f8LVKAOiCjxvXUpSXfqTI5g0h /bag== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gASO78qnd+QKC6Tryaqp/xMfAhHvhZxuVEnU1FHt3IQ=; fh=HVUa4aM71crQQn38QJbIeGl6fAmgjpkScHyWWW8JIjI=; b=Q4h8ZRyPgnzKJ8dt/DIEpIPdmBAC5kOHousWqa2vU+RhF3s5RovBbCboQb3hCk8NSP EeBuMiodPyf9p8yNEXZQGK9upSy1ernQvDt7mR3IEL3Esenl0l2iTGa9aHqOfg08LiFq FmRoKiAKqrltEa18bkr+KTHqLeJSqBxeW0NHNTyuuDyUJD0zKWRRsWeeFVeCjvb5SRIG Z7Yrrk4hUVLG77FlMNPR6U+cysF2ioZ0bEotg5AhVYaH+oZAzcEOkI2N5tNDYP1wkKRD Sjyy04IMvOVa1Ae0JjkM+0Ul/LhqcCBoBl9PIpjFCAhEAAgpnf7qSHgvdNgOXMdBBJ9J YaHA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@baylibre-com.20230601.gappssmtp.com header.s=20230601 header.b=jmNeG6Ka; arc=pass (i=1 spf=pass spfdomain=baylibre.com dkim=pass dkdomain=baylibre-com.20230601.gappssmtp.com); spf=pass (google.com: domain of linux-kernel+bounces-55161-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-55161-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=1; AJvYcCWlOgT+esRudfqvAM2wyN6HHphUI0qOokGz9rLp0IOcQS/87iqesvm375p5/UFtBUmX4ABbPM1LyP3XWFJ1hanxXKTSiQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Tue, 06 Feb 2024 06:57:37 -0800 (PST) From: Markus Schneider-Pargmann To: Viresh Kumar , Nishanth Menon , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Vignesh Raghavendra , Tero Kristo , "Rafael J . Wysocki" Cc: Andrew Davis , Dhruva Gole , linux-pm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Markus Schneider-Pargmann Subject: [PATCH 3/3] arm64: dts: ti: k3-am625: Use nvmem-cells for opp Date: Tue, 6 Feb 2024 15:57:21 +0100 Message-ID: <20240206145721.2418893-4-msp@baylibre.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206145721.2418893-1-msp@baylibre.com> References: <20240206145721.2418893-1-msp@baylibre.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790162169194239890 X-GMAIL-MSGID: 1790162169194239890 Use nvmem cells referring to chip variant and speed grade for the operating points. Signed-off-by: Markus Schneider-Pargmann --- arch/arm64/boot/dts/ti/k3-am625.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625.dtsi b/arch/arm64/boot/dts/ti/k3-am625.dtsi index 4193c2b3eed6..d60e1be9eb89 100644 --- a/arch/arm64/boot/dts/ti/k3-am625.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am625.dtsi @@ -105,6 +105,8 @@ a53_opp_table: opp-table { compatible = "operating-points-v2-ti-cpu"; opp-shared; syscon = <&wkup_conf>; + nvmem-cells = <&chip_variant>, <&chip_speed>; + nvmem-cell-names = "chipvariant", "chipspeed"; opp-200000000 { opp-hz = /bits/ 64 <200000000>;