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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=uTXrWNubyLzCiIBjGuyeLuaLctOfWgzRYqR/gLqFmdyFPgJ8ldFddvCijIJamxOj1 wUq/gY1IEpZd1luuilgZ0H9HTjG5U+B6NmO5iKp9jyw2QskNV0KyZZidUklVG8mNvm QTyJwIvJumibZNQlsUbdWCVfnn7+wwZg7F7zU59hlTYycy1q62/X7Km6gySBvgn/uZ sLoUjvYLpYu2eKm16CJhbp3C1ZQSpywxap+kn58vVXXKP9Kt3WEbQ1taWXdMq38G9k 039OFf4YkxBqshTegzFxcNZyrM35vK64L2eaG6H6hnJG+VkWbO6e3jlBwPYitzYsam hTsYEOYCIMcYg== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id CE8583782072; Tue, 6 Feb 2024 12:07:52 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 1/9] drm/mediatek: dsi: Use GENMASK() for register mask definitions Date: Tue, 6 Feb 2024 13:07:40 +0100 Message-ID: <20240206120748.136610-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790151836176595965 X-GMAIL-MSGID: 1790151836176595965 Change magic numerical masks with usage of the GENMASK() macro to improve readability. While at it, also fix the DSI_PS_SEL mask to include all bits instead of just a subset of them. This commit brings no functional changes. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 45 +++++++++++++++--------------- 1 file changed, 23 insertions(+), 22 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index a2fdfc8ddb15..3b7392c03b4d 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -58,18 +58,18 @@ #define DSI_TXRX_CTRL 0x18 #define VC_NUM BIT(1) -#define LANE_NUM (0xf << 2) +#define LANE_NUM GENMASK(5, 2) #define DIS_EOT BIT(6) #define NULL_EN BIT(7) #define TE_FREERUN BIT(8) #define EXT_TE_EN BIT(9) #define EXT_TE_EDGE BIT(10) -#define MAX_RTN_SIZE (0xf << 12) +#define MAX_RTN_SIZE GENMASK(15, 12) #define HSTX_CKLP_EN BIT(16) #define DSI_PSCTRL 0x1c -#define DSI_PS_WC 0x3fff -#define DSI_PS_SEL (3 << 16) +#define DSI_PS_WC GENMASK(14, 0) +#define DSI_PS_SEL GENMASK(19, 16) #define PACKED_PS_16BIT_RGB565 (0 << 16) #define LOOSELY_PS_18BIT_RGB666 (1 << 16) #define PACKED_PS_18BIT_RGB666 (2 << 16) @@ -109,26 +109,26 @@ #define LD0_WAKEUP_EN BIT(2) #define DSI_PHY_TIMECON0 0x110 -#define LPX (0xff << 0) -#define HS_PREP (0xff << 8) -#define HS_ZERO (0xff << 16) -#define HS_TRAIL (0xff << 24) +#define LPX GENMASK(7, 0) +#define HS_PREP GENMASK(15, 8) +#define HS_ZERO GENMASK(23, 16) +#define HS_TRAIL GENMASK(31, 24) #define DSI_PHY_TIMECON1 0x114 -#define TA_GO (0xff << 0) -#define TA_SURE (0xff << 8) -#define TA_GET (0xff << 16) -#define DA_HS_EXIT (0xff << 24) +#define TA_GO GENMASK(7, 0) +#define TA_SURE GENMASK(15, 8) +#define TA_GET GENMASK(23, 16) +#define DA_HS_EXIT GENMASK(31, 24) #define DSI_PHY_TIMECON2 0x118 -#define CONT_DET (0xff << 0) -#define CLK_ZERO (0xff << 16) -#define CLK_TRAIL (0xff << 24) +#define CONT_DET GENMASK(7, 0) +#define CLK_ZERO GENMASK(23, 16) +#define CLK_TRAIL GENMASK(31, 24) #define DSI_PHY_TIMECON3 0x11c -#define CLK_HS_PREP (0xff << 0) -#define CLK_HS_POST (0xff << 8) -#define CLK_HS_EXIT (0xff << 16) +#define CLK_HS_PREP GENMASK(7, 0) +#define CLK_HS_POST GENMASK(15, 8) +#define CLK_HS_EXIT GENMASK(23, 16) #define DSI_VM_CMD_CON 0x130 #define VM_CMD_EN BIT(0) @@ -138,13 +138,14 @@ #define FORCE_COMMIT BIT(0) #define BYPASS_SHADOW BIT(1) -#define CONFIG (0xff << 0) +/* CMDQ related bits */ +#define CONFIG GENMASK(7, 0) #define SHORT_PACKET 0 #define LONG_PACKET 2 #define BTA BIT(2) -#define DATA_ID (0xff << 8) -#define DATA_0 (0xff << 16) -#define DATA_1 (0xff << 24) +#define DATA_ID GENMASK(15, 8) +#define DATA_0 GENMASK(23, 16) +#define DATA_1 GENMASK(31, 24) #define NS_TO_CYCLE(n, c) ((n) / (c) + (((n) % (c)) ? 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IZAJ7ATombfarBAlVMMwEeKRK5mDRLVmnMnRXdzCMZW+IG/2FkSFRvE1aFfgKNyOO IjKAFp0g4jnfEiMAOmgBx7gItpwS0Hegq1lJzYvkRL68cwA5d8GZ8EgZrzjWJFKiYe Rwpxf9Nv3BDbNN9XlvJYvBxqL2hUCr9vK/lZqUiU6uJbpDyze3JgxzIaaafprSG3N2 IMdrnVqMnTcVo/NVmj7UcewDwjqb5ALajTLKJHb21dC68cBOTjy80aJKWoOsl2sCfb NmX+SpMOSdHXbHOOSNEbWaXly7Agt2c7mKMeDFHc/uyGpBmQx0kSWE/TZko5xMzrUM Msx0mAAqZGg0g== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id C74943782077; Tue, 6 Feb 2024 12:07:53 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 2/9] drm/mediatek: dsi: Fix DSI RGB666 formats and definitions Date: Tue, 6 Feb 2024 13:07:41 +0100 Message-ID: <20240206120748.136610-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790151477928953236 X-GMAIL-MSGID: 1790151477928953236 The register bits definitions for RGB666 formats are wrong in multiple ways: first, in the DSI_PS_SEL bits region, the Packed 18-bits RGB666 format is selected with bit 1, while the Loosely Packed one is bit 2, and second - the definition name "LOOSELY_PS_18BIT_RGB666" is wrong because the loosely packed format is 24 bits instead! Either way, functions mtk_dsi_ps_control_vact() and mtk_dsi_ps_control() do not even agree on the DSI_PS_SEL bit to set in DSI_PSCTRL: one sets loosely packed (24) on RGB666, the other sets packed (18), and the other way around for RGB666_PACKED. Fixing this entire stack of issues is done in one go: - Use the correct bit for the Loosely Packed RGB666 definition - Rename LOOSELY_PS_18BIT_RGB666 to LOOSELY_PS_24BIT_RGB666 - Change ps_bpp_mode in mtk_dsi_ps_control_vact() to set: - Loosely Packed, 24-bits for MIPI_DSI_FMT_RGB666 - Packed, 18-bits for MIPI_DSI_FMT_RGB666_PACKED Fixes: 2e54c14e310f ("drm/mediatek: Add DSI sub driver") Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 3b7392c03b4d..9fbf293db1c8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -71,8 +71,8 @@ #define DSI_PS_WC GENMASK(14, 0) #define DSI_PS_SEL GENMASK(19, 16) #define PACKED_PS_16BIT_RGB565 (0 << 16) -#define LOOSELY_PS_18BIT_RGB666 (1 << 16) -#define PACKED_PS_18BIT_RGB666 (2 << 16) +#define PACKED_PS_18BIT_RGB666 (1 << 16) +#define LOOSELY_PS_24BIT_RGB666 (2 << 16) #define PACKED_PS_24BIT_RGB888 (3 << 16) #define DSI_VSA_NL 0x20 @@ -370,10 +370,10 @@ static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) ps_bpp_mode |= PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; + ps_bpp_mode |= LOOSELY_PS_24BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |= LOOSELY_PS_18BIT_RGB666; + ps_bpp_mode |= PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: ps_bpp_mode |= PACKED_PS_16BIT_RGB565; @@ -427,7 +427,7 @@ static void mtk_dsi_ps_control(struct mtk_dsi *dsi) dsi_tmp_buf_bpp = 3; break; case MIPI_DSI_FMT_RGB666: - tmp_reg = LOOSELY_PS_18BIT_RGB666; + tmp_reg = LOOSELY_PS_24BIT_RGB666; dsi_tmp_buf_bpp = 3; break; case MIPI_DSI_FMT_RGB666_PACKED: From patchwork Tue Feb 6 12:07:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 197376 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp1492524dyb; Tue, 6 Feb 2024 04:11:37 -0800 (PST) X-Google-Smtp-Source: AGHT+IFRuKL4M9/LA+Oo3EZ3IdDM8V4wANVTAylANtfe7fVjXBvPaV88kxQ0nrC/DX1G1n8/kY3A X-Received: by 2002:a05:622a:1450:b0:42a:b843:e0b2 with SMTP id v16-20020a05622a145000b0042ab843e0b2mr3047680qtx.26.1707221496889; Tue, 06 Feb 2024 04:11:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707221496; cv=pass; d=google.com; s=arc-20160816; b=Xm2uu5CvVx4eTkd1Xb4vqNEexhgTRip9VA75EzNo4YEx+9PgoNrJ2ar9WpaQnZcI9j nLp4BDvAQgcrtNiXsCqqaoPr/P4iuzL4FrhhCsFp6RHcl9eq41+VGDmx1bfo4sWqImBu C3o14LHFHG3bwwfy56txuj9jNygWod5774O8F8Tbyu/VHzdoQWA3nnN31CW1RKCyjah8 H2de4rxtzIrA63k3wh+GCkV6Ry5Xll1aJAg3HF4JqtRqLhbCCYILQAvlpdMI1bABBvg0 GBY7SKmEJVnxIndNleqPsHGOiUfvxul+Z5b8jkZSdhmNx/paWdeHaBcmI2yHnO1Rvhid tuLA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=H7xEu5ciwVXXqveNVWs6cWBNvpUYtmwG9ZoWrRrpWCU=; fh=ca7Xd7Ls+JQH0cuFtHe86714P7ww76mIBSaN/DJusf0=; b=dqwZ2i1RHbW6RFWj8VciLZ/YVJwBsfp5rEgx34QU8HjVTjV62UXwmM72Iz0r2y+HkD b0FOwvCafEpOSEGleWyXNZ3XHrX0RZMHReZA0tCsVsoJdeqivrvPBCvbMwDR16hScuRn DX56pbdPLJygLDqqfIoRlnx7exlOBQ6Ut7wvAfX2WrTBQmKtuKQMIpQsKmIDiTF1X8Tu 0zpsfFjIqf7a8f/Dcqy/SSqk7UhhDr4BikzPgqUwi8DpyTdRDI0PBsrOZzHgV+d30KkA 8ffbEUlCbMZJmT7cmVITuZyYhUviH4+XkkBJJJreZEXAAQQ6JJS4JEatUenNTNqKFe10 jIBA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=Hhyf9fsE; arc=pass (i=1 spf=pass spfdomain=collabora.com dkim=pass dkdomain=collabora.com dmarc=pass fromdomain=collabora.com); spf=pass (google.com: domain of linux-kernel+bounces-54861-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-54861-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=QUARANTINE dis=NONE) header.from=collabora.com X-Forwarded-Encrypted: i=1; AJvYcCVDYttMZ6ibfeOcc9EggvEuIlXgIN1+T06CQSs9eqsnRR869PEvm3BXY8P4DqW4R0WNSeFiulZF53vquwXTFWH1sbVySQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Hhyf9fsEBBp6qXAm1190EYZlJ8bC2/mbTeBprdiNhxBY1KP9bugFTESyurPOWDvEQ aYkz2hd1dKXCp6EnpLERDQsPDVVRnYnHMOnZ8ViL7VkSgFEsqM3Ta6dFcKVVC5jT/L TMy5WUDGtmp5HeNLCSAPMyZY0pnvZ/GVISvWL7PLIQ8WhhrGSjZE2NiyGHnd56yLnu XBPQFGiAfuwFT5V3MaSuvpb2UKjjiwFIKjrVn/w+layT0BKXxamlL/rL29VKIIc2J8 Mtf5s2NvvPpnD++/OkGe5+9YwOguQJzBagEw6Z4XQnuzgF2CI1/Z2vlhMu3o5I2PH/ whJDkTSmlgKlQ== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id CAA8F3782076; Tue, 6 Feb 2024 12:07:54 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 3/9] drm/mediatek: dsi: Cleanup functions mtk_dsi_ps_control{_vact}() Date: Tue, 6 Feb 2024 13:07:42 +0100 Message-ID: <20240206120748.136610-4-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790151488343288177 X-GMAIL-MSGID: 1790151488343288177 Function mtk_dsi_ps_control() is a subset of mtk_dsi_ps_control_vact(): merge the two in one mtk_dsi_ps_control() function by adding one function parameter `config_vact` which, when true, writes the VACT related registers. Reviewed-by: Fei Shao Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 76 +++++++++--------------------- 1 file changed, 23 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 9fbf293db1c8..b025886be680 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -351,40 +351,6 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) mtk_dsi_mask(dsi, DSI_VM_CMD_CON, TS_VFP_EN, TS_VFP_EN); } -static void mtk_dsi_ps_control_vact(struct mtk_dsi *dsi) -{ - struct videomode *vm = &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; - - if (dsi->format == MIPI_DSI_FMT_RGB565) - dsi_buf_bpp = 2; - else - dsi_buf_bpp = 3; - - ps_wc = vm->hactive * dsi_buf_bpp; - ps_bpp_mode = ps_wc; - - switch (dsi->format) { - case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |= PACKED_PS_24BIT_RGB888; - break; - case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |= LOOSELY_PS_24BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; - break; - case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |= PACKED_PS_16BIT_RGB565; - break; - } - - writel(vm->vactive, dsi->regs + DSI_VACT_NL); - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); - writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); -} - static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { u32 tmp_reg; @@ -416,36 +382,40 @@ static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); } -static void mtk_dsi_ps_control(struct mtk_dsi *dsi) +static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - u32 dsi_tmp_buf_bpp; - u32 tmp_reg; + struct videomode *vm = &dsi->vm; + u32 dsi_buf_bpp, ps_wc; + u32 ps_bpp_mode; + + if (dsi->format == MIPI_DSI_FMT_RGB565) + dsi_buf_bpp = 2; + else + dsi_buf_bpp = 3; + + ps_wc = vm->hactive * dsi_buf_bpp; + ps_bpp_mode = ps_wc; switch (dsi->format) { case MIPI_DSI_FMT_RGB888: - tmp_reg = PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_24BIT_RGB888; break; case MIPI_DSI_FMT_RGB666: - tmp_reg = LOOSELY_PS_24BIT_RGB666; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= LOOSELY_PS_24BIT_RGB666; break; case MIPI_DSI_FMT_RGB666_PACKED: - tmp_reg = PACKED_PS_18BIT_RGB666; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_18BIT_RGB666; break; case MIPI_DSI_FMT_RGB565: - tmp_reg = PACKED_PS_16BIT_RGB565; - dsi_tmp_buf_bpp = 2; - break; - default: - tmp_reg = PACKED_PS_24BIT_RGB888; - dsi_tmp_buf_bpp = 3; + ps_bpp_mode |= PACKED_PS_16BIT_RGB565; break; } - tmp_reg += dsi->vm.hactive * dsi_tmp_buf_bpp & DSI_PS_WC; - writel(tmp_reg, dsi->regs + DSI_PSCTRL); + if (config_vact) { + writel(vm->vactive, dsi->regs + DSI_VACT_NL); + writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); + } + writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); } static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -521,7 +491,7 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) writel(horizontal_backporch_byte, dsi->regs + DSI_HBP_WC); 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h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g3CM26vU6vDrtkIr+laszsm2o4YIs8uCDYQRiS+QxdI4MgcJDHct4qjctYT3+3wMO G6PwM7/EdH1pJbLJFoAPqQr6JdU6qgaqt7oi1J+CItj5Aw3V6KeY2nApqK0EmWku7B BWHDoHzhvwl3jQt/DFB1NWw5Ud5VZR9DTQaBMap2JphRQiW1paF3lAHE+nGGa+P1am R4fQTrzPxPDrZgCXBjjPQDlmouLqr5BWl2UKDD9ngvuJrkScfS2VRwb+4akLo85J3p WCdl6Dq1DOD6yWTtKcpFNXJAf0hhHah2H/Rk1XVFttU7opbw4hD2cdVEtQTTdehtgp jV+kUT4+BScqw== Received: from IcarusMOD.eternityproject.eu (cola.collaboradmins.com [195.201.22.229]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madrid.collaboradmins.com (Postfix) with ESMTPSA id D24D9378207C; Tue, 6 Feb 2024 12:07:55 +0000 (UTC) From: AngeloGioacchino Del Regno To: chunkuang.hu@kernel.org Cc: fshao@chromium.org, p.zabel@pengutronix.de, airlied@gmail.com, daniel@ffwll.ch, matthias.bgg@gmail.com, angelogioacchino.delregno@collabora.com, dri-devel@lists.freedesktop.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@collabora.com Subject: [PATCH v4 4/9] drm/mediatek: dsi: Use bitfield macros where useful Date: Tue, 6 Feb 2024 13:07:43 +0100 Message-ID: <20240206120748.136610-5-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> References: <20240206120748.136610-1-angelogioacchino.delregno@collabora.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790151531050482864 X-GMAIL-MSGID: 1790151531050482864 Instead of open coding bitshifting for various register fields, use the bitfield macro FIELD_PREP(): this allows to enhance the human readability, decrease likeliness of mistakes (and register field overflowing) and also to simplify the code. The latter is especially seen in mtk_dsi_rxtx_control(), where it was possible to change a switch to a short for loop and to also remove the need to check for maximum DSI lanes == 4 thanks to the FIELD_PREP macro masking the value. While at it, also add the missing DA_HS_SYNC bitmask, used in mtk_dsi_phy_timconfig(). Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 97 ++++++++++++++++-------------- 1 file changed, 52 insertions(+), 45 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index b025886be680..26c221737387 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -3,6 +3,7 @@ * Copyright (c) 2015 MediaTek Inc. */ +#include #include #include #include @@ -70,16 +71,19 @@ #define DSI_PSCTRL 0x1c #define DSI_PS_WC GENMASK(14, 0) #define DSI_PS_SEL GENMASK(19, 16) -#define PACKED_PS_16BIT_RGB565 (0 << 16) -#define PACKED_PS_18BIT_RGB666 (1 << 16) -#define LOOSELY_PS_24BIT_RGB666 (2 << 16) -#define PACKED_PS_24BIT_RGB888 (3 << 16) +#define PACKED_PS_16BIT_RGB565 0 +#define PACKED_PS_18BIT_RGB666 1 +#define LOOSELY_PS_24BIT_RGB666 2 +#define PACKED_PS_24BIT_RGB888 3 #define DSI_VSA_NL 0x20 #define DSI_VBP_NL 0x24 #define DSI_VFP_NL 0x28 #define DSI_VACT_NL 0x2C +#define VACT_NL GENMASK(14, 0) #define DSI_SIZE_CON 0x38 +#define DSI_HEIGHT GENMASK(30, 16) +#define DSI_WIDTH GENMASK(14, 0) #define DSI_HSA_WC 0x50 #define DSI_HBP_WC 0x54 #define DSI_HFP_WC 0x58 @@ -122,6 +126,7 @@ #define DSI_PHY_TIMECON2 0x118 #define CONT_DET GENMASK(7, 0) +#define DA_HS_SYNC GENMASK(15, 8) #define CLK_ZERO GENMASK(23, 16) #define CLK_TRAIL GENMASK(31, 24) @@ -253,14 +258,23 @@ static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) timing->clk_hs_zero = timing->clk_hs_trail * 4; timing->clk_hs_exit = 2 * timing->clk_hs_trail; - timcon0 = timing->lpx | timing->da_hs_prepare << 8 | - timing->da_hs_zero << 16 | timing->da_hs_trail << 24; - timcon1 = timing->ta_go | timing->ta_sure << 8 | - timing->ta_get << 16 | timing->da_hs_exit << 24; - timcon2 = 1 << 8 | timing->clk_hs_zero << 16 | - timing->clk_hs_trail << 24; - timcon3 = timing->clk_hs_prepare | timing->clk_hs_post << 8 | - timing->clk_hs_exit << 16; + timcon0 = FIELD_PREP(LPX, timing->lpx) | + FIELD_PREP(HS_PREP, timing->da_hs_prepare) | + FIELD_PREP(HS_ZERO, timing->da_hs_zero) | + FIELD_PREP(HS_TRAIL, timing->da_hs_trail); + + timcon1 = FIELD_PREP(TA_GO, timing->ta_go) | + FIELD_PREP(TA_SURE, timing->ta_sure) | + FIELD_PREP(TA_GET, timing->ta_get) | + FIELD_PREP(DA_HS_EXIT, timing->da_hs_exit); + + timcon2 = FIELD_PREP(DA_HS_SYNC, 1) | + FIELD_PREP(CLK_ZERO, timing->clk_hs_zero) | + FIELD_PREP(CLK_TRAIL, timing->clk_hs_trail); + + timcon3 = FIELD_PREP(CLK_HS_PREP, timing->clk_hs_prepare) | + FIELD_PREP(CLK_HS_POST, timing->clk_hs_post) | + FIELD_PREP(CLK_HS_EXIT, timing->clk_hs_exit); writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); @@ -353,69 +367,61 @@ static void mtk_dsi_set_vm_cmd(struct mtk_dsi *dsi) static void mtk_dsi_rxtx_control(struct mtk_dsi *dsi) { - u32 tmp_reg; + u32 regval, tmp_reg = 0; + u8 i; - switch (dsi->lanes) { - case 1: - tmp_reg = 1 << 2; - break; - case 2: - tmp_reg = 3 << 2; - break; - case 3: - tmp_reg = 7 << 2; - break; - case 4: - tmp_reg = 0xf << 2; - break; - default: - tmp_reg = 0xf << 2; - break; - } + /* Number of DSI lanes (max 4 lanes), each bit enables one DSI lane. */ + for (i = 0; i < dsi->lanes; i++) + tmp_reg |= BIT(i); + + regval = FIELD_PREP(LANE_NUM, tmp_reg); if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) - tmp_reg |= HSTX_CKLP_EN; + regval |= HSTX_CKLP_EN; if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) - tmp_reg |= DIS_EOT; + regval |= DIS_EOT; - writel(tmp_reg, dsi->regs + DSI_TXRX_CTRL); + writel(regval, dsi->regs + DSI_TXRX_CTRL); } static void mtk_dsi_ps_control(struct mtk_dsi *dsi, bool config_vact) { - struct videomode *vm = &dsi->vm; - u32 dsi_buf_bpp, ps_wc; - u32 ps_bpp_mode; + u32 dsi_buf_bpp, ps_val, ps_wc, vact_nl; if (dsi->format == MIPI_DSI_FMT_RGB565) dsi_buf_bpp = 2; else dsi_buf_bpp = 3; - ps_wc = vm->hactive * dsi_buf_bpp; - ps_bpp_mode = ps_wc; + /* Word count */ + ps_wc = FIELD_PREP(DSI_PS_WC, dsi->vm.hactive * dsi_buf_bpp); + ps_val = ps_wc; + /* Pixel Stream type */ switch (dsi->format) { + default: + fallthrough; case MIPI_DSI_FMT_RGB888: - ps_bpp_mode |= PACKED_PS_24BIT_RGB888; + ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_24BIT_RGB888); break; case MIPI_DSI_FMT_RGB666: - ps_bpp_mode |= LOOSELY_PS_24BIT_RGB666; + ps_val |= FIELD_PREP(DSI_PS_SEL, LOOSELY_PS_24BIT_RGB666); break; case MIPI_DSI_FMT_RGB666_PACKED: - ps_bpp_mode |= PACKED_PS_18BIT_RGB666; + ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_18BIT_RGB666); break; case MIPI_DSI_FMT_RGB565: - ps_bpp_mode |= PACKED_PS_16BIT_RGB565; + ps_val |= FIELD_PREP(DSI_PS_SEL, PACKED_PS_16BIT_RGB565); break; } if (config_vact) { - writel(vm->vactive, dsi->regs + DSI_VACT_NL); + vact_nl = FIELD_PREP(VACT_NL, dsi->vm.vactive); + writel(vact_nl, dsi->regs + DSI_VACT_NL); writel(ps_wc, dsi->regs + DSI_HSTX_CKL_WC); } - writel(ps_bpp_mode, dsi->regs + DSI_PSCTRL); + writel(ps_val, dsi->regs + DSI_PSCTRL); } static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) @@ -442,7 +448,8 @@ static void mtk_dsi_config_vdo_timing(struct mtk_dsi *dsi) writel(vm->vactive, dsi->regs + DSI_VACT_NL); if (dsi->driver_data->has_size_ctl) - writel(vm->vactive << 16 | vm->hactive, + writel(FIELD_PREP(DSI_HEIGHT, vm->vactive) | + FIELD_PREP(DSI_WIDTH, vm->hactive), dsi->regs + DSI_SIZE_CON); horizontal_sync_active_byte = (vm->hsync_len * dsi_tmp_buf_bpp - 10); From patchwork Tue Feb 6 12:07:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 197377 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp1492758dyb; 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Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Alexandre Mergnat --- drivers/gpu/drm/mediatek/mtk_dsi.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/mediatek/mtk_dsi.c b/drivers/gpu/drm/mediatek/mtk_dsi.c index 26c221737387..5e383ca00ba8 100644 --- a/drivers/gpu/drm/mediatek/mtk_dsi.c +++ b/drivers/gpu/drm/mediatek/mtk_dsi.c @@ -13,6 +13,7 @@ #include #include #include +#include #include