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Mon, 05 Feb 2024 12:08:15 -0800 (PST) From: sabiya.d@mistralsolutions.com X-Google-Original-From: sabiya.d@ti.com To: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, u-kumar1@ti.com, sabiya.d@mistralsolutions.com, Dasnavis Sabiya Subject: [PATCH V2 1/2] arm64: dts: ti: k3-am69-sk: Enable CAN interfaces for AM69 SK board Date: Tue, 6 Feb 2024 01:37:42 +0530 Message-Id: <20240205200744.216572-2-sabiya.d@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240205200744.216572-1-sabiya.d@ti.com> References: <20240205200744.216572-1-sabiya.d@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-BESS-ID: 1707163696-304267-12419-35371-1 X-BESS-VER: 2019.1_20240201.2150 X-BESS-Apparent-Source-IP: 209.85.214.197 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUirNy1bSUcovVrIysjSxALIygIJJycaJBslmFm ZJyabmBqlGiSnGaUbGqQYpxommRgYWpkq1sQAPbUbmQQAAAA== X-BESS-Outbound-Spam-Score: 0.00 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.254009 [from cloudscan20-102.eu-central-1b.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.00 NO_REAL_NAME HEADER: From: does not include a real name X-BESS-Outbound-Spam-Status: SCORE=0.00 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_BESS_OUTBOUND, BSF_SC0_MISMATCH_TO, NO_REAL_NAME X-BESS-BRTS-Status: 1 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790096793083485179 X-GMAIL-MSGID: 1790096793083485179 From: Dasnavis Sabiya AM69 SK board has several CAN bus interfaces on both MCU and MAIN domains. This enables the CAN interfaces on MCU and MAIN domain. Signed-off-by: Dasnavis Sabiya --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 8da591579868..64c737cc3d49 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -321,6 +321,31 @@ tfp410_out: endpoint { }; }; }; + + transceiver1: can-phy0 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver2: can-phy1 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver3: can-phy2 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + + transceiver4: can-phy3 { + compatible = "ti,tcan1042"; + #phy-cells = <0>; + max-bitrate = <5000000>; + }; + }; &main_pmx0 { @@ -429,6 +454,20 @@ hdmi_hpd_pins_default: hdmi-hpd-default-pins { J784S4_IOPAD(0x000, PIN_INPUT, 7) /* (AN35) EXTINTN.GPIO0_0 */ >; }; + + main_mcan6_pins_default: main-mcan6-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x098, PIN_INPUT, 0) /* (AH36) MCAN6_RX */ + J784S4_IOPAD(0x094, PIN_OUTPUT, 0) /* (AG35) MCAN6_TX */ + >; + }; + + main_mcan7_pins_default: main-mcan7-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0A0, PIN_INPUT, 0) /* (AD34) MCAN7_RX */ + J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ + >; + }; }; &wkup_pmx2 { @@ -525,6 +564,20 @@ hdmi_pdn_pins_default: hdmi-pdn-default-pins { J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 7) /* (H37) WKUP_GPIO0_14 */ >; }; + + mcu_mcan0_pins_default: mcu-mcan0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ + J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ + >; + }; + + mcu_mcan1_pins_default: mcu-mcan1-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ + J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0)/* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ + >; + }; }; &wkup_pmx3 { @@ -992,3 +1045,31 @@ dp0_out: endpoint { }; }; }; + +&mcu_mcan0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan0_pins_default>; + phys = <&transceiver1>; +}; + +&mcu_mcan1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_mcan1_pins_default>; + phys = <&transceiver2>; +}; + +&main_mcan6 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan6_pins_default>; + phys = <&transceiver3>; +}; + +&main_mcan7 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_mcan7_pins_default>; + phys = <&transceiver4>; +}; From patchwork Mon Feb 5 20:07:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dasnavis Sabiya X-Patchwork-Id: 197045 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp1164032dyb; Mon, 5 Feb 2024 13:51:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtYxi1V3SHbFtLbpcCzZwVTU1kJeNE8W7V7laqmQhBieKGfq/fMUan+r/uKRxb3ZiHgK2/ X-Received: by 2002:a05:6402:1a24:b0:560:58f:7148 with SMTP id be4-20020a0564021a2400b00560058f7148mr422168edb.34.1707169902763; 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Mon, 05 Feb 2024 12:08:18 -0800 (PST) From: sabiya.d@mistralsolutions.com X-Google-Original-From: sabiya.d@ti.com To: nm@ti.com, vigneshr@ti.com, kristo@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, linus.walleij@linaro.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, u-kumar1@ti.com, sabiya.d@mistralsolutions.com, Dasnavis Sabiya Subject: [PATCH V2 2/2] arm64: dts: ti: k3-am69-sk: Add support for OSPI flash Date: Tue, 6 Feb 2024 01:37:43 +0530 Message-Id: <20240205200744.216572-3-sabiya.d@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240205200744.216572-1-sabiya.d@ti.com> References: <20240205200744.216572-1-sabiya.d@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-BESS-ID: 1707165271-304267-12419-36669-1 X-BESS-VER: 2019.1_20240201.2150 X-BESS-Apparent-Source-IP: 209.85.216.71 X-BESS-Parts: H4sIAAAAAAACA4uuVkqtKFGyUirNy1bSUcovVrIysjQxBLIygIKWBkmJKWaJqU lGRknJ5hZJlsapZmnJZkkGFmZm5onJZkq1sQC4+3ihQQAAAA== X-BESS-Outbound-Spam-Score: 0.50 X-BESS-Outbound-Spam-Report: Code version 3.2, rules version 3.2.2.254009 [from cloudscan14-232.eu-central-1a.ess.aws.cudaops.com] Rule breakdown below pts rule name description ---- ---------------------- -------------------------------- 0.00 BSF_SC0_MISMATCH_TO META: Envelope rcpt doesn't match header 0.50 BSF_RULE7568M META: Custom Rule 7568M 0.00 BSF_BESS_OUTBOUND META: BESS Outbound 0.00 NO_REAL_NAME HEADER: From: does not include a real name X-BESS-Outbound-Spam-Status: SCORE=0.50 using account:ESS91090 scores of KILL_LEVEL=7.0 tests=BSF_SC0_MISMATCH_TO, BSF_RULE7568M, BSF_BESS_OUTBOUND, NO_REAL_NAME X-BESS-BRTS-Status: 1 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790097388079169746 X-GMAIL-MSGID: 1790097388079169746 From: Dasnavis Sabiya AM69 SK has S28HS512T OSPI flash connected to MCU OSPI0. Enable support for the same. Also describe the partition information according to the offsets in the bootloader. Signed-off-by: Dasnavis Sabiya --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 81 +++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 64c737cc3d49..9ef9aec0b5bd 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -470,6 +470,25 @@ J784S4_IOPAD(0x09C, PIN_OUTPUT, 0) /* (AF35) MCAN7_TX */ }; }; +&wkup_pmx0 { + bootph-all; + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ + J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ + J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ + J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ + J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ + J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ + J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ + >; + }; +}; + &wkup_pmx2 { bootph-all; pmic_irq_pins_default: pmic-irq-default-pins { @@ -1073,3 +1092,65 @@ &main_mcan7 { pinctrl-0 = <&main_mcan7_pins_default>; phys = <&transceiver4>; }; + +&ospi0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0x0>; + spi-tx-bus-width = <8>; + spi-rx-bus-width = <8>; + spi-max-frequency = <25000000>; + cdns,tshsl-ns = <60>; + cdns,tsd2d-ns = <60>; + cdns,tchsh-ns = <60>; + cdns,tslch-ns = <60>; + cdns,read-delay = <4>; + + partitions { + bootph-all; + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "ospi.tiboot3"; + reg = <0x0 0x80000>; + }; + + partition@80000 { + label = "ospi.tispl"; + reg = <0x80000 0x200000>; + }; + + partition@280000 { + label = "ospi.u-boot"; + reg = <0x280000 0x400000>; + }; + + partition@680000 { + label = "ospi.env"; + reg = <0x680000 0x40000>; + }; + + partition@6c0000 { + label = "ospi.env.backup"; + reg = <0x6c0000 0x40000>; + }; + + partition@800000 { + label = "ospi.rootfs"; + reg = <0x800000 0x37c0000>; + }; + + partition@3fc0000 { + bootph-pre-ram; + label = "ospi.phypattern"; + reg = <0x3fc0000 0x40000>; + }; + }; + }; +};