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Mon, 5 Feb 2024 18:43:38 +0000 Received: from EX19MTAUWA001.ant.amazon.com (10.250.64.204) by EX19D031EUB002.ant.amazon.com (10.252.61.105) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40; Mon, 5 Feb 2024 18:43:37 +0000 Received: from dev-dsk-sauravsc-1a-8777b848.eu-west-1.amazon.com (172.19.118.34) by mail-relay.amazon.com (10.250.64.204) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.40 via Frontend Transport; Mon, 5 Feb 2024 18:43:35 +0000 From: Saurav Sachidanand To: Marc Zyngier , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon CC: Saurav Sachidanand , , , Subject: [PATCH] [RFC] KVM: arm64/vgic: Populate GICR_TYPER with Aff3 Date: Mon, 5 Feb 2024 18:43:26 +0000 Message-ID: <20240205184326.78814-1-sauravsc@amazon.com> X-Mailer: git-send-email 2.40.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790085603220892058 X-GMAIL-MSGID: 1790085603220892058 According to spec, bits [63:56] of the GICR_TYPER register are supposed to contain Affinity level 3 (Aff3) bits of the Processing Element (PE) associated with its GIC redistributor. Linux guests on boot match PEs with their redistributor using all four Affinity level bits from this register. Currently, vGIC populates GICR_TYPER with just the first three Affinity levels of a vCPU's MPIDR. This works fine for a Linux guest that boots with KVM's default vCPU MPIDR assignment, which also only populates till the first three Affinity levels. However, a hypervisor can override KVM's default MPIDR assignment by writing directly to a vCPU's MPIDR_EL1 register. If such a hypervisor were to populate Aff3 bits for a VM, a Linux guest booting there would fail to match vCPUs with their vGIC redistributors, since their virtual GICR_TYPER registers would be missing the respective Aff3 bits. To change that, let's populate GICR_TYPER using Aff3 bits [39:32] from the vCPU's MPIDR. Signed-off-by: Saurav Sachidanand --- arch/arm64/kvm/vgic/vgic-mmio-v3.c | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c index c15ee1df036a..26bc838ce14c 100644 --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c @@ -324,6 +324,7 @@ static unsigned long vgic_mmio_read_v3r_typer(struct kvm_vcpu *vcpu, u64 value; value = (u64)(mpidr & GENMASK(23, 0)) << 32; + value |= (u64)((mpidr >> 32) & GENMASK(7, 0)) << 56; value |= ((target_vcpu_id & 0xffff) << 8); if (vgic_has_its(vcpu->kvm))