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Introduce CKSEG0ADDR_OR_64BIT and CKSEG1ADDR_OR_64BIT to get an XPHYS address in 64bits and CKSEG[01]ADDR() in 32 bits mode. Co-developed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/addrspace.h | 5 +++++ arch/mips/include/asm/mach-generic/spaces.h | 4 ++++ 2 files changed, 9 insertions(+) diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h index 59a48c60a065c..03a5e2c8b5dc9 100644 --- a/arch/mips/include/asm/addrspace.h +++ b/arch/mips/include/asm/addrspace.h @@ -47,6 +47,11 @@ */ #define KSEGX(a) ((_ACAST32_(a)) & _ACAST32_(0xe0000000)) +/* + * Gives the size of each kernel segment + */ +#define KSEGX_SIZE 0x20000000 + /* * Returns the physical address of a CKSEGx / XKPHYS address */ diff --git a/arch/mips/include/asm/mach-generic/spaces.h b/arch/mips/include/asm/mach-generic/spaces.h index b247575c5e699..f8783d339fb0d 100644 --- a/arch/mips/include/asm/mach-generic/spaces.h +++ b/arch/mips/include/asm/mach-generic/spaces.h @@ -49,6 +49,8 @@ #define HIGHMEM_START _AC(0x20000000, UL) #endif +#define CKSEG0ADDR_OR_64BIT(x) CKSEG0ADDR(x) +#define CKSEG1ADDR_OR_64BIT(x) CKSEG1ADDR(x) #endif /* CONFIG_32BIT */ #ifdef CONFIG_64BIT @@ -82,6 +84,8 @@ #define TO_CAC(x) (CAC_BASE | ((x) & TO_PHYS_MASK)) #define TO_UNCAC(x) (UNCAC_BASE | ((x) & TO_PHYS_MASK)) +#define CKSEG0ADDR_OR_64BIT(x) TO_CAC(x) +#define CKSEG1ADDR_OR_64BIT(x) TO_UNCAC(x) #endif /* CONFIG_64BIT */ /* From patchwork Mon Feb 5 15:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196865 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp953694dyb; Mon, 5 Feb 2024 07:36:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IFjHhmgVVXKT1kqReAyv40shJ+17i7cF8RMNbco2TiO2UBgMFitgUPmMk9QvVcF89SrGzKz X-Received: by 2002:a05:620a:158f:b0:783:f827:124 with SMTP id d15-20020a05620a158f00b00783f8270124mr12886630qkk.78.1707147380232; Mon, 05 Feb 2024 07:36:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147380; cv=pass; d=google.com; s=arc-20160816; b=BeIDfzSptBqDPY9UR574RZcn7/S3hSKHB7LL/4KTk9AzxkRiRo2kvQlB1JNje2Hs16 1Yy11jPK8bMAA4+pEmwdSAkgXkQIC8A0Ep0vl862qoDJ51B/k40vkQcX+qYdGh5vcX4P KffNWB8ikc0uipbse/JXnZAlnn3CUeJ4IjeGJNct1a2kU5P1qANbLobnDyXblW9NlUE/ MWpXezA0XUQ/0BjnSQ1R+q0jDcsWJSqOlq35gtvWun2p0HxAXINcug9iOzw/l6PDjD2Y c7IXr8mnspZVYBzRyljaxNADVJ4RYVknwOnk2gAiIbnG5O0mTnwVibGjjNPuR5/Lp6xP LQhw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=kCu7pbyVCXYyBTkd+j43VhZPPnMfAyc4JbkgYZulLro=; fh=RBDTGtqaqBT/M5/8NTG5B7VPnqyFJLT82daVWAYAGxA=; b=CqQkQjvh/wBHVQ2nA07pmzTZ1XmkbD3au6fq71pIGOgymnPRBC/0qH3B7eTMApDK80 kfly9CLdamOAY8l4hCUydFnQ9WuSIOVfxVJ9fWyFZnAv8shW0LKFRAOFQkVtB1GRRYPz Elv/r9K+ZOIGn92rb9QECF5hhOS9QJhV4FzhIqqd9xx/3D5RQ16Pgrd3BrSuqzJ1mcl3 WDgLdsYZd4DdLtgtx+IcB9ifuDRkpTDCKpA3SRNvR6kulOkG1b6cQJzAPUkVTs888ePa XwH9yHEMeKuGrzNmTJZaUO98wmAGfTWbofy7ezaOVuSHsCzIX+I1lvrOE2mXqSs1NLFA /+uA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=PbRjKJGe; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52924-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52924-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCVxPEXinoLo2/z+WhGxLncZLFatdQ2nACLuwLJdbM3mmLq7EYfKuqw2x8gToZTDSYzx3M4wdQYNTXRic6QUxSA4JouBGQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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To map EBASE into uncached space, we convert it back to its physical address and utilize the new CKSEG1ADDR_OR_64BIT helper for mapping. Co-developed-by: Vladimir Kondratiev Signed-off-by: Vladimir Kondratiev Co-developed-by: Gregory CLEMENT Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 0e3f2f2fa732b..355d0f0709de8 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2295,7 +2295,7 @@ static const char panic_null_cerr[] = void set_uncached_handler(unsigned long offset, void *addr, unsigned long size) { - unsigned long uncached_ebase = CKSEG1ADDR(ebase); + unsigned long uncached_ebase = CKSEG1ADDR_OR_64BIT(__pa(ebase)); if (!addr) panic(panic_null_cerr); From patchwork Mon Feb 5 15:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196869 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp954358dyb; Mon, 5 Feb 2024 07:37:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IGsDcwcO33wST2Z2zAXcqtUZNvXVuU2lvji5iO+L+AJUbs0+IoZ6NROX5n2SPBKzSzxVztR X-Received: by 2002:a17:907:7745:b0:a36:f854:7a84 with SMTP id kx5-20020a170907774500b00a36f8547a84mr6084062ejc.11.1707147443260; Mon, 05 Feb 2024 07:37:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147443; cv=pass; d=google.com; s=arc-20160816; b=Bg7RavNqPvhHruODiNmRdifYNb3rSScEVIaz8eteXjlKF+B3DRPUb+DVSK257bClu1 4uvMSMYHum22Ok3MefVfXp0UyMRhazoPx77jzVhYoWGXXqzn+u7j9EzxA5hwkdYi2dj5 0P+hDpmWY0y7nDgk8nuIhrBEEvuKn1u58BMRjdmcFyMMxjwh+4hvjmsRTVW4xorqOSC5 1oGWTsJpXh2rdWmwdI2Nprv8vz2Y3DqlX+9MXHgGhCRXZGnnahh5t3f84uPRxrtBHvZC l6Ia8AiM3iouXz92mkr3FuA7Jop/tbwI9FPbhJ1JieGL9CZoPKjK2VHPNv/AlwGbQdM7 Nlxg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=L9FhHosUT371iMjw9Xs3Tj8tq8si8nd8C8MXoIw+WeM=; fh=lO4Dd5pS7uK8JKmxKjfzxLhTM5mcSFWWP9o30zP62uk=; b=x2t3QNGFBate+w+13adC0Z97km56ej/Y1E89UGHXDOJO0gqkmI7kBDPeJj+hn0ufwa 5slY6uiT3Yv740uDoiIo0KnZ8gRObToc5SU3gGXGE1op+HQJdvmrUQkst68migNFHdMs 0ewyLdeocpD7lMAo5Sw7Yi4lwYBWfLlsaZHmd6gfBDSAqc+C6pb6Hjp7SDptNKz4G/ib BKTC48iNTUyCwWZNdgZaKfgSNz8tjqvrfSsps3BuxJk5OYNdff+UqpXKdWg0AjOrM4K8 ovr2zAWYHmbyPqcADOKxqjLS+Qia8wIC3XeAB8zjGoAiCLgXigYHygN6c0lRJCl+e6cp N6KQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=OFSE16+w; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52926-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52926-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCV9rtTFCxEVoVb/d8R9xuW3Vp4djR3pffzgBtH7bXzQMUpDDsm2+Ua3/9gecEB6rCImWk3fJAGC/viokkyk79Z7xHzZXg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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It will try to allocate from KSEG1 first, and then try to allocate in low 4G if possible. The main reset vector is now generated by uasm, to avoid tons of patches to the code. Other vectors are copied to the location later. gc: use the new macro CKSEG[0A1]DDR_OR_64BIT() move 64bits fix in an other patch fix cache issue with mips_cps_core_entry rewrite the patch to reduce the diff stat Signed-off-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/include/asm/mips-cm.h | 1 + arch/mips/include/asm/smp-cps.h | 4 +- arch/mips/kernel/cps-vec.S | 48 ++------- arch/mips/kernel/smp-cps.c | 171 +++++++++++++++++++++++++++----- 4 files changed, 157 insertions(+), 67 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index 23c67c0871b17..15d8d69de4550 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -311,6 +311,7 @@ GCR_CX_ACCESSOR_RW(32, 0x018, other) /* GCR_Cx_RESET_BASE - Configure where powered up cores will fetch from */ GCR_CX_ACCESSOR_RW(32, 0x020, reset_base) #define CM_GCR_Cx_RESET_BASE_BEVEXCBASE GENMASK(31, 12) +#define CM_GCR_Cx_RESET_BASE_MODE BIT(1) /* GCR_Cx_ID - Identify the current core */ GCR_CX_ACCESSOR_RO(32, 0x028, id) diff --git a/arch/mips/include/asm/smp-cps.h b/arch/mips/include/asm/smp-cps.h index 22a572b70fe31..39a602e5fecc4 100644 --- a/arch/mips/include/asm/smp-cps.h +++ b/arch/mips/include/asm/smp-cps.h @@ -24,7 +24,7 @@ struct core_boot_config { extern struct core_boot_config *mips_cps_core_bootcfg; -extern void mips_cps_core_entry(void); +extern void mips_cps_core_boot(int cca, void __iomem *gcr_base); extern void mips_cps_core_init(void); extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); @@ -32,8 +32,6 @@ extern void mips_cps_boot_vpes(struct core_boot_config *cfg, unsigned vpe); extern void mips_cps_pm_save(void); extern void mips_cps_pm_restore(void); -extern void *mips_cps_core_entry_patch_end; - #ifdef CONFIG_MIPS_CPS extern bool mips_cps_smp_in_use(void); diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index 64ecfdac6580b..df610c006b443 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -4,6 +4,7 @@ * Author: Paul Burton */ +#include #include #include #include @@ -82,39 +83,10 @@ .endm -.balign 0x1000 - -LEAF(mips_cps_core_entry) - /* - * These first several instructions will be patched by cps_smp_setup to load the - * CCA to use into register s0 and GCR base address to register s1. - */ - .rept CPS_ENTRY_PATCH_INSNS - nop - .endr - - .global mips_cps_core_entry_patch_end -mips_cps_core_entry_patch_end: - - /* Check whether we're here due to an NMI */ - mfc0 k0, CP0_STATUS - and k0, k0, ST0_NMI - beqz k0, not_nmi - nop - - /* This is an NMI */ - PTR_LA k0, nmi_handler - jr k0 - nop - -not_nmi: - /* Setup Cause */ - li t0, CAUSEF_IV - mtc0 t0, CP0_CAUSE - - /* Setup Status */ - li t0, ST0_CU1 | ST0_CU0 | ST0_BEV | STATUS_BITDEPS - mtc0 t0, CP0_STATUS +LEAF(mips_cps_core_boot) + /* Save CCA and GCR base */ + move s0, a0 + move s1, a1 /* We don't know how to do coherence setup on earlier ISA */ #if MIPS_ISA_REV > 0 @@ -178,49 +150,45 @@ not_nmi: PTR_L sp, VPEBOOTCFG_SP(v1) jr t1 nop - END(mips_cps_core_entry) + END(mips_cps_core_boot) -.org 0x200 + __INIT LEAF(excep_tlbfill) DUMP_EXCEP("TLB Fill") b . nop END(excep_tlbfill) -.org 0x280 LEAF(excep_xtlbfill) DUMP_EXCEP("XTLB Fill") b . nop END(excep_xtlbfill) -.org 0x300 LEAF(excep_cache) DUMP_EXCEP("Cache") b . nop END(excep_cache) -.org 0x380 LEAF(excep_genex) DUMP_EXCEP("General") b . nop END(excep_genex) -.org 0x400 LEAF(excep_intex) DUMP_EXCEP("Interrupt") b . nop END(excep_intex) -.org 0x480 LEAF(excep_ejtag) PTR_LA k0, ejtag_debug_handler jr k0 nop END(excep_ejtag) + __FINIT LEAF(mips_cps_core_init) #ifdef CONFIG_MIPS_MT_SMP diff --git a/arch/mips/kernel/smp-cps.c b/arch/mips/kernel/smp-cps.c index dd55d59b88db3..f4cdd50177e0b 100644 --- a/arch/mips/kernel/smp-cps.c +++ b/arch/mips/kernel/smp-cps.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -25,7 +26,34 @@ #include #include +#define BEV_VEC_SIZE 0x500 +#define BEV_VEC_ALIGN 0x1000 + +#define A0 4 +#define A1 5 +#define T9 25 +#define K0 26 +#define K1 27 + +#define C0_STATUS 12, 0 +#define C0_CAUSE 13, 0 + +#define ST0_NMI_BIT 19 +#ifdef CONFIG_64BIT +#define ST0_KX_IF_64 ST0_KX +#else +#define ST0_KX_IF_64 0 +#endif + +enum label_id { + label_not_nmi = 1, +}; + +UASM_L_LA(_not_nmi) + static DECLARE_BITMAP(core_power, NR_CPUS); +static uint32_t core_entry_reg; +static phys_addr_t cps_vec_pa; struct core_boot_config *mips_cps_core_bootcfg; @@ -34,10 +62,115 @@ static unsigned __init core_vpe_count(unsigned int cluster, unsigned core) return min(smp_max_threads, mips_cps_numvps(cluster, core)); } +static void __init *mips_cps_build_core_entry(void *addr) +{ + extern void (*nmi_handler)(void); + u32 *p = addr; + u32 val; + struct uasm_label labels[2]; + struct uasm_reloc relocs[2]; + struct uasm_label *l = labels; + struct uasm_reloc *r = relocs; + + memset(labels, 0, sizeof(labels)); + memset(relocs, 0, sizeof(relocs)); + + uasm_i_mfc0(&p, K0, C0_STATUS); + if (cpu_has_mips_r2_r6) + uasm_i_ext(&p, K0, K0, ST0_NMI_BIT, 1); + else { + uasm_i_srl(&p, K0, K0, ST0_NMI_BIT); + uasm_i_andi(&p, K0, K0, 0x1); + } + + uasm_il_bnez(&p, &r, K0, label_not_nmi); + uasm_i_nop(&p); + UASM_i_LA(&p, K0, (long)&nmi_handler); + + uasm_l_not_nmi(&l, p); + + val = CAUSEF_IV; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_CAUSE); + val = ST0_CU1 | ST0_CU0 | ST0_BEV | ST0_KX_IF_64; + uasm_i_lui(&p, K0, val >> 16); + uasm_i_ori(&p, K0, K0, val & 0xffff); + uasm_i_mtc0(&p, K0, C0_STATUS); + uasm_i_ehb(&p); + uasm_i_ori(&p, A0, 0, read_c0_config() & CONF_CM_CMASK); + UASM_i_LA(&p, A1, (long)mips_gcr_base); +#if defined(KBUILD_64BIT_SYM32) || defined(CONFIG_32BIT) + UASM_i_LA(&p, T9, CKSEG1ADDR(__pa_symbol(mips_cps_core_boot))); +#else + UASM_i_LA(&p, T9, TO_UNCAC(__pa_symbol(mips_cps_core_boot))); +#endif + uasm_i_jr(&p, T9); + uasm_i_nop(&p); + + uasm_resolve_relocs(relocs, labels); + + return p; +} + +static int __init allocate_cps_vecs(void) +{ + /* Try to allocate in KSEG1 first */ + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, KSEGX_SIZE - 1); + + if (cps_vec_pa) + core_entry_reg = CKSEG1ADDR(cps_vec_pa) & + CM_GCR_Cx_RESET_BASE_BEVEXCBASE; + + if (!cps_vec_pa && mips_cm_is64) { + cps_vec_pa = memblock_phys_alloc_range(BEV_VEC_SIZE, BEV_VEC_ALIGN, + 0x0, SZ_4G - 1); + if (cps_vec_pa) + core_entry_reg = (cps_vec_pa & CM_GCR_Cx_RESET_BASE_BEVEXCBASE) | + CM_GCR_Cx_RESET_BASE_MODE; + } + + if (!cps_vec_pa) + return -ENOMEM; + + return 0; +} + +static void __init setup_cps_vecs(void) +{ + extern void excep_tlbfill(void); + extern void excep_xtlbfill(void); + extern void excep_cache(void); + extern void excep_genex(void); + extern void excep_intex(void); + extern void excep_ejtag(void); + void *cps_vec; + + /* We want to ensure cache is clean before writing uncached mem */ + blast_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); + bc_wback_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); + __sync(); + + cps_vec = (void *)CKSEG1ADDR_OR_64BIT(cps_vec_pa); + mips_cps_build_core_entry(cps_vec); + + memcpy(cps_vec + 0x200, &excep_tlbfill, 0x80); + memcpy(cps_vec + 0x280, &excep_xtlbfill, 0x80); + memcpy(cps_vec + 0x300, &excep_cache, 0x80); + memcpy(cps_vec + 0x380, &excep_genex, 0x80); + memcpy(cps_vec + 0x400, &excep_intex, 0x80); + memcpy(cps_vec + 0x480, &excep_ejtag, 0x80); + + /* Make sure no prefetched data in cache */ + blast_inv_dcache_range(CKSEG0ADDR_OR_64BIT(cps_vec_pa), CKSEG0ADDR_OR_64BIT(cps_vec_pa) + BEV_VEC_SIZE); + bc_inv(CKSEG0ADDR_OR_64BIT(cps_vec_pa), BEV_VEC_SIZE); + __sync(); +} + static void __init cps_smp_setup(void) { unsigned int nclusters, ncores, nvpes, core_vpes; - unsigned long core_entry; int cl, c, v; /* Detect & record VPE topology */ @@ -94,10 +227,11 @@ static void __init cps_smp_setup(void) /* Make core 0 coherent with everything */ write_gcr_cl_coherence(0xff); - if (mips_cm_revision() >= CM_REV_CM3) { - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_bev_base(core_entry); - } + if (allocate_cps_vecs()) + pr_err("Failed to allocate CPS vectors\n"); + + if (core_entry_reg && mips_cm_revision() >= CM_REV_CM3) + write_gcr_bev_base(core_entry_reg); #ifdef CONFIG_MIPS_MT_FPAFF /* If we have an FPU, enroll ourselves in the FPU-full mask */ @@ -110,10 +244,14 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) { unsigned ncores, core_vpes, c, cca; bool cca_unsuitable, cores_limited; - u32 *entry_code; mips_mt_set_cpuoptions(); + if (!core_entry_reg) { + pr_err("core_entry address unsuitable, disabling smp-cps\n"); + goto err_out; + } + /* Detect whether the CCA is unsuited to multi-core SMP */ cca = read_c0_config() & CONF_CM_CMASK; switch (cca) { @@ -145,20 +283,7 @@ static void __init cps_prepare_cpus(unsigned int max_cpus) (cca_unsuitable && cpu_has_dc_aliases) ? " & " : "", cpu_has_dc_aliases ? "dcache aliasing" : ""); - /* - * Patch the start of mips_cps_core_entry to provide: - * - * s0 = kseg0 CCA - */ - entry_code = (u32 *)&mips_cps_core_entry; - uasm_i_addiu(&entry_code, 16, 0, cca); - UASM_i_LA(&entry_code, 17, (long)mips_gcr_base); - BUG_ON((void *)entry_code > (void *)&mips_cps_core_entry_patch_end); - blast_dcache_range((unsigned long)&mips_cps_core_entry, - (unsigned long)entry_code); - bc_wback_inv((unsigned long)&mips_cps_core_entry, - (void *)entry_code - (void *)&mips_cps_core_entry); - __sync(); + setup_cps_vecs(); /* Allocate core boot configuration structs */ ncores = mips_cps_numcores(0); @@ -213,7 +338,7 @@ static void boot_core(unsigned int core, unsigned int vpe_id) mips_cm_lock_other(0, core, 0, CM_GCR_Cx_OTHER_BLOCK_LOCAL); /* Set its reset vector */ - write_gcr_co_reset_base(CKSEG1ADDR((unsigned long)mips_cps_core_entry)); + write_gcr_co_reset_base(core_entry_reg); /* Ensure its coherency is disabled */ write_gcr_co_coherence(0); @@ -290,7 +415,6 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) unsigned vpe_id = cpu_vpe_id(&cpu_data[cpu]); struct core_boot_config *core_cfg = &mips_cps_core_bootcfg[core]; struct vpe_boot_config *vpe_cfg = &core_cfg->vpe_config[vpe_id]; - unsigned long core_entry; unsigned int remote; int err; @@ -314,8 +438,7 @@ static int cps_boot_secondary(int cpu, struct task_struct *idle) if (cpu_has_vp) { mips_cm_lock_other(0, core, vpe_id, CM_GCR_Cx_OTHER_BLOCK_LOCAL); - core_entry = CKSEG1ADDR((unsigned long)mips_cps_core_entry); - write_gcr_co_reset_base(core_entry); + write_gcr_co_reset_base(core_entry_reg); mips_cm_unlock_other(); } From patchwork Mon Feb 5 15:34:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196866 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp953867dyb; Mon, 5 Feb 2024 07:36:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IFFHxaOYankKz7kX9s0zPfDZS0SZc7X6ukLKl5VzOB9Ra0Mr2vrF9Pju3Zq9y6NUiszvT3U X-Received: by 2002:a0c:9b02:0:b0:68c:a560:edaf with SMTP id b2-20020a0c9b02000000b0068ca560edafmr2500920qve.18.1707147398404; Mon, 05 Feb 2024 07:36:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147398; cv=pass; d=google.com; s=arc-20160816; b=sn70254EWjx8Yhwy2C/auPw9wAM/Bveg0F4IDMqpyDr5FfUvAi0j/SuXVei1P5xLF/ uVlkRDg9bcjrhQYT0SzobZbp0zuALXEllyjiABzo/bqDqGbK5xmjmtHjT8C2DGxzItF5 VqiIJFLNqQdJ8gSGKqxcEOp6ogMygoZkMTI/fIiG2jG1ImqbbPRHjPJMBTD0yQgBBk/p ZEoR+RrIY/LvZhmuif0M2ZoiojrT3kEv75BodMSCcjLXgq7HiSQCWrLm42vfrB8+Rj2d 8Jyjzv8RZFJWRpvcXt7ODYylPAAn/RQM0PPmZsmDM2fT7l+ofi4ZvpvPPISP3eU/0zUv 8a6w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=esfeCMI7Pwpjz+uzSpSUDXn4KCrjxw72sDAlH2LRRks=; fh=TQ67dPoje9zf4yC/ELlfYb7tM6T7XCuU1FSnDtJqi9s=; b=jRYEnJpNxNln37w5xIlvSxp+QzP1HowRt91ydW3lfIdKyW5D3PYdLZdwPNmcJ3Wpk8 84A9HzHG7oOF9KJeStEdM0d3g3766BDb9IQT6DnY5N17iXs6itGE3OGCRTPzDgxUVba1 QvdK9ejEbPQPILXnoxXBLKeGFlQxwqU0bPM7SQj/emfOllJDwslXHVCfqij0PNiSvRW/ TMs4TjipNsP9hYFuBNFJWm1+CLrA11dC+EjgvELrG/89F1Fs+v+ohGrYBlC/o6w1NzFl XvLY2ARnOtSTQkUhtOmvCJH31EVOjToxGSNBQhJ7Wl9185r3PDB4gZHnW431Ax5ZF/nw SRTA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=jaTCArOJ; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52925-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52925-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCW/on+SQiHqQkmp4rtHscVn1Oo8l1qmfhoIkWqyaW4W1Onf8WPMse3C01R9axSFSemepuX5neQZpxoptE1aQC2QzWDEhw== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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d=bootlin.com; s=gm1; t=1707147310; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=esfeCMI7Pwpjz+uzSpSUDXn4KCrjxw72sDAlH2LRRks=; b=jaTCArOJUbwNw5HiAKOEX5uVtZ1sgVDqqQhs8RvBNz+tZCAClENSE1h3tjRDLbU56lHleX yceVEgesS4BoNf7fPq7dx/2u/Y82/PjZ4IXxAptaKIWo9M50MdH13jjpgAN8mo7MD5JEkL L+En+wNaMur8UHAihFC9x8H43d4rXNhM2yl+tZ3MfTngZDvr7M3XLfqY6NKjeQRjkwJzMG pUDFAGIGjIiUgP4kqffMG29+BKhWahnt/dcE5twYsLDce7S+Dz7kJ8OeEHxHHAgLh8xPpH EMXLdmr7DSFGTPq3KWZi6Y8c5u8jFjfscSuv9M0iY14hMAP5VJiKybGv353VGQ== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v7 04/14] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Date: Mon, 5 Feb 2024 16:34:50 +0100 Message-ID: <20240205153503.574468-5-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205153503.574468-1-gregory.clement@bootlin.com> References: <20240205153503.574468-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790073790596684279 X-GMAIL-MSGID: 1790073790596684279 With the expanded support for placing the kernel in XPHYS rather than just KSEG0, scenarios where ebase doesn't belong to KSEG0 are more likely to occur. In such cases, we currently experience a substantial and perplexing stack dump without any accompanying explanation. To rectify this, we aim to replace the uninformative stack dump with a warning that offers a clear explanation of the issue. Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/traps.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c index 355d0f0709de8..911d2233d6d0b 100644 --- a/arch/mips/kernel/traps.c +++ b/arch/mips/kernel/traps.c @@ -2347,10 +2347,13 @@ void __init trap_init(void) * EVA is special though as it allows segments to be rearranged * and to become uncached during cache error handling. */ - if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) + if (!IS_ENABLED(CONFIG_EVA) && ebase_pa < 0x20000000) ebase = CKSEG0ADDR(ebase_pa); else ebase = (unsigned long)phys_to_virt(ebase_pa); + if (ebase_pa >= 0x20000000) + pr_warn("ebase(%pa) should better be in KSeg0", + &ebase_pa); } if (cpu_has_mmips) { From patchwork Mon Feb 5 15:34:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196867 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp954259dyb; Mon, 5 Feb 2024 07:37:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IE1LZycnHIjsoEjTsRBvM77HjbqYyNZvU8XNWIMqBh2sAhfESWZMj8gx19KgUG4fY01oJ6z X-Received: by 2002:a05:622a:a8b:b0:42b:f0dc:b141 with SMTP id ku11-20020a05622a0a8b00b0042bf0dcb141mr5717476qtb.8.1707147433010; Mon, 05 Feb 2024 07:37:13 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147432; cv=pass; d=google.com; s=arc-20160816; b=KRpbi5Uvac7+gIZb5OFcC1nniqdOmqUBEmg6uSwHZ9a6RfOc6VVc5AhVOl/7dLu6JB RXGA6YC4F5SMQ55jipMXj6hpi9Hco39tDY8GZUictbNP0mpv0tfIDCyCBBmLEKYptPxZ 23bD0fAFM/0kWcSp0NBeaJNz+yqT0ios1PXvzBmxiWTcAlf7onZOAm9M5t2FoYFTveL2 3gehvP7s59sBalwrD7+jWGaed3HfuXmXreYrnvuwEWnNnVUdMSvB1+CpJ9NidXToNAEt dIJW0zEz2EdDVgwQ7jZHFh0ZToD0/BVv3al7YdmTaRrXW44MJkwU229CJq+AY9Fgnx/o l31Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=6uEXIbyuTE8+uGbb2wp9Vlt8m5ypasCyIw0FxaqtHUs=; fh=kyPQIfKGd2CtIyEsbSNZRdvadFO/RF3mDRjhlLtOgSE=; b=O+E5yBqgvWvf6vRqGbn5nsv0d0Qk6TPRvTOCd7tkpZlTAsjZZNs1Wbvc0nB9vE5r8E szKQmjI5c9MujBn6fUVo9WSfZD+Q1bjwNfV7OOPI/ThD10fNQg2nOA5dDF1p9Ll5uRCS Nwrbr3ySOhyFAPG5sPteRQAnGJtK6+nVxmIk5QHDqZ8Kvo1knqcSUoUUs/89b54FfqWl NMDoeRqT8pLnvPhz1WufI7E4wyZvz6hOYw/xjt5eXS9STWaqVZmDSuVhyuxRNVRVhK0F ZG0+cdStrVxSuKzZRf6cr/He1BkwhMWFB/tSyi/Caf73bdiXsUrPsgu+K4UEoAav0mnA NblA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=lNWXhzeV; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52927-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52927-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWvrmBhLbCqwq2HIt/ZXO8RJZH5FlOhiQxb75MhtmMlqw5lMTDY8We8I2mgqartUPxye9xpBGJd24WoZ7qrZVW8SWrlcw== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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This was extract from an initial patch from Jiaxun Co-developed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/kernel/cps-vec.S | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/mips/kernel/cps-vec.S b/arch/mips/kernel/cps-vec.S index df610c006b443..f876309130ad1 100644 --- a/arch/mips/kernel/cps-vec.S +++ b/arch/mips/kernel/cps-vec.S @@ -396,7 +396,7 @@ LEAF(mips_cps_boot_vpes) /* Calculate a pointer to the VPEs struct vpe_boot_config */ li t0, VPEBOOTCFG_SIZE mul t0, t0, ta1 - addu t0, t0, ta3 + PTR_ADDU t0, t0, ta3 /* Set the TC restart PC */ lw t1, VPEBOOTCFG_PC(t0) @@ -571,10 +571,10 @@ dcache_done: lw $1, TI_CPU(gp) sll $1, $1, LONGLOG PTR_LA \dest, __per_cpu_offset - addu $1, $1, \dest + PTR_ADDU $1, $1, \dest lw $1, 0($1) PTR_LA \dest, cps_cpu_state - addu \dest, \dest, $1 + PTR_ADDU \dest, \dest, $1 .set pop .endm From patchwork Mon Feb 5 15:34:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196868 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp954280dyb; Mon, 5 Feb 2024 07:37:14 -0800 (PST) X-Google-Smtp-Source: AGHT+IHkzefdi+KsxjOYeoaKy3uQyzMRTa5LZPt5B11iCsXFgIyU2dIwPixYdIg9lGK+wuITb5bx X-Received: by 2002:a17:906:49:b0:a35:85b7:560a with SMTP id 9-20020a170906004900b00a3585b7560amr7425120ejg.46.1707147434589; Mon, 05 Feb 2024 07:37:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147434; cv=pass; d=google.com; s=arc-20160816; b=ZmH125AXCnmU6Sp3Hjy97EBBmSeiogGfQAoCJV8ae6Lq52J7OooFoPdeDk2wFu3Vya CJGDV341KtlybE0jAecScHO4NKLWoftMLkf2FZGlJKJHIn/+a+/wKvFIFWIRHWQ5sZeW dmlFiM+tuUnZ5UqFVUj+ZYlzs2EDo4ys0s50KKTFbBcz0yLKR1KjEKZ5Y6gxpGdJv5S7 a89WEyJLyuQJjuw45HK+uZtjMlb+h+PaKd7i9tqKln9rG/++fUgEjoq3HbE1PZYWxIXG RGztXYsiO0zpfn6jU9SvteVgIlj0BYiyBgdlp1WRTPFeGIW1NOOvvIWaO7KndnIs3GJo 1hiQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=R/UuJlLlj7UNzM37CJzBwzJx6aNeNRPUwdDv7PdUBac=; fh=WXF1y9bM59L6tKm38xQiH2QMG+wHNkOVwYF5CHjJkbw=; b=UNJuLdRyBMoVZOxr2quCR99zOm/TuLo6ONIBIZShflMoqzW4FTY+5iQlr/AOmybofi s5rHS0a6RlJ7RfrwSsOrWH5t7zK/gWg59m3hYIz7p0vCm2J1kIgCXraqPxQ8nlnXEvGy e0tb+TGBDt9IyXdk6U+/1PJ7NyupOQXH7M20nKGf5mShc8uEedIV9kpNYa/nJykKILLf c1zSti+p0oHWzd5EoEqiiQZWr6A9izi8Jqnr0GK53uOIscz/1Eo0G/5wQQOjxNQlfvgo RQvSXvcCSxJlPOZ9EQ/0iBsaRx03EzcJ/FkpDOSshc3p6Evj7WM1hOv5fKA2OrJA8OBc SVYg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=mayL4sYR; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52928-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52928-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCW03xDONyZYR1s2QNCrrSTfyalllMS2fzB+i+En+Jkx5j9c8uqS18fCgTU8yDSFdn9IDOkkcmNGR0MOai3X3ieFnu6mcQ== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Date: Mon, 5 Feb 2024 16:34:52 +0100 Message-ID: <20240205153503.574468-7-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205153503.574468-1-gregory.clement@bootlin.com> References: <20240205153503.574468-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790073828530509159 X-GMAIL-MSGID: 1790073828530509159 Mobileye Vision Technologies Ltd. is a company developing autonomous driving technologies and advanced driver-assistance systems (ADAS) including cameras, computer chips and software. Reviewed-by: Philippe Mathieu-Daudé Acked-by: Rob Herring Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 309b94c328c84..b45279bc97c14 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -897,6 +897,8 @@ patternProperties: description: Miyoo "^mntre,.*": description: MNT Research GmbH + "^mobileye,.*": + description: Mobileye Vision Technologies Ltd. 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Let's fix it. Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index cf382dea3922c..9bc47868d28b6 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,22 +23,22 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 - - ingenic,xburst-mxu1.0 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 + - ingenic,xburst-mxu1.0 - ingenic,xburst2-fpu2.1-mxu2.1-smt - loongson,gs264 - mips,m14Kc - - mips,mips4Kc - - mips,mips4KEc - - mips,mips24Kc + - mips,mips1004Kc - mips,mips24KEc + - mips,mips24Kc + - mips,mips4KEc + - mips,mips4Kc - mips,mips74Kc - - mips,mips1004Kc - mti,interaptiv - - mti,mips24KEc - mti,mips14KEc - mti,mips14Kc + - mti,mips24KEc reg: maxItems: 1 From patchwork Mon Feb 5 15:34:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196871 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp955063dyb; Mon, 5 Feb 2024 07:38:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IGyREZEWxUf1LKUrLm0yW33cDKxCWy1uQup8L9RjRHLZD/yfXqNynVYWlcASDkcFmoDB4+V X-Received: by 2002:a62:ce43:0:b0:6e0:4a04:2282 with SMTP id y64-20020a62ce43000000b006e04a042282mr1840430pfg.22.1707147513385; Mon, 05 Feb 2024 07:38:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147513; cv=pass; d=google.com; s=arc-20160816; b=SjPxzGKC56s2dRz850jdyVsdxct5cvkWHLR5WMYcqQH32BX3pdsWOuPOiPnaD7SYwo TcObxhNSBsuticzf9KDlD00Rw2BRDBxb3cdI2kSOGRuUdCDQYCD3dk1boGUtLApvAKi5 jS/L59tbfvnLY0cMPqJfgxMLuRvZ33zxSMHKspxeVcGDpDMI4oM7ni+NMXRo77UvXPLq xEPR1u5+vK5/Pnydd3g0X/owPXVFfOHx8coilyKaJlD3YbT15QP54JegDLVOwPPhxuLp gSAVuxC1phun8S1uMvNoBMp3nrX27ytQM/F2Wau3fzj0g50vcMGtEQMmM6p15LGtJBq3 Xt5w== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GbsWh/XsZeOFv6yit27z5l5/TqUISO3EzDeBeQy/R68=; fh=tmjRQQPu6ZQlawfqBB6wbltBL/hjh8X3r/0l8KZk6Fs=; b=aQvTaTA9wblHFi/sDVSJKT3cuzfGeetoEtsYkqepja/Q7BxIRhLHWi+wGPjX+fK6cW /mYHHYN9/Zb1j2AVhetdZAioaDtfYT6fAMT1fVPdgqLUjG5vdAdGr8Pi8wAZdGz/kLV/ VtbeZmobDakTEDIWttnoAGZn9mpjePF9Gm0js79867grcuIixBGuruhz+e6ylKOCuJyO 09zAvnkXs2q1HRGR94ilAC5D+sPCblg75KdoTBM6pHTAmf2MG4Vo8pBMtdMfSsH60XU2 pEdkGGoRAyEBl8zwlR274nem3SCWf9wle09VLG8VjyLYSoygpumupiHmhJuY/ilz7rkJ U7tw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Je6psvHr; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52930-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52930-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWPDFzlVS3YSe00QJ/NUuJYz3Xf3j7Jc42ytVI5mubdhmLT1bu5REQkI0OeifWTjDBDR6KkGymrlvJ1ihSnCIkyfXFY+w== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1707147314; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=GbsWh/XsZeOFv6yit27z5l5/TqUISO3EzDeBeQy/R68=; b=Je6psvHrJ9MCiX4Z7guNm8f0H31MFCdLInAkLRPKVMic9pynQmaM8hj8U3uXOeU9MENs0p FQu5p9GT5Oct0bQUGtqSVn9aYOlhDqFgSeBBtgC7SJf5EOd2Yd4GlwzfnDa+GiiH0/4Wly cvjmoU9Znm/PfnLKMircaVMj3sFoJRh45OWUvv5jWqy1X4p2HHml7I5USL2LtrBiGkMnHS wvG/Fnea6cfgWD5Ukkw26fPHvO6sRI7rYdZ56y8Xg/ro8GaDV8CUqBvb5Vvu1cvyQTM2FZ 7LF3CXw//gJDydBkHqV/vfx/Xk5q161zwdRSBTBpm3sfO/2sN4VarCk4XZikqA== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT , Arnd Bergmann , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Serge Semin , Krzysztof Kozlowski Subject: [PATCH v7 08/14] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Date: Mon, 5 Feb 2024 16:34:54 +0100 Message-ID: <20240205153503.574468-9-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205153503.574468-1-gregory.clement@bootlin.com> References: <20240205153503.574468-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790073911316799541 X-GMAIL-MSGID: 1790073911316799541 The MIPS Warrior I-class I6500 was announced by Imagination Technologies in 2016 and is used in the Mobileye SoC EyeQ5. Acked-by: Arnd Bergmann Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Serge Semin Acked-by: Krzysztof Kozlowski Signed-off-by: Gregory CLEMENT --- Documentation/devicetree/bindings/mips/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mips/cpus.yaml b/Documentation/devicetree/bindings/mips/cpus.yaml index 9bc47868d28b6..a85137add6689 100644 --- a/Documentation/devicetree/bindings/mips/cpus.yaml +++ b/Documentation/devicetree/bindings/mips/cpus.yaml @@ -23,6 +23,7 @@ properties: - brcm,bmips4380 - brcm,bmips5000 - brcm,bmips5200 + - img,i6500 - ingenic,xburst-fpu1.0-mxu1.1 - ingenic,xburst-fpu2.0-mxu2.0 - ingenic,xburst-mxu1.0 From patchwork Mon Feb 5 15:34:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196911 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp973631dyb; Mon, 5 Feb 2024 08:07:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMkFWmYgRtuSvRXFz1kMVuTko5r01sK2VK6wUtQ9lQ5N9WN8h0CBwF3o8VDsB0rRe1Grr1 X-Received: by 2002:a05:6a20:89a7:b0:19c:89f4:c2d7 with SMTP id h39-20020a056a2089a700b0019c89f4c2d7mr16746201pzg.34.1707149245146; Mon, 05 Feb 2024 08:07:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707149245; cv=pass; d=google.com; s=arc-20160816; b=ZMn+APnMero2r3mQPIOouzgcJZwunZPEfynssyZk8Pv9NtsibBtDlZ9583jOL/QCO1 p8QDahow8y1SBMe53UOPkTZ9Y7mYseFIimQbs1rSMxGxcPCxpXGVAFcBlsvanXL6jtEV QnAx7ij74zunubFYSsq8MgIm1p9l3ohGm8CRU1RRZd5Ns5YvbMCnT505Im7imjf72i4w dS4o/cOJq/1KhWw+/fGKz1IcYL2OgwzpXc/V86BLU/btsBHrNWhVh/Ie/IfloEDk/4nr d3N0ckAQA8lEOkkrtDqpKU17JSWuQspUKTUOvrAOOYs3ZiZ6jvD6flQ5pd5XCHZZd0Kt AnvA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=KtLJx1LoT2GXTWyVjN+1FeAU3avbgKgLJY8tRT/zqqY=; fh=bu/5mzB6n/rf8oIR/1J044E87y5OAeuaPhMacAik61I=; b=xvTQlOTUnXdMQ/xdFPnpr262axZ2ep2ZW2vcJDZ+9NKIVdHuEDdFqTD3MK63QwNKCi abvhQa8PVR+uxtofG71DA8wKsNnU7X+6OfzNHKYeauNwi7+KC673LGI3EUNQwTwzxYIf sWlPt/P+1Z/H/ZpynJEgT7Cvr0tH6UHKZ4dmQDCGbkEUn/ogCaipOUEvlg5Xo4Ss6kch x4mdttbSWRRTKjW2QtqBx5UuxmiMjQK2ugSRDWpIiIRNsWW+HGRbE4QwfWyLcYkGUZTn hrmjpWr8jfuW/vzIGkdvszGRq5w0ne5G7Zp1wScpM+C+h/ihLCsPzJa8vOYH0CtRNqEd bjfg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="Ggj/MG1L"; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52931-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52931-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWuAraKuOG04U1AH+FgGi0A0X1cG/0g1+rkbLZzx6nuOlpGNUJZUTiswenV5qIRRRO7myUIlnzB6P0EV3/3cO1FmHA1Ew== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Currently only EyeQ5 is supported Reviewed-by: Rob Herring Signed-off-by: Gregory CLEMENT --- .../devicetree/bindings/mips/mobileye.yaml | 32 +++++++++++++++++++ 1 file changed, 32 insertions(+) create mode 100644 Documentation/devicetree/bindings/mips/mobileye.yaml diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml new file mode 100644 index 0000000000000..831975f6b479f --- /dev/null +++ b/Documentation/devicetree/bindings/mips/mobileye.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +# Copyright 2023 Mobileye Vision Technologies Ltd. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mips/mobileye.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye SoC series + +maintainers: + - Vladimir Kondratiev + - Gregory CLEMENT + - Théo Lebrun + +description: + Boards with a Mobileye SoC shall have the following properties. + +properties: + $nodename: + const: '/' + + compatible: + oneOf: + - description: Boards with Mobileye EyeQ5 SoC + items: + - enum: + - mobileye,eyeq5-epm5 + - const: mobileye,eyeq5 + +additionalProperties: true + +... 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Based on the work of Slava Samsonov Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/Makefile | 1 + .../boot/dts/mobileye/eyeq5-fixed-clocks.dtsi | 292 ++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 124 ++++++++ 3 files changed, 417 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi create mode 100644 arch/mips/boot/dts/mobileye/eyeq5.dtsi diff --git a/arch/mips/boot/dts/Makefile b/arch/mips/boot/dts/Makefile index 928f38a79dff9..efff87cb33a9e 100644 --- a/arch/mips/boot/dts/Makefile +++ b/arch/mips/boot/dts/Makefile @@ -8,6 +8,7 @@ subdir-$(CONFIG_LANTIQ) += lantiq subdir-$(CONFIG_MACH_LOONGSON64) += loongson subdir-$(CONFIG_SOC_VCOREIII) += mscc subdir-$(CONFIG_MIPS_MALTA) += mti +subdir-$(CONFIG_MACH_EYEQ5) += mobileye subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni subdir-$(CONFIG_MACH_PIC32) += pic32 diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi new file mode 100644 index 0000000000000..78f5533a95c67 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi @@ -0,0 +1,292 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/ { + /* Fixed clock */ + pll_cpu: pll-cpu { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1500000000>; + }; + + pll_vdi: pll-vdi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1280000000>; + }; + + pll_per: pll-per { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <2000000000>; + }; + + pll_ddr0: pll-ddr0 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + + pll_ddr1: pll-ddr1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <1857210000>; + }; + +/* PLL_CPU derivatives */ + occ_cpu: occ-cpu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */ + compatible = "fixed-factor-clock"; + clocks = <&occ_cpu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cpc_clk: cpc-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core0_clk: core0-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core1_clk: core1-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core2_clk: core2-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + core3_clk: core3-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + cm_clk: cm-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + mem_clk: mem-clk { + compatible = "fixed-factor-clock"; + clocks = <&si_css0_ref_clk>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_isram: occ-isram { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + isram_clk: isram-clk { /* gate ClkRstGen_isram */ + compatible = "fixed-factor-clock"; + clocks = <&occ_isram>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_dbu: occ-dbu { + compatible = "fixed-factor-clock"; + clocks = <&pll_cpu>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + }; + si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ + compatible = "fixed-factor-clock"; + clocks = <&occ_dbu>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; +/* PLL_VDI derivatives */ + occ_vdi: occ-vdi { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + }; + vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ + compatible = "fixed-factor-clock"; + clocks = <&occ_vdi>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + occ_can_ser: occ-can-ser { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ + compatible = "fixed-factor-clock"; + clocks = <&occ_can_ser>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_ser_clk: i2c-ser-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_vdi>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + }; +/* PLL_PER derivatives */ + occ_periph: occ-periph { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <16>; + clock-mult = <1>; + }; + periph_clk: periph-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + can_clk: can-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + spi_clk: spi-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + uart_clk: uart-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + }; + i2c_clk: i2c-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "i2c_clk"; + }; + timer_clk: timer-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "timer_clk"; + }; + gpio_clk: gpio-clk { + compatible = "fixed-factor-clock"; + clocks = <&occ_periph>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "gpio_clk"; + }; + emmc_sys_clk: emmc-sys-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <10>; + clock-mult = <1>; + clock-output-names = "emmc_sys_clk"; + }; + ccf_ctrl_clk: ccf-ctrl-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <4>; + clock-mult = <1>; + clock-output-names = "ccf_ctrl_clk"; + }; + occ_mjpeg_core: occ-mjpeg-core { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <2>; + clock-mult = <1>; + clock-output-names = "occ_mjpeg_core"; + }; + hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "hsm_clk"; + }; + mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ + compatible = "fixed-factor-clock"; + clocks = <&occ_mjpeg_core>; + #clock-cells = <0>; + clock-div = <1>; + clock-mult = <1>; + clock-output-names = "mjpeg_core_clk"; + }; + fcmu_a_clk: fcmu-a-clk { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <20>; + clock-mult = <1>; + clock-output-names = "fcmu_a_clk"; + }; + occ_pci_sys: occ-pci-sys { + compatible = "fixed-factor-clock"; + clocks = <&pll_per>; + #clock-cells = <0>; + clock-div = <8>; + clock-mult = <1>; + clock-output-names = "occ_pci_sys"; + }; + pclk: pclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <250000000>; /* 250MHz */ + }; + tsu_clk: tsu-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; /* 125MHz */ + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi new file mode 100644 index 0000000000000..6cc5980e2fa17 --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* +* Copyright 2023 Mobileye Vision Technologies Ltd. +*/ + +#include + +#include "eyeq5-fixed-clocks.dtsi" + +/ { + #address-cells = <2>; + #size-cells = <2>; + cpus { + #address-cells = <1>; + #size-cells = <0>; + cpu@0 { + device_type = "cpu"; + compatible = "img,i6500"; + reg = <0>; + clocks = <&core0_clk>; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* These reserved memory regions are also defined in bootmanager + * for configuring inbound translation for BARS, don't change + * these without syncing with bootmanager + */ + shmem0_reserved: shmem@804000000 { + reg = <0x8 0x04000000 0x0 0x1000000>; + }; + shmem1_reserved: shmem@805000000 { + reg = <0x8 0x05000000 0x0 0x1000000>; + }; + pci0_msi_reserved: pci0-msi@806000000 { + reg = <0x8 0x06000000 0x0 0x100000>; + }; + pci1_msi_reserved: pci1-msi@806100000 { + reg = <0x8 0x06100000 0x0 0x100000>; + }; + + mini_coredump0_reserved: mini-coredump0@806200000 { + reg = <0x8 0x06200000 0x0 0x100000>; + }; + mhm_reserved_0: the-mhm-reserved-0@0 { + reg = <0x8 0x00000000 0x0 0x0000800>; + }; + }; + + aliases { + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + }; + + cpu_intc: interrupt-controller { + compatible = "mti,cpu-interrupt-controller"; + interrupt-controller; + #address-cells = <0>; + #interrupt-cells = <1>; + }; + + soc: soc { + #address-cells = <2>; + #size-cells = <2>; + ranges; + compatible = "simple-bus"; + + uart0: serial@800000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x800000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart1: serial@900000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0x900000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@a00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0 0xa00000 0x0 0x1000>; + reg-io-width = <4>; + interrupt-parent = <&gic>; + interrupts = ; + clocks = <&uart_clk>, <&occ_periph>; + clock-names = "uartclk", "apb_pclk"; + }; + + gic: interrupt-controller@140000 { + compatible = "mti,gic"; + reg = <0x0 0x140000 0x0 0x20000>; + interrupt-controller; + #interrupt-cells = <3>; + + /* + * Declare the interrupt-parent even though the mti,gic + * binding doesn't require it, such that the kernel can + * figure out that cpu_intc is the root interrupt + * controller & should be probed first. + */ + interrupt-parent = <&cpu_intc>; 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Reviewed-by: Jiaxun Yang Signed-off-by: Gregory CLEMENT --- arch/mips/boot/dts/mobileye/Makefile | 4 ++++ arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 23 ++++++++++++++++++++++ 2 files changed, 27 insertions(+) create mode 100644 arch/mips/boot/dts/mobileye/Makefile create mode 100644 arch/mips/boot/dts/mobileye/eyeq5-epm5.dts diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile new file mode 100644 index 0000000000000..01c01c3aad81d --- /dev/null +++ b/arch/mips/boot/dts/mobileye/Makefile @@ -0,0 +1,4 @@ +# SPDX-License-Identifier: GPL-2.0-only +# Copyright 2023 Mobileye Vision Technologies Ltd. + +dtb-$(CONFIG_MACH_EYEQ5) += eyeq5-epm5.dtb diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts new file mode 100644 index 0000000000000..6898b2d8267df --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Copyright 2023 Mobileye Vision Technologies Ltd. + */ + +/dts-v1/; + +#include "eyeq5.dtsi" + +/ { + compatible = "mobileye,eyeq5-epm5", "mobileye,eyeq5"; + model = "Mobile EyeQ5 MP5 Evaluation board"; + + chosen { + stdout-path = "serial2:115200n8"; + }; + + memory@0 { + device_type = "memory"; + reg = <0x0 0x40000000 0x0 0x02000000>, + <0x8 0x02000000 0x0 0x7E000000>; + }; +}; From patchwork Mon Feb 5 15:34:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196873 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp955460dyb; Mon, 5 Feb 2024 07:39:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtx7V2c26f/aLy688quK2CNU3po6HfYB3XTLZUe7ItxMx90ZkD5nit6niVa+Nl/aMQfqM/ X-Received: by 2002:a05:622a:800b:b0:42b:f6c1:dc1b with SMTP id jr11-20020a05622a800b00b0042bf6c1dc1bmr5350989qtb.31.1707147560483; Mon, 05 Feb 2024 07:39:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147560; cv=pass; d=google.com; s=arc-20160816; b=krlJr3khabRwvY03UfOfjLzWPM1jHd/tprnuBMAJ6FcrjIODITPLdoEfri897uhKV0 rmaGyCWtNl+X30VPoZV4YI7DJFzTcRbYHwXQ2Nd11B6A7PqMb9qDTJlmfiIH74xgG31/ AhqQBHMvTNFWtGE17gX+Uay6lmHWuJidHZgWGI6Fg3AH4ZHYhgfRjLDGZSo9a48AkJAS /wWw19ll+6D3+tfv4rnbTEbWqezHNkHIJfKG8bLEgvGTDLztBJLKqFJzhgE9Xozf5GKX BDHMM4TuA36XsW4RNytQnR+wGxzXjgAcNww2y/Em7k4oCJ4vHhlGK+37V4N9XbXK7o7t EO7A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=2Wk0pf2LEOjDnkraDRWIDqQ91OCoFBDydZfp83yb0pk=; fh=NebCFaDmkFckgtbuZACxCSz8z3ERNn/N+VUo94o46kc=; b=RzF2D1oOFbt62M/N6xtNcPm3gNQhTGZsLnjMtAytES3GMg9ig6BsYVYthgfSdLKrPU fjWTNbK9zkxSvF/tr1y/hQBX6cEkONOfptcxtuuQ2JyUUuiPtp/WV9h0iobJlYORxbMD f6aKfGzei4o9BBpKSx1gOpkjyejofBA0cDm1tyk34N7Re4G+0beR0izgxHkx7Vdkqfty T0qOhMwFrAtCK1ER2Xs7CxgoIZhHCcMcJN/tz54+adNsw6lfjJjumXELDfknbw7TXFT7 evMp3qBE++1Nj8UsBo2Y2rWju6ejxaWHhkEKgnUZUg1KuhcgPZoGrWQivHhee73MWFf6 73ew==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=jyaDsTDt; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52934-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52934-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCXl57iGw1XujtF7OsmkP7LVq3vTPduZ36bPQmHOhrbamJhX8BiMq4T8o+LqcEtOUGAcpOcEN/7OhIEUxobN/8ozYchO4A== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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d=bootlin.com; s=gm1; t=1707147317; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2Wk0pf2LEOjDnkraDRWIDqQ91OCoFBDydZfp83yb0pk=; b=jyaDsTDtaEcCfxi8hPZQTaUQj22/lvuqXaHaORad3+otn6iFysGdjUN3h+2TXaM3CzKtNs o3VIoFe5rEow+xgo5hvVBfyBpuz8zg1VjGp43FCFNSh+f8xB0E90PzNA8+YOH5A+24WsDN Dbuz5BptEGagbm10fvmNt46qEqtPiiqX1uYwY1fnvLk2Fm5S36jxqg4AFRGN6K6CR9uRMV Ju1+lYFkDZub/DFKDyCxw12j8BW16y8/lVztTBgNNsWGp60/a2TjzjVALY/2FWycyF9tLc DphsiySOxPYQ2Rv6eqqdxYaSsA22yA9rdOgW5Pk/lA9+N9kmpiHwAfcWxyDQ0A== From: Gregory CLEMENT To: Paul Burton , Thomas Bogendoerfer , linux-mips@vger.kernel.org, Jiaxun Yang , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Vladimir Kondratiev , Tawfik Bayouk , Alexandre Belloni , =?utf-8?q?Th=C3=A9o_Lebr?= =?utf-8?q?un?= , Thomas Petazzoni , Gregory CLEMENT Subject: [PATCH v7 12/14] MIPS: Share generic kernel code with other architecture Date: Mon, 5 Feb 2024 16:34:58 +0100 Message-ID: <20240205153503.574468-13-gregory.clement@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240205153503.574468-1-gregory.clement@bootlin.com> References: <20240205153503.574468-1-gregory.clement@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: gregory.clement@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1790073960512720786 X-GMAIL-MSGID: 1790073960512720786 Some architectures might seek to utilize a significant portion of the generic kernel code while maintaining independence from the generic kernel due to specific peculiarities. This patch allows for the reuse of core code, preventing unnecessary duplication. Suggested-by: Thomas Bogendoerfer Signed-off-by: Gregory CLEMENT Reviewed-by: Jiaxun Yang --- arch/mips/Kbuild | 1 + arch/mips/Kconfig | 3 +++ arch/mips/generic/Makefile | 6 +++--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/mips/Kbuild b/arch/mips/Kbuild index af2967bffb73d..d683993ed331c 100644 --- a/arch/mips/Kbuild +++ b/arch/mips/Kbuild @@ -17,6 +17,7 @@ obj- := $(platform-y) # mips object files # The object files are linked as core-y files would be linked +obj-y += generic/ obj-y += kernel/ obj-y += mm/ obj-y += net/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 797ae590ebdba..5549d26448941 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -109,6 +109,9 @@ config MIPS_FIXUP_BIGPHYS_ADDR config MIPS_GENERIC bool +config MACH_GENERIC_CORE + bool + config MACH_INGENIC bool select SYS_SUPPORTS_32BIT_KERNEL diff --git a/arch/mips/generic/Makefile b/arch/mips/generic/Makefile index e37a59bae0a62..56011d738441f 100644 --- a/arch/mips/generic/Makefile +++ b/arch/mips/generic/Makefile @@ -4,9 +4,9 @@ # Author: Paul Burton # -obj-y += init.o -obj-y += irq.o -obj-y += proc.o +obj-$(CONFIG_MACH_GENERIC_CORE) += init.o +obj-$(CONFIG_MACH_GENERIC_CORE) += irq.o +obj-$(CONFIG_MACH_GENERIC_CORE) += proc.o obj-$(CONFIG_YAMON_DT_SHIM) += yamon-dt.o obj-$(CONFIG_LEGACY_BOARD_SEAD3) += board-sead3.o From patchwork Mon Feb 5 15:34:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196874 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp955710dyb; Mon, 5 Feb 2024 07:39:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IHQ6+pgXrhdICWhIi2xvESvmFY3NN2VON9/WmN3im+bKp2X5nSEdggewKHNY7nBTmp8oGZq X-Received: by 2002:a05:622a:27c5:b0:42b:f0dc:1fcb with SMTP id gx5-20020a05622a27c500b0042bf0dc1fcbmr6811954qtb.1.1707147584648; Mon, 05 Feb 2024 07:39:44 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707147584; cv=pass; d=google.com; s=arc-20160816; b=prMElzHU1PAaNae7JR2BdFuPEz2XD+YE7iNOt+eYakpI7EkXb+6CcrRts1+qIByowE NNbtZbM+n3Mq6dJpn1o8BgGBAGAkDIS8SmKbF2u98j/3IWznscAA++og02lnO3h26lYh Z/P2y1k82FkwUWDM2bPugu1CWTGkeACju5j2/a7J+4Gs51B9naZZnNLNjKE82/q9fLun Z62GO/qu5xOumaYh2V8xWTj/DjgYujs/eTTHw2IJ+uhwUZI8ozhwCEjZCDguTC8Bn+5q zKDx/T7eeQkCjOMLhZhl33hU1chAk/sRXuOA2qPtMtb1+3/Ls1ChXSIkpoaQNjVydnLR S4LQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=bprVesusT+I/wfCto8f0Ql9854QTM+VSasVk49QQf8U=; fh=7Zkb0g32fDWzBKRmu30T2UO082NAT9O+NGUJqGnE6Fs=; b=vGKeTUA9q6hOJgf0mUXO/tldCiAVF4izuQzETfPYUK8lINHUug34FbPB489zYASfOe Zlc5bepPf8vbvoDk/BoTX2+qm1ersrs4dwZiLLQda2RhVzvetd5AlzT8gY8ee6ZYH1Pc jF83buEabFb9xaokcVJgcBR6iUQ2zPW6coOiDjYxUXTatgimpecrkQ5osChSCF3ADu7x WYhA87Unut249CmGvr2amDHzqOlVwANvI5P3ygVcpCGy4jCdFqeINworJ/mEPd9T8YV8 mI356qYIL4VDT5CnbiAGKEsWCycbzZ+dXdng9Qk3Pfx+V6Im+pK1rsi0yuHxRT+ZsQB7 9d7w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=mxUxEPqp; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-52936-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-52936-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCVRKVPQRxX9SpfXDoD/+PHBte34UtLEc33e3FfNxU4+5jVMaFbuOXukungLTWztUUM9yKJAdKlIQZP3al1tPAVuBRT0mA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Signed-off-by: Gregory CLEMENT Reviewed-by: Jiaxun Yang --- arch/mips/Kbuild.platforms | 1 + arch/mips/Kconfig | 54 ++++++++++++++ arch/mips/configs/eyeq5_defconfig | 108 ++++++++++++++++++++++++++++ arch/mips/mobileye/Makefile | 1 + arch/mips/mobileye/Platform | 16 +++++ arch/mips/mobileye/board-epm5.its.S | 24 +++++++ arch/mips/mobileye/vmlinux.its.S | 32 +++++++++ 7 files changed, 236 insertions(+) create mode 100644 arch/mips/configs/eyeq5_defconfig create mode 100644 arch/mips/mobileye/Makefile create mode 100644 arch/mips/mobileye/Platform create mode 100644 arch/mips/mobileye/board-epm5.its.S create mode 100644 arch/mips/mobileye/vmlinux.its.S diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms index a2311c4bce6a6..5c145b67d3bf4 100644 --- a/arch/mips/Kbuild.platforms +++ b/arch/mips/Kbuild.platforms @@ -17,6 +17,7 @@ platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/ platform-$(CONFIG_MACH_LOONGSON32) += loongson32/ platform-$(CONFIG_MACH_LOONGSON64) += loongson64/ platform-$(CONFIG_MIPS_MALTA) += mti-malta/ +platform-$(CONFIG_MACH_EYEQ5) += mobileye/ platform-$(CONFIG_MACH_NINTENDO64) += n64/ platform-$(CONFIG_PIC32MZDA) += pic32/ platform-$(CONFIG_RALINK) += ralink/ diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 5549d26448941..a40eb9ecb50d5 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -569,6 +569,60 @@ config MACH_PIC32 Microchip PIC32 is a family of general-purpose 32 bit MIPS core microcontrollers. +config MACH_EYEQ5 + bool "Mobileye EyeQ5 SoC" + select MACH_GENERIC_CORE + select ARM_AMBA + select PHYSICAL_START_BOOL + select ARCH_SPARSEMEM_DEFAULT if 64BIT + select BOOT_RAW + select BUILTIN_DTB + select CEVT_R4K + select CLKSRC_MIPS_GIC + select COMMON_CLK + select CPU_MIPSR2_IRQ_EI + select CPU_MIPSR2_IRQ_VI + select CSRC_R4K + select DMA_NONCOHERENT + select HAVE_PCI + select IRQ_MIPS_CPU + select MIPS_AUTO_PFN_OFFSET + select MIPS_CPU_SCACHE + select MIPS_GIC + select MIPS_L1_CACHE_SHIFT_7 + select PCI_DRIVERS_GENERIC + select SMP_UP if SMP + select SWAP_IO_SPACE + select SYS_HAS_CPU_MIPS64_R6 + select SYS_SUPPORTS_64BIT_KERNEL + select SYS_SUPPORTS_HIGHMEM + select SYS_SUPPORTS_LITTLE_ENDIAN + select SYS_SUPPORTS_MIPS_CPS + select SYS_SUPPORTS_RELOCATABLE + select SYS_SUPPORTS_ZBOOT + select UHI_BOOT + select USB_EHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_EHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_OHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USB_UHCI_BIG_ENDIAN_DESC if CPU_BIG_ENDIAN + select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN + select USE_OF + help + Select this to build a kernel supporting EyeQ5 SoC from Mobileye. + + bool + +config FIT_IMAGE_FDT_EPM5 + bool "Include FDT for Mobileye EyeQ5 development platforms" + depends on MACH_EYEQ5 + default n + help + Enable this to include the FDT for the EyeQ5 development platforms + from Mobileye in the FIT kernel image. + This requires u-boot on the platform. + + config MACH_NINTENDO64 bool "Nintendo 64 console" select CEVT_R4K diff --git a/arch/mips/configs/eyeq5_defconfig b/arch/mips/configs/eyeq5_defconfig new file mode 100644 index 0000000000000..c35c29a4d4795 --- /dev/null +++ b/arch/mips/configs/eyeq5_defconfig @@ -0,0 +1,108 @@ +CONFIG_SYSVIPC=y +CONFIG_NO_HZ_IDLE=y +CONFIG_HIGH_RES_TIMERS=y +CONFIG_BPF_SYSCALL=y +CONFIG_TASKSTATS=y +CONFIG_IKCONFIG=y +CONFIG_IKCONFIG_PROC=y +CONFIG_MEMCG=y +CONFIG_BLK_CGROUP=y +CONFIG_CFS_BANDWIDTH=y +CONFIG_RT_GROUP_SCHED=y +CONFIG_CGROUP_PIDS=y +CONFIG_CGROUP_FREEZER=y +CONFIG_CPUSETS=y +CONFIG_CGROUP_DEVICE=y +CONFIG_CGROUP_CPUACCT=y +CONFIG_NAMESPACES=y +CONFIG_USER_NS=y +CONFIG_SCHED_AUTOGROUP=y +CONFIG_BLK_DEV_INITRD=y +CONFIG_EXPERT=y +CONFIG_MACH_EYEQ5=y +CONFIG_FIT_IMAGE_FDT_EPM5=y +CONFIG_PAGE_SIZE_16KB=y +CONFIG_MIPS_CPS=y +CONFIG_CPU_HAS_MSA=y +CONFIG_NR_CPUS=16 +CONFIG_MIPS_RAW_APPENDED_DTB=y +CONFIG_JUMP_LABEL=y +CONFIG_COMPAT_32BIT_TIME=y +CONFIG_MODULES=y +CONFIG_MODULE_UNLOAD=y +CONFIG_TRIM_UNUSED_KSYMS=y +# CONFIG_COMPAT_BRK is not set +CONFIG_SPARSEMEM_MANUAL=y +CONFIG_USERFAULTFD=y +CONFIG_NET=y +CONFIG_PACKET=y +CONFIG_UNIX=y +CONFIG_NET_KEY=y +CONFIG_INET=y +CONFIG_IP_PNP=y +CONFIG_IP_PNP_DHCP=y +CONFIG_NETFILTER=y +CONFIG_CAN=y +CONFIG_PCI=y +CONFIG_PCI_MSI=y +CONFIG_PCI_DEBUG=y +CONFIG_PCI_ENDPOINT=y +CONFIG_DEVTMPFS=y +CONFIG_DEVTMPFS_MOUNT=y +CONFIG_CONNECTOR=y +CONFIG_MTD=y +CONFIG_MTD_UBI=y +CONFIG_MTD_UBI_BLOCK=y +CONFIG_SCSI=y +CONFIG_NETDEVICES=y +CONFIG_MACVLAN=y +CONFIG_IPVLAN=y +CONFIG_MACB=y +CONFIG_MARVELL_PHY=y +CONFIG_MICREL_PHY=y +CONFIG_CAN_M_CAN=y +CONFIG_SERIAL_AMBA_PL011=y +CONFIG_SERIAL_AMBA_PL011_CONSOLE=y +CONFIG_HW_RANDOM=y +# CONFIG_PTP_1588_CLOCK is not set +CONFIG_PINCTRL=y +CONFIG_MFD_SYSCON=y +CONFIG_HID_A4TECH=y +CONFIG_HID_BELKIN=y +CONFIG_HID_CHERRY=y +CONFIG_HID_CYPRESS=y +CONFIG_HID_EZKEY=y +CONFIG_HID_ITE=y +CONFIG_HID_KENSINGTON=y +CONFIG_HID_REDRAGON=y +CONFIG_HID_MICROSOFT=y +CONFIG_HID_MONTEREY=y +CONFIG_MMC=y +CONFIG_MMC_SDHCI=y +# CONFIG_IOMMU_SUPPORT is not set +CONFIG_RESET_CONTROLLER=y +# CONFIG_NVMEM is not set +CONFIG_EXT4_FS=y +CONFIG_EXT4_FS_POSIX_ACL=y +CONFIG_EXT4_FS_SECURITY=y +CONFIG_FS_ENCRYPTION=y +CONFIG_FUSE_FS=y +CONFIG_CUSE=y +CONFIG_MSDOS_FS=y +CONFIG_VFAT_FS=y +CONFIG_TMPFS=y +CONFIG_TMPFS_POSIX_ACL=y +CONFIG_UBIFS_FS=y +CONFIG_NFS_FS=y +CONFIG_NFS_V3_ACL=y +CONFIG_NFS_V4=y +CONFIG_NFS_V4_1=y +CONFIG_NFS_V4_2=y +CONFIG_ROOT_NFS=y +CONFIG_CRYPTO_CRC32_MIPS=y +CONFIG_FRAME_WARN=1024 +CONFIG_DEBUG_FS=y +# CONFIG_RCU_TRACE is not set +# CONFIG_FTRACE is not set +CONFIG_CMDLINE_BOOL=y +CONFIG_CMDLINE="earlycon" diff --git a/arch/mips/mobileye/Makefile b/arch/mips/mobileye/Makefile new file mode 100644 index 0000000000000..315c06b689cfb --- /dev/null +++ b/arch/mips/mobileye/Makefile @@ -0,0 +1 @@ +# SPDX-License-Identifier: GPL-2.0-or-later diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform new file mode 100644 index 0000000000000..43b6f4644592f --- /dev/null +++ b/arch/mips/mobileye/Platform @@ -0,0 +1,16 @@ +# +# Copyright (C) 2016 Imagination Technologies +# Author: Paul Burton +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the +# Free Software Foundation; either version 2 of the License, or (at your +# option) any later version. +# + +load-$(CONFIG_MACH_EYEQ5) = 0xa800000808000000 +all-$(CONFIG_MACH_EYEQ5) += vmlinux.gz.itb + +its-y := vmlinux.its.S +its-$(CONFIG_FIT_IMAGE_FDT_EPM5) += board-epm5.its.S + diff --git a/arch/mips/mobileye/board-epm5.its.S b/arch/mips/mobileye/board-epm5.its.S new file mode 100644 index 0000000000000..08e8c4f183d63 --- /dev/null +++ b/arch/mips/mobileye/board-epm5.its.S @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */ +/ { + images { + fdt-mobileye-epm5 { + description = "Mobileeye MP5 Device Tree"; + data = /incbin/("boot/dts/mobileye/eyeq5-epm5.dtb"); + type = "flat_dt"; + arch = "mips"; + compression = "none"; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-1"; + conf-1 { + description = "Mobileye EPM5 Linux kernel"; + kernel = "kernel"; + fdt = "fdt-mobileye-epm5"; + }; + }; +}; diff --git a/arch/mips/mobileye/vmlinux.its.S b/arch/mips/mobileye/vmlinux.its.S new file mode 100644 index 0000000000000..3e254676540f4 --- /dev/null +++ b/arch/mips/mobileye/vmlinux.its.S @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/dts-v1/; + +/ { + description = KERNEL_NAME; + #address-cells = ; + + images { + kernel { + description = KERNEL_NAME; + data = /incbin/(VMLINUX_BINARY); + type = "kernel"; + arch = "mips"; + os = "linux"; + compression = VMLINUX_COMPRESSION; + load = /bits/ ADDR_BITS ; + entry = /bits/ ADDR_BITS ; + hash { + algo = "sha1"; + }; + }; + }; + + configurations { + default = "conf-default"; + + conf-default { + description = "Generic Linux kernel"; + kernel = "kernel"; + }; + }; +}; From patchwork Mon Feb 5 15:35:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Gregory CLEMENT X-Patchwork-Id: 196913 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp974388dyb; Mon, 5 Feb 2024 08:08:25 -0800 (PST) X-Google-Smtp-Source: AGHT+IEgz3VkQWRVCBWVoZbW6wjBRPUndMHjOF7mEUx4QcS9KlVrN4lXsVtMBBOJ3amRAG2ZVsLe X-Received: by 2002:a05:6a20:93a7:b0:19e:4e58:5026 with SMTP id x39-20020a056a2093a700b0019e4e585026mr12249692pzh.4.1707149305470; Mon, 05 Feb 2024 08:08:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1707149305; cv=pass; d=google.com; s=arc-20160816; b=KqkuvJ8XMj2FoQX0SHm3vSf5qX2L2O7Fmviv1hTnCSTs6vnnFzKU0PX9N6RpBGnwSe lyK38NAxLhdtD6lVxMMmx6Pn3WOafQGsgmn/MR7tbdf85paeL9LQ/bO3sq+Arffi0N8k xK71CVz+5TKh/zmUWkQFCBX2DQYPTb7xlQUsKzxquzLLdmcHSZC+Go5AMgiygxQGLmNg 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Signed-off-by: Vladimir Kondratiev Signed-off-by: Théo Lebrun Signed-off-by: Gregory CLEMENT --- MAINTAINERS | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index b3444c8c6512e..b18f328ee8ee7 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14546,6 +14546,18 @@ W: https://linuxtv.org Q: http://patchwork.linuxtv.org/project/linux-media/list/ F: drivers/media/dvb-frontends/mn88473* +MOBILEYE MIPS SOCS +M: Vladimir Kondratiev +M: Gregory CLEMENT +M: Théo Lebrun +L: linux-mips@vger.kernel.org +S: Maintained +F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: arch/mips/boot/dts/mobileye/ +F: arch/mips/configs/eyeq5_defconfig +F: arch/mips/mobileye/board-epm5.its.S +F: include/dt-bindings/soc/mobileye,eyeq5.h + MODULE SUPPORT M: Luis Chamberlain L: linux-modules@vger.kernel.org