From patchwork Tue Nov 15 15:45:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 20444 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2803532wru; Tue, 15 Nov 2022 07:51:22 -0800 (PST) X-Google-Smtp-Source: AA0mqf7uTj6O3n4Y/pbNIQlxZWaVvOCUujDC2Vzjzj3yrFLorkvkAIb5Laj+cCAi1VqcRlMM/2Zv X-Received: by 2002:a17:902:b901:b0:172:b0f3:527f with SMTP id bf1-20020a170902b90100b00172b0f3527fmr4875472plb.40.1668527482061; Tue, 15 Nov 2022 07:51:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668527482; cv=none; d=google.com; s=arc-20160816; b=Vc9r2S0JneSz3FigplfYmC0orLlt9mT8XzuoQap53/ZpwnolyQUDQJuoIG2Y0yg17+ fmOFdNqUXdV4nRBtFZrT31Kbsex9dxMjIsIAIobVi5vfFxTPprmMPrWs23FT59hhJDsC 9F+FsbjC6JtGH6OTP3XcuJcK99/9otoNoJUGttR4N7IL4J0avyYoaSKZBLp1y6njjr/t AcIb8fkG+pbcgSspetEXbQSmQxgBsYXyhmwyPX19yroBMLISb3BwVMwMr/6Fvrsd+hEn ITnBHWc1Z+Vyf4q87W6nlVrRYioTCuKw/pAknSessGE8rX3+/UzQXutMOp2yq430xS0H daeA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=3RvR159E4JvV7WBAq7vVaYd+t2PF5FI05rQn9eJjPps=; b=gKaqHjd9zoOevpBCNUGAAztAPKJeWpayLgqyRcvFNhwnT1HmzEWTfJmhodoCkYX69a BG7dMO4JbydtY/FB3jj0PytL/+9JTS1G/nuKjslqDNUnPxwUbsNLMacd+J0XcpYl1v0d zm1wmOI2lsFnOlCqRdXJ9zBH75cg6Uv8y2bjT7JZ4XR7chopT1MF35joVncCwqs4Jk3w 2P8lQUFsajUuq9ZjJ2GksoY83AP1N6BJ8037/poAh09wtsJn0uOp1BzEsdkpuG6CInVe GrCLxeL5UoOObJM+vdfP3GMHs8RCBKHaXOY8pHSJM+vkG122UkmUpAJ1z6aFtvUHvua0 +2Qw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=mw7bUZK8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id h17-20020a62b411000000b00540d5753591si11086039pfn.299.2022.11.15.07.51.08; Tue, 15 Nov 2022 07:51:22 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=mw7bUZK8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229613AbiKOPqT (ORCPT + 99 others); Tue, 15 Nov 2022 10:46:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43656 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238410AbiKOPqF (ORCPT ); Tue, 15 Nov 2022 10:46:05 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FF872CCAD; Tue, 15 Nov 2022 07:46:01 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id B92D56602A2D; Tue, 15 Nov 2022 15:45:59 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668527160; bh=diKrpCWyppPm84t0hqsBG/0u3xN/nvNnHoXQJMzv5rY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mw7bUZK8HJNS7KCvBxQuJJGEmtpPWgbcat2Liv3YGr9bV439fYCkzUBUcQalCVzHL WlAzba/TUuDggKpTIEjO3otW4yNKUcdLM6BNQMNHyRQWmVYSLZgawSIZaxCh59b3p8 0vL1rROwZV57nrIxAUpQq9UjZ5zemHXrBU7Tf7uQSFvjzANScJkxPwjvtWwMFjHJwg dTvwECTvwIOMIK9AqSw71NSNLQzmrU4x64NvOoghmE2ed0gDz5pBg9wINZyMosghJG ZaZzjiGbmV7NAk3h80Ziz7oKLvpxDJO5rt3jYZXDmm0V9YylKU/hJqv6Wplsvt5PZZ sGFG1bgB1TEQg== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com, Krzysztof Kozlowski Subject: [PATCH v3 1/2] dt-bindings: soc: qcom: Add bindings for Qualcomm Ramp Controller Date: Tue, 15 Nov 2022 16:45:54 +0100 Message-Id: <20221115154555.324437-2-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221115154555.324437-1-angelogioacchino.delregno@collabora.com> References: <20221115154555.324437-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749577873228373028?= X-GMAIL-MSGID: =?utf-8?q?1749577873228373028?= Document the Qualcomm Ramp Controller, found on various legacy Qualcomm SoCs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- .../qcom/qcom,msm8976-ramp-controller.yaml | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml new file mode 100644 index 000000000000..aae9cf7b8caf --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,msm8976-ramp-controller.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,msm8976-ramp-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Ramp Controller + +maintainers: + - AngeloGioacchino Del Regno + +description: + The Ramp Controller is used to program the sequence ID for pulse + swallowing, enable sequences and link Sequence IDs (SIDs) for the + CPU cores on some Qualcomm SoCs. + +properties: + compatible: + enum: + - qcom,msm8976-ramp-controller + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cpu-power-controller@b014000 { + compatible = "qcom,msm8976-ramp-controller"; + reg = <0x0b014000 0x68>; + }; From patchwork Tue Nov 15 15:45:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: AngeloGioacchino Del Regno X-Patchwork-Id: 20445 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2803575wru; Tue, 15 Nov 2022 07:51:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf7b7orNPtPRltfvG+RkgAYTjkiD+n6c1GInRzqZGiNKfexev/TPtWpLVTvk1Q/LWY8jig6x X-Received: by 2002:a17:903:24a:b0:176:a0cc:5eff with SMTP id j10-20020a170903024a00b00176a0cc5effmr4750701plh.128.1668527487000; Tue, 15 Nov 2022 07:51:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668527486; cv=none; d=google.com; s=arc-20160816; b=jeFJzeX/n645b+sB83oT/sSo6o+sPvexxWB5ROwCOuw+408FQMGjNJxgu9oweUViCm lNzwLSwHpeNIjpa4+OIyX1s38PMvHdLBi5h37/qW/oblQi15ssgvzN6a42WOH6Nx0993 2uN7DTe3nJUnBslGNiS6JiFz7KJJrNMV4K7ACUIVgjT/OCbf6UGSLthJS4GaTWPV75ku DTAWFe+3xZnbzgqj3l20okHbD3/wqzTv0AxxmytQw5cbRpfcP+TMU87mQWXFOjq78Xac cyfzg/h1QD5dOFYyl/0GY7+8vjrF5NijCURaXS4ht0JfZHm5aXfYptaRCRfFl2ySPbc6 w8RA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=o+Zv6Z1gd33a7qO3KbWlw+iM1Gzo4gy3KqAtJZLPfSY=; b=RCx2WFXdd6f48I6te/PD94qT/0+CkVANcKbpyBfB2UFvwLvhkhHB1kIdiC92yCCaJd fdc+HbB2P41VqFf8wpFH/GWjr08C26TWywJLRquXQzY4dP8WEdzIQfF0S2l2POTMc+7T 1vtxn5R6bRcdku0hu8bgTTjkCu0meBUmhwEyRKxBjl3WwMf/qLEcJ/1u2GNo8qo7Ywkr s4prLrTgqqfdgrw/Ha0sqfJRZAhzDcbKwI6hXn9V7umiqhp0iY9+Crm1M3MeC2gRLm5t NAL2KLYZ/cwoOnDM/0ooGtDHZVNIV+tJj9eqpnCi+c/cPWPXT0IZXAF0uRJIkrEy/ga4 0YeQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ODYwKbcu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id f18-20020a170902ce9200b0017a0e8713cesi14404920plg.452.2022.11.15.07.51.13; Tue, 15 Nov 2022 07:51:26 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@collabora.com header.s=mail header.b=ODYwKbcu; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=collabora.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229645AbiKOPqX (ORCPT + 99 others); Tue, 15 Nov 2022 10:46:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238358AbiKOPqF (ORCPT ); Tue, 15 Nov 2022 10:46:05 -0500 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A6682CC88; Tue, 15 Nov 2022 07:46:02 -0800 (PST) Received: from IcarusMOD.eternityproject.eu (2-237-20-237.ip236.fastwebnet.it [2.237.20.237]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: kholk11) by madras.collabora.co.uk (Postfix) with ESMTPSA id 7C8F66602A3E; Tue, 15 Nov 2022 15:46:00 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1668527161; bh=l/FvjL31dvpXnqHGpKT2Du5mUQN7XFBrQqHoBWmt0B8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ODYwKbcu4TstTAqoHSxKUDGH/bkMJRD/k8hRP3vhXbodnU5azAHwDmVNjp+oTZTj6 nkBHERPGybGFLzMCMVsGwrADm0s7rPj+nfbqWtSX7DReKsfZ4K+rgX/bPi9i/NCb8Y cfW5avAkoDTOcmki2M91XH9L1PJJ0hizhh5l+kMZ1oWlfGEp/S98jqvpK2Di04ihfD ILaWTtB+XNw23/vF2k0r0TZhcjTpw+l0oUi9sWIJJUpVCgjp0vLWk8z7PjEvyHHe2X awAayQOcBytdHbr8vuMtq+Yp55a7gF/+auXnq9Xggkt35B3/GTyDFvF+8CZcKdsBm8 tEkXRolGHmO/Q== From: AngeloGioacchino Del Regno To: agross@kernel.org Cc: andersson@kernel.org, konrad.dybcio@somainline.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, angelogioacchino.delregno@collabora.com, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, marijn.suijten@somainline.org, kernel@collabora.com Subject: [PATCH v3 2/2] soc: qcom: Add Qualcomm Ramp Controller driver Date: Tue, 15 Nov 2022 16:45:55 +0100 Message-Id: <20221115154555.324437-3-angelogioacchino.delregno@collabora.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221115154555.324437-1-angelogioacchino.delregno@collabora.com> References: <20221115154555.324437-1-angelogioacchino.delregno@collabora.com> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749577878534694686?= X-GMAIL-MSGID: =?utf-8?q?1749577878534694686?= The Ramp Controller is used to program the sequence ID for pulse swallowing, enable sequence and linking sequence IDs for the CPU cores on some Qualcomm SoCs. Signed-off-by: AngeloGioacchino Del Regno --- drivers/soc/qcom/Kconfig | 9 + drivers/soc/qcom/Makefile | 1 + drivers/soc/qcom/ramp_controller.c | 331 +++++++++++++++++++++++++++++ 3 files changed, 341 insertions(+) create mode 100644 drivers/soc/qcom/ramp_controller.c diff --git a/drivers/soc/qcom/Kconfig b/drivers/soc/qcom/Kconfig index 024e420f1bb7..d174183a26f7 100644 --- a/drivers/soc/qcom/Kconfig +++ b/drivers/soc/qcom/Kconfig @@ -95,6 +95,15 @@ config QCOM_QMI_HELPERS tristate depends on NET +config QCOM_RAMP_CTRL + tristate "Qualcomm Ramp Controller driver" + depends on ARCH_QCOM || COMPILE_TEST + help + The Ramp Controller is used to program the sequence ID for pulse + swallowing, enable sequence and link sequence IDs for the CPU + cores on some Qualcomm SoCs. + Say y here to enable support for the ramp controller. + config QCOM_RMTFS_MEM tristate "Qualcomm Remote Filesystem memory driver" depends on ARCH_QCOM diff --git a/drivers/soc/qcom/Makefile b/drivers/soc/qcom/Makefile index d66604aff2b0..6e02333c4080 100644 --- a/drivers/soc/qcom/Makefile +++ b/drivers/soc/qcom/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_QCOM_OCMEM) += ocmem.o obj-$(CONFIG_QCOM_PDR_HELPERS) += pdr_interface.o obj-$(CONFIG_QCOM_QMI_HELPERS) += qmi_helpers.o qmi_helpers-y += qmi_encdec.o qmi_interface.o +obj-$(CONFIG_QCOM_RAMP_CTRL) += ramp_controller.o obj-$(CONFIG_QCOM_RMTFS_MEM) += rmtfs_mem.o obj-$(CONFIG_QCOM_RPMH) += qcom_rpmh.o qcom_rpmh-y += rpmh-rsc.o diff --git a/drivers/soc/qcom/ramp_controller.c b/drivers/soc/qcom/ramp_controller.c new file mode 100644 index 000000000000..b403493f3541 --- /dev/null +++ b/drivers/soc/qcom/ramp_controller.c @@ -0,0 +1,331 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Qualcomm Ramp Controller driver + * Copyright (c) 2022, AngeloGioacchino Del Regno + * + */ + +#include +#include +#include +#include +#include +#include +#include + +#define RC_UPDATE_EN BIT(0) +#define RC_ROOT_EN BIT(1) + +#define RC_REG_CFG_UPDATE 0x60 +#define RC_CFG_UPDATE_EN BIT(8) +#define RC_CFG_ACK GENMASK(31, 16) + +#define RC_DCVS_CFG_SID 2 +#define RC_LINK_SID 3 +#define RC_LMH_SID 6 +#define RC_DFS_SID 14 + +#define RC_UPDATE_TIMEOUT_US 500 + +/** + * struct qcom_ramp_controller_desc - SoC specific parameters + * @cfg_dfs_sid: Dynamic Frequency Scaling SID configuration + * @cfg_link_sid: Link SID configuration + * @cfg_lmh_sid: Limits Management hardware SID configuration + * @cfg_ramp_pre_en: Ramp Controller pre-enable sequence + * @cfg_ramp_en: Ramp Controller enable sequence + * @cfg_ramp_post_en: Ramp Controller post-enable sequence + * @cfg_ramp_dis: Ramp Controller disable sequence + * @cmd_reg: Command register offset + * @num_dfs_sids: Number of DFS SIDs (max 8) + * @num_link_sids: Number of Link SIDs (max 3) + * @num_lmh_sids: Number of LMh SIDs (max 8) + */ +struct qcom_ramp_controller_desc { + const struct reg_sequence *cfg_dfs_sid; + const struct reg_sequence *cfg_link_sid; + const struct reg_sequence *cfg_lmh_sid; + const struct reg_sequence *cfg_ramp_pre_en; + const struct reg_sequence *cfg_ramp_en; + const struct reg_sequence *cfg_ramp_post_en; + const struct reg_sequence *cfg_ramp_dis; + u8 cmd_reg; + u8 num_dfs_sids; + u8 num_link_sids; + u8 num_lmh_sids; +}; + +/** + * struct qcom_ramp_controller - Main driver structure + * @regmap: Regmap handle + * @desc: SoC specific parameters + */ +struct qcom_ramp_controller { + struct regmap *regmap; + const struct qcom_ramp_controller_desc *desc; +}; + +/** + * rc_wait_for_update() - Wait for Ramp Controller root update + * @qrc: Main driver structure + * + * Return: Zero for success or negative number for failure + */ +static int rc_wait_for_update(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + struct regmap *r = qrc->regmap; + u32 val; + int ret; + + ret = regmap_set_bits(r, d->cmd_reg, RC_ROOT_EN); + if (ret) + return ret; + + return regmap_read_poll_timeout(r, d->cmd_reg, val, !(val & RC_UPDATE_EN), + 1, RC_UPDATE_TIMEOUT_US); +} + +/** + * rc_set_cfg_update() - Ramp Controller configuration update + * @qrc: Main driver structure + * @ce: Configuration entry to update + * + * Return: Zero for success or negative number for failure + */ +static int rc_set_cfg_update(struct qcom_ramp_controller *qrc, u8 ce) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + struct regmap *r = qrc->regmap; + u32 ack, val; + int ret; + + /* The ack bit is between bits 16-31 of RC_REG_CFG_UPDATE */ + ack = FIELD_PREP(RC_CFG_ACK, BIT(ce)); + + /* Write the configuration type first... */ + ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, ce); + if (ret) + return ret; + + /* ...and after that, enable the update bit to sync the changes */ + ret = regmap_set_bits(r, d->cmd_reg + RC_REG_CFG_UPDATE, RC_CFG_UPDATE_EN); + if (ret) + return ret; + + /* Wait for the changes to go through */ + ret = regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, val, + val & ack, 1, RC_UPDATE_TIMEOUT_US); + if (ret) + return ret; + + /* + * Configuration update success! The CFG_UPDATE register will not be + * cleared automatically upon applying the configuration, so we have + * to do that manually in order to leave the ramp controller in a + * predictable and clean state. + */ + ret = regmap_write(r, d->cmd_reg + RC_REG_CFG_UPDATE, 0); + if (ret) + return ret; + + /* Wait for the update bit cleared ack */ + return regmap_read_poll_timeout(r, d->cmd_reg + RC_REG_CFG_UPDATE, + val, !(val & RC_CFG_ACK), 1, + RC_UPDATE_TIMEOUT_US); +} + +/** + * rc_write_cfg - Send configuration sequence + * @qrc: Main driver structure + * @seq: Register sequence to send before asking for update + * @ce: Configuration SID + * @nsids: Total number of SIDs + * + * Returns: Zero for success or negative number for error + */ +static int rc_write_cfg(struct qcom_ramp_controller *qrc, + const struct reg_sequence *seq, + u16 ce, u8 nsids) +{ + int ret; + u8 i; + + /* Check if, and wait until the ramp controller is ready */ + ret = rc_wait_for_update(qrc); + if (ret) + return ret; + + /* Write the sequence */ + ret = regmap_multi_reg_write(qrc->regmap, seq, nsids); + if (ret) + return ret; + + /* Pull the trigger: do config update starting from the last sid */ + for (i = 0; i < nsids; i++) { + ret = rc_set_cfg_update(qrc, (u8)ce - i); + if (ret) + return ret; + } + + return 0; +} + +/** + * rc_ramp_ctrl_enable() - Enable Ramp up/down Control + * @qrc: Main driver structure + * + * Return: Zero for success or negative number for error + */ +static int rc_ramp_ctrl_enable(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + int ret; + + ret = rc_write_cfg(qrc, d->cfg_ramp_pre_en, RC_DCVS_CFG_SID, 1); + if (ret) + return ret; + + ret = rc_write_cfg(qrc, d->cfg_ramp_en, RC_DCVS_CFG_SID, 1); + if (ret) + return ret; + + return rc_write_cfg(qrc, d->cfg_ramp_post_en, RC_DCVS_CFG_SID, 1); +} + +/** + * qcom_ramp_controller_start() - Initialize and start the ramp controller + * @qrc: Main driver structure + * + * The Ramp Controller needs to be initialized by programming the relevant + * registers with SoC-specific configuration: once programming is done, + * the hardware will take care of the rest (no further handling required). + * + * Return: Zero for success or negative number for error + */ +static int qcom_ramp_controller_start(struct qcom_ramp_controller *qrc) +{ + const struct qcom_ramp_controller_desc *d = qrc->desc; + int ret; + + /* Program LMH, DFS, Link SIDs */ + ret = rc_write_cfg(qrc, d->cfg_lmh_sid, RC_LMH_SID, d->num_lmh_sids); + if (ret) + return ret; + + ret = rc_write_cfg(qrc, d->cfg_dfs_sid, RC_DFS_SID, d->num_dfs_sids); + if (ret) + return ret; + + ret = rc_write_cfg(qrc, d->cfg_link_sid, RC_LINK_SID, d->num_link_sids); + if (ret) + return ret; + + /* Everything is ready! Enable the ramp up/down control */ + return rc_ramp_ctrl_enable(qrc); +} + +static const struct regmap_config qrc_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .max_register = 0x68, + .fast_io = true, +}; + +static const struct qcom_ramp_controller_desc msm8976_rc_cfg = { + .cfg_dfs_sid = (const struct reg_sequence[]) { + { 0x10, 0xfefebff7 }, + { 0x14, 0xfdff7fef }, + { 0x18, 0xfbffdefb }, + { 0x1c, 0xb69b5555 }, + { 0x20, 0x24929249 }, + { 0x24, 0x49241112 }, + { 0x28, 0x11112111 }, + { 0x2c, 0x8102 }, + }, + .cfg_link_sid = (const struct reg_sequence[]) { + { 0x40, 0xfc987 }, + }, + .cfg_lmh_sid = (const struct reg_sequence[]) { + { 0x30, 0x77706db }, + { 0x34, 0x5550249 }, + { 0x38, 0x111 }, + }, + .cfg_ramp_pre_en = (const struct reg_sequence[]) { + { 0x50, 0x800 }, + }, + .cfg_ramp_en = (const struct reg_sequence[]) { + { 0x50, 0xc00 }, + }, + .cfg_ramp_post_en = (const struct reg_sequence[]) { + { 0x50, 0x400 }, + }, + .cfg_ramp_dis = (const struct reg_sequence[]) { + { 0x50, 0x0 }, + }, + .cmd_reg = 0x0, + + .num_dfs_sids = 8, + .num_lmh_sids = 3, + .num_link_sids = 1, +}; + +static int qcom_ramp_controller_probe(struct platform_device *pdev) +{ + struct qcom_ramp_controller *qrc; + void __iomem *base; + + base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + qrc = devm_kmalloc(&pdev->dev, sizeof(*qrc), GFP_KERNEL); + if (!qrc) + return -ENOMEM; + + qrc->desc = device_get_match_data(&pdev->dev); + if (!qrc) + return -EINVAL; + + qrc->regmap = devm_regmap_init_mmio(&pdev->dev, base, &qrc_regmap_config); + if (IS_ERR(qrc->regmap)) + return PTR_ERR(qrc->regmap); + + platform_set_drvdata(pdev, qrc); + + return qcom_ramp_controller_start(qrc); +} + +static int qcom_ramp_controller_remove(struct platform_device *pdev) +{ + struct qcom_ramp_controller *qrc = platform_get_drvdata(pdev); + + return rc_write_cfg(qrc, qrc->desc->cfg_ramp_dis, RC_DCVS_CFG_SID, 1); +} + +static const struct of_device_id qcom_ramp_controller_match_table[] = { + { .compatible = "qcom,msm8976-ramp-controller", .data = &msm8976_rc_cfg }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, qcom_ramp_controller_match_table); + +static struct platform_driver qcom_ramp_controller_driver = { + .driver = { + .name = "qcom-ramp-controller", + .of_match_table = qcom_ramp_controller_match_table, + .suppress_bind_attrs = true, + }, + .probe = qcom_ramp_controller_probe, + .remove = qcom_ramp_controller_remove, +}; + +static int __init qcom_ramp_controller_init(void) +{ + return platform_driver_register(&qcom_ramp_controller_driver); +} +arch_initcall(qcom_ramp_controller_init); + +MODULE_AUTHOR("AngeloGioacchino Del Regno "); +MODULE_DESCRIPTION("Qualcomm Ramp Controller driver"); +MODULE_LICENSE("GPL");