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[2620:137:e000::1:20]) by mx.google.com with ESMTP id sd31-20020a1709076e1f00b007ae1052554esi11423886ejc.898.2022.11.15.07.32.05; Tue, 15 Nov 2022 07:32:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XeD7h1D8; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238028AbiKOP1s (ORCPT + 99 others); Tue, 15 Nov 2022 10:27:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237742AbiKOP1n (ORCPT ); Tue, 15 Nov 2022 10:27:43 -0500 Received: from mail-ej1-x633.google.com (mail-ej1-x633.google.com [IPv6:2a00:1450:4864:20::633]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 243E42C109 for ; Tue, 15 Nov 2022 07:27:40 -0800 (PST) Received: by mail-ej1-x633.google.com with SMTP id ud5so36948287ejc.4 for ; Tue, 15 Nov 2022 07:27:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/OnIF5KJq38ydF7gLxLfsf0iN2iW7kEJTrwDz5/qCW8=; b=XeD7h1D85c6PELOSUkCRH42zXo6QrloEq7je/ihrbaWxuZGUSugvC6ZYCtZPrpYQ4C m0/ZoyjftHwJDvZSWFeHc7V1cB19WR8ouls1xE8wSHQj9ZSBG/zZdQbUr//U4Hz78NOh 70ld40peqz55/qWelsXnefWszp8OMz/rpqmTbA6IjQrxu45BbDpIS0QzOQ2DFbGI6PtQ RNqBkZX2Prkbb3LIHpdKtx0PT/Q6nocYrCQXe9fVAYLrKU6ViBsbbJUZSQKlvvaQsi7f 49WgjnxLy320wM2CPMu7og+jlX6VaL9gxSlfXHPthueLNUy/SEDBgRDH8QLQkHu54Wqp dG4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/OnIF5KJq38ydF7gLxLfsf0iN2iW7kEJTrwDz5/qCW8=; b=GGhKMG5ks/hGAAV/AyDQb0Wm4QUaPyVK8jbwFoPI6UfdTXABV+bqB12mWPZhpZ8bCo SyjubCqDWGaXpC+SdMP3LGpAkgdQzUHI0tgXqf7LGar1LTiBehapJmRa3Ufe++J6u87A GmeS7XD58PFXD0w2D+tG5sV0nf9WQ+OlY1pkGjRnwKk+ToDr5ZpXaDnTovAX63iGDj64 A4NYmD8OzBT2n6KUZecb4G/IElRjx9O8b/TSfwmBvgAfmcf4xQo0DJBVgCWnUAI0cJwf xXw/0P2dm75xKRihb27iB+oC6xEG6az74vAsFkALCGAJBXz3abgxElfykQn6nrLQy5zX Sxqw== X-Gm-Message-State: ANoB5pmY1pvZBhroxjsjcqKZ5z97Tuk3Kn2hhpAWvAquO9LKCk2UpCeh DnyM0kALfej33cNRuiKxgnZL2w== X-Received: by 2002:a17:906:d82:b0:7ad:8a7a:2343 with SMTP id m2-20020a1709060d8200b007ad8a7a2343mr13999054eji.225.1668526058653; Tue, 15 Nov 2022 07:27:38 -0800 (PST) Received: from localhost.localdomain ([194.29.137.22]) by smtp.gmail.com with ESMTPSA id ku21-20020a170907789500b007ae1ab8f887sm5750679ejc.14.2022.11.15.07.27.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 15 Nov 2022 07:27:38 -0800 (PST) From: Konrad Dybcio To: linux-arm-msm@vger.kernel.org, andersson@kernel.org, agross@kernel.org, krzysztof.kozlowski@linaro.org Cc: patches@linaro.org, Konrad Dybcio , Will Deacon , Robin Murphy , Joerg Roedel , Rob Herring , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/9] dt-bindings: arm-smmu: Allow 3 power domains on SM6375 MMU500 Date: Tue, 15 Nov 2022 16:27:19 +0100 Message-Id: <20221115152727.9736-2-konrad.dybcio@linaro.org> X-Mailer: git-send-email 2.32.0 (Apple Git-132) In-Reply-To: <20221115152727.9736-1-konrad.dybcio@linaro.org> References: <20221115152727.9736-1-konrad.dybcio@linaro.org> MIME-Version: 1.0 X-Spam-Status: No, score=-2.1 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_NONE, SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749576692764266267?= X-GMAIL-MSGID: =?utf-8?q?1749576692764266267?= The SMMU on SM6375 requires 3 power domains to be active. Add an appropriate description of that. Signed-off-by: Konrad Dybcio Reviewed-by: Krzysztof Kozlowski Acked-by: Will Deacon --- .../devicetree/bindings/iommu/arm,smmu.yaml | 23 ++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml index 28f5720824cd..348a73f3e5f0 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.yaml +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.yaml @@ -200,7 +200,8 @@ properties: maxItems: 7 power-domains: - maxItems: 1 + minItems: 1 + maxItems: 3 nvidia,memory-controller: description: | @@ -364,6 +365,26 @@ allOf: - description: interface clock required to access smmu's registers through the TCU's programming interface. + - if: + properties: + compatible: + contains: + const: qcom,sm6375-smmu-500 + then: + properties: + power-domains: + items: + - description: SNoC MMU TBU RT GDSC + - description: SNoC MMU TBU NRT GDSC + - description: SNoC TURING MMU TBU0 GDSC + + required: + - power-domains + else: + properties: + power-domains: + maxItems: 1 + examples: - |+ /* SMMU with stream matching or stream indexing */ From patchwork Tue Nov 15 15:27:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20431 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793557wru; Tue, 15 Nov 2022 07:32:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf6JAz4psQ3Clcp9izhsDjC18ETpqHaqp6qLKTjuhUVIipObE5mCER5tEQdsUnmcJyblHIEi X-Received: by 2002:a17:906:141b:b0:78d:5176:c4d2 with SMTP id p27-20020a170906141b00b0078d5176c4d2mr13992777ejc.532.1668526358732; Tue, 15 Nov 2022 07:32:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526358; cv=none; d=google.com; s=arc-20160816; b=aIlGfpmVqjSJJXChPd0QoI7dcJjEaRLlSGCx3tU1GjBng79PGaIQ/a9dzGvcdw4wOU A+Fs3SOPGBTMEryC7Hm1kL7OCCfuZ2qH83qew/Xv911u5BVR3HRI2PsBbjjBWJaTm/Dg /7ok9yFp0+q89FF5WskYGAkGjejyj/5Py9vwuOEMKPKqakTpTjWNcmZVDTo2Mex/mUdh MQ55q73uhi8BujaN8rpQ+6nUArSmToLLfdNNHDy039rZgI5IOflRIg2I//EiqD/eQqWH HH47fitNoxN2SF49Jts5x7rCr171mufEOsEdOJM0qHfSxoWZcwelM5fB0EUYFwZvLi9s iOrw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=IypuJ/Pof2USoK7b4/Atk2DRjHrF23U2plR6w47C7ao=; b=mpcd/JyUWm2fo4+2+EtIUo4mZ6cl0Fk0uwtV9+ZJ3VQJ5KROQa+Jz2Odwzs48Tpfuu 4AQrgPwGJtvThmT629buL7vIE9vzpuBI4s/vcP+IeGc7QM8xBsDjTeYlHQglgUShawnZ v/L+HSR3Ygib6sdnrjjKCadhw8Jj84q94pEa6ab43PbbqBX9z+waw+vgfg/y3KagjrAk oBDI5BdHtwV9G44hSuKY9aDdraGVrpXqtsCjNNHWIzcfRkra95TkjMZmPsPDRq96oTRB aUVbPLWPwwThvje0/fXjbB/Aa6PNuFqf0q0NkhYA8D3jq8MD4WDOT6LpE3EARV1nG8fH ildw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ito5/jlo"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Add some preprocessor logic to allow changing the SID in cases like this. While I am not in favour of adding #if's into the device tree, this is the least messy way to handle this. If one isn't specified, it will default to 0 (as it has been previously). Suggested-by: Dmitry Baryshkov Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index a7ec9d11946d..2730d97ab213 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -8,10 +8,15 @@ #include #include +/* (Sadly) this PMIC can be configured to be at different SIDs */ +#ifndef PMK8350_SID + #define PMK8350_SID 0 +#endif + &spmi_bus { - pmk8350: pmic@0 { + pmk8350: pmic@PMK8350_SID { compatible = "qcom,pmk8350", "qcom,spmi-pmic"; - reg = <0x0 SPMI_USID>; + reg = ; #address-cells = <1>; #size-cells = <0>; @@ -21,14 +26,14 @@ pmk8350_pon: pon@1300 { pon_pwrkey: pwrkey { compatible = "qcom,pmk8350-pwrkey"; - interrupts = <0x0 0x13 0x7 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; linux,code = ; status = "disabled"; }; pon_resin: resin { compatible = "qcom,pmk8350-resin"; - interrupts = <0x0 0x13 0x6 IRQ_TYPE_EDGE_BOTH>; + interrupts = ; status = "disabled"; }; }; @@ -38,14 +43,14 @@ pmk8350_vadc: adc@3100 { reg = <0x3100>; #address-cells = <1>; #size-cells = <0>; - interrupts = <0x0 0x31 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #io-channel-cells = <1>; }; pmk8350_adc_tm: adc-tm@3400 { compatible = "qcom,adc-tm7"; reg = <0x3400>; - interrupts = <0x0 0x34 0x0 IRQ_TYPE_EDGE_RISING>; + interrupts = ; #address-cells = <1>; #size-cells = <0>; #thermal-sensor-cells = <1>; @@ -56,7 +61,7 @@ pmk8350_rtc: rtc@6100 { compatible = "qcom,pmk8350-rtc"; reg = <0x6100>, <0x6200>; reg-names = "rtc", "alarm"; - interrupts = <0x0 0x62 0x1 IRQ_TYPE_EDGE_RISING>; + interrupts = ; status = "disabled"; }; From patchwork Tue Nov 15 15:27:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20429 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793555wru; Tue, 15 Nov 2022 07:32:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf5WYO0LGW62pwH35NONS9OfYOk4SUdAmgXRm6m0YN1kJDOP+17Bn5UuWJNG30rCPHPqyzaJ X-Received: by 2002:a17:906:f8d6:b0:7ad:a0cb:f79e with SMTP id lh22-20020a170906f8d600b007ada0cbf79emr13750025ejb.458.1668526358441; Tue, 15 Nov 2022 07:32:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526358; cv=none; d=google.com; s=arc-20160816; b=GpfFHxmavi37B6LQQf2V/s3yyb+4HdNvCnFO2osElJXhirPWjaaJfy2IPZmprMIAff xJr8yXljQeYT6qFJNKcLV5jpri8F8cvn1sZtKYKPV5/fOTAKcjr2/mTDgteynd3tu334 dUbRBCHSQSUi8rpHxrEW8BW9LUARReHQXEe2KIMcg/0DvuUH7ZpwAHMEUWBXtkRKHK86 cMULVcTsi+wpfY4QZ2kUeiIj+Zlmw+60jHBvzzVrHV/eMNk5yd87fGCFFuF5KfhuluVU vX0wqvCOwrDaFOtxihtki1zC4RMeE6grT8ZIYhAABh+iBWiY4MWmkKYnV1bryd5u1WD8 6mzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Pye56l5tV+PFr5V02s5kVYgOc0gcJFpQaxO9onF9KkY=; b=a7+SbyYQdBw4kzPLzewwCT1r4vhf5VDuBdU2kGvEWPI6KKISkkpz6qKr/HXw0z0NAx YV4W17xJBeds7+srVvISwhwBr9cug7Tx/tZkLHEWVxNp1+heUP/1bVh2I6W/cUQkd2JH 0s2laGAttGvn90IukKp0XlpJqmbXqobs5xZnvlXrFIdjRQGONFzxEOghiTqcHNiyeOfp GxGAjLFq7uWvqRCrZoBqh2QHDGH8pQYR9AbKI32NXK4lq4jto5e2D52KMIgttDhDsCIY GY7+nt0Pn3pILSZBxNwENHDtDg+ML0fkkq9PpU/OyveKbq5v0FhRpnj/JOgE4GafFKzT C3Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rQyKdD+G; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 40 ++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 9b1a497e5ca7..62a64dd731a0 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -567,6 +567,46 @@ rpm_msg_ram: sram@45f0000 { reg = <0 0x045f0000 0 0x7000>; }; + gpi_dma0: dma-controller@4a00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04a00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0x16 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + + gpi_dma1: dma-controller@4c00000 { + compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; + reg = <0 0x04c00000 0 0x60000>; + interrupts = , + , + , + , + , + , + , + , + , + ; + dma-channels = <10>; + dma-channel-mask = <0x1f>; + iommus = <&apps_smmu 0xd6 0x0>; + #dma-cells = <3>; + status = "disabled"; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Tue Nov 15 15:27:22 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20430 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793554wru; Tue, 15 Nov 2022 07:32:38 -0800 (PST) X-Google-Smtp-Source: AA0mqf7xFncsJGLQzznD9E+bGmFt9XsWM86cuKekUozHJqDI9/UGUN4DRrE02BMSDMhPnlQTePn2 X-Received: by 2002:a17:906:f916:b0:7ae:ea4:583c with SMTP id lc22-20020a170906f91600b007ae0ea4583cmr14295002ejb.587.1668526358334; Tue, 15 Nov 2022 07:32:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526358; cv=none; d=google.com; s=arc-20160816; b=FV665XTxgUHebfR60/DBJ6b7P697gXV0dJ0QG/aYei6bpxICdEbN7DOvDISNjD40cM atJ+07PBXmj5FSLYtK3l0FpkrS0CK0Gu2LB3/fukGc1B1afboVj3mmscz8j+z3e+D2U8 aSqj4FPuqCka99X8RZCe8Ab+A2CYsmGBB2dV5TRmZ6VzX1CmmUvL5RB0uzDKRSWLCVNf P91WohMso/2Za4jqG1j4m0zj9ZU9ajN6XuCylx8kkYAH0gDeIc/fcH3awbRCozaAJgfa nessrIfgAM58aJAVPKdd49OROnrFASYVGq8Qp8mJhiWG8kaV5LSdo34QdKakr9vPZkFL nU+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=SDy57A29Jt3nxCLhxNQpZVWPQDSpsEBiQXxsa3bo3/k=; b=AXnEyfBC91D4LLGherYEVGrThW02bZ/rt8Q6LS50lz0ovbB+WmMjqgyppy1S7iyWzb ZFmA1G7YhUDn18Cxgus6uufvubkCwSkFb7OpHZsLbm/nC2vz786/Cs7NyYzOBCZ1MJVz p1MpUYqqaHQZcDBhTcRxSYOfYkIh1R1Y+t2d0NEAWGgVOfQGeq60l+qxdtX19VHI84Fo vv317+RWVIy3IJ+qZ7A4tFnd1G+ymzsrJpVvT1MoaRqSmdrqhCG5MFSyVUHg2ObMXpyP nlmD4YmIOEkVW7gqS6u4MaOK6T+T53DjIjRkoWD6ohmVIiQg00ntxxG7GP10/DZ/deuH myzw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RxdALIPT; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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I can guesstimate the correct settings for other buses, but: - I have no hardware to test it on - Some QUPs are straight up missing pin funcs in TLMM - Vendors probably didn't really care and used whatever was there in the reference design and BSP - should any other be used, they can be configured at a later time Acked-by: Krzysztof Kozlowski Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 43 ++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 62a64dd731a0..952156891476 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -519,6 +519,49 @@ tlmm: pinctrl@500000 { gpio-controller; #interrupt-cells = <2>; #gpio-cells = <2>; + + qup_i2c0_default: qup-i2c0-default-state { + pins = "gpio0", "gpio1"; + function = "qup00"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c1_default: qup-i2c1-default-state { + pins = "gpio61", "gpio62"; + function = "qup01"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c2_default: qup-i2c2-default-state { + pins = "gpio45", "gpio46"; + function = "qup02"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c8_default: qup-i2c8-default-state { + pins = "gpio19", "gpio20"; + /* TLMM, GCC and vendor DT all have different indices.. */ + function = "qup12"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_i2c10_default: qup-i2c10-default-state { + pins = "gpio4", "gpio5"; + function = "qup10"; + drive-strength = <2>; + bias-pull-up; + }; + + qup_spi0_default: qup-spi0-default-state { + pins = "gpio0", "gpio1", "gpio2", "gpio3"; + function = "qup00"; + drive-strength = <6>; + bias-disable; + }; }; gcc: clock-controller@1400000 { From patchwork Tue Nov 15 15:27:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20433 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793667wru; Tue, 15 Nov 2022 07:32:49 -0800 (PST) X-Google-Smtp-Source: AA0mqf5dLV7ckSgEPgxoxD4zQEnHa3c5D4ZwSClHyYQUJXhdvFDZFWGDtaRqYARgE0SawKc9d/sM X-Received: by 2002:a17:906:7203:b0:7ae:664a:a7d2 with SMTP id m3-20020a170906720300b007ae664aa7d2mr14281718ejk.676.1668526368987; Tue, 15 Nov 2022 07:32:48 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526368; cv=none; d=google.com; s=arc-20160816; b=Yi7TfAq+i3NOU5xdIfi3Qw9oakPcwVu+lr98JrH2AHu/jR6vf34GDSB0FwOJNU7URh er7b1n63wkuPOdayOsGpSfFZDda6qRaWlG/PAqv3hlXvHFs6o/DuNDu8lPKpyl5Mu+43 /OZqgucCivJ2hsw42ThmkhGRChCUFsevqLm9uBXzq9XVpqgBsyhXEL0THypfrIo3ml1F P8M06lVwDb8KLBTH/nAsxSGGkU1nyKZ2zNCRWQ3Hc3SQGsnohqNr4dDtKCE9YIPnUUAV 9dgnWmcpkNGLtM9HjZkFYVTEQn/lbNCRCsNeb9cIkdtrqHJSF1cPmyfcTSmaq/ZNKS7p YW1w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=iAgMkFLh+A9qlmK7u0Nv6XHzT4Yq7Xys6b3k49GmNps=; b=xXPoHhhyY6BEI0K22qwUfXEFak4VeIv/wDMvoynXWlBgvTgW3M87OasHbYnC5cXQvL fAb+//datRTd43cUebP35Fhky+qVVZJ8bmG1pGtNaTFa4SEb3WWJTgQuqdmfptEytz58 uWjNoq9ucnc0tNfA0PqW8ddLg59rxGHYW66Bm/qZB/2t7OhO7SlpR/Ku2vqJG/tiwOnh MWFJXNh6+5hftUsSzcvESe0sG4H22ZeWE25A2GkQueah/kzlDxHVF2NIhn97EKfgRlyU L2h1ycqoGYBIwEw4eDk/fYbl+haojg7wGyfAZXll5WXnwxC74vwCJTA9w52HKAZLchP3 FcRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tHaUT9hl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Note that: - QUP3/4/5 and 11 are straight up missing - There may be more QUPs physically on the SoC that work perfectly fine, but Qualcomm decided not to expose them on the downstream kernel - Many are missing pinctrls, as there are both missing pin funcs in the TLMM driver and missing configuration settings (though they are possible to guesstimate quite easily) Signed-off-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sm6375.dtsi | 306 +++++++++++++++++++++++++++ 1 file changed, 306 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375.dtsi b/arch/arm64/boot/dts/qcom/sm6375.dtsi index 952156891476..6adffd927a8e 100644 --- a/arch/arm64/boot/dts/qcom/sm6375.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6375.dtsi @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -317,6 +318,25 @@ CLUSTER_PD: cpu-cluster0 { }; }; + qup_opp_table: opp-table-qup { + compatible = "operating-points-v2"; + + opp-75000000 { + opp-hz = /bits/ 64 <75000000>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-100000000 { + opp-hz = /bits/ 64 <100000000>; + required-opps = <&rpmpd_opp_svs>; + }; + + opp-128000000 { + opp-hz = /bits/ 64 <128000000>; + required-opps = <&rpmpd_opp_nom>; + }; + }; + reserved_memory: reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -630,6 +650,125 @@ gpi_dma0: dma-controller@4a00000 { status = "disabled"; }; + qupv3_id_0: geniqup@4ac0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04ac0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c0: i2c@4a80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c0_default>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, + <&gpi_dma0 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi0: spi@4a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_spi0_default>; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, + <&gpi_dma0 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@4a84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c1_default>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, + <&gpi_dma0 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@4a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, + <&gpi_dma0 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@4a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c2_default>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, + <&gpi_dma0 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi2: spi@4a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04a88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, + <&gpi_dma0 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + /* + * As per GCC, QUP3/4/5/11 also exist, but are not even defined downstream. + * There is a comment in the included DTSI of another SoC saying that they + * are not "bolled out" (probably meaning not routed to solder balls) + * TLMM driver however, suggests there are as many as 15 QUPs in total! + * Most of which don't even have pin configurations for.. Sad stuff! + */ + }; + gpi_dma1: dma-controller@4c00000 { compatible = "qcom,sm6375-gpi-dma", "qcom,sm6350-gpi-dma"; reg = <0 0x04c00000 0 0x60000>; @@ -650,6 +789,173 @@ gpi_dma1: dma-controller@4c00000 { status = "disabled"; }; + qupv3_id_1: geniqup@4cc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x04cc0000 0x0 0x2000>; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; + iommus = <&apps_smmu 0xc3 0x0>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + i2c6: i2c@4c80000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, + <&gpi_dma1 1 0 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi6: spi@4c80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c80000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, + <&gpi_dma1 1 0 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c7: i2c@4c84000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, + <&gpi_dma1 1 1 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi7: spi@4c84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c84000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, + <&gpi_dma1 1 1 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c8: i2c@4c88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c8_default>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, + <&gpi_dma1 1 2 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi8: spi@4c88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c88000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, + <&gpi_dma1 1 2 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c9: i2c@4c8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, + <&gpi_dma1 1 3 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi9: spi@4c8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c8c000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, + <&gpi_dma1 1 3 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c10: i2c@4c90000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&qup_i2c10_default>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, + <&gpi_dma1 1 4 QCOM_GPI_I2C>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi10: spi@4c90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x04c90000 0x0 0x4000>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interrupts = ; + power-domains = <&rpmpd SM6375_VDDCX>; + operating-points-v2 = <&qup_opp_table>; + dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, + <&gpi_dma1 1 4 QCOM_GPI_SPI>; + dma-names = "tx", "rx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + }; + usb_1: usb@4ef8800 { compatible = "qcom,sm6375-dwc3", "qcom,dwc3"; reg = <0 0x04ef8800 0 0x400>; From patchwork Tue Nov 15 15:27:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20435 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793754wru; Tue, 15 Nov 2022 07:32:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf4sPjRLqSXP+Hp6lBz3VA82SL78NDIN0UoqHYsyoHGj+vQoOYGcaeGJSLYxQgoSCWI+/Ce+ X-Received: by 2002:a17:906:3bc8:b0:7ae:6450:c620 with SMTP id v8-20020a1709063bc800b007ae6450c620mr14178838ejf.270.1668526375045; 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 450d4a557df1..6a0f4c0bf7ad 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -65,6 +65,22 @@ vph_pwr: vph-pwr-regulator { }; }; +&gpi_dma0 { + status = "okay"; +}; + +&gpi_dma1 { + status = "okay"; +}; + +&qupv3_id_0 { + status = "okay"; +}; + +&qupv3_id_1 { + status = "okay"; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Tue Nov 15 15:27:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20436 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793771wru; Tue, 15 Nov 2022 07:32:57 -0800 (PST) X-Google-Smtp-Source: AA0mqf4o678J/USVNLUiDb24/cSUxQcLJOsFA1bhZZojaWZmoAumTVZFZaDrz9RPiWX+Rk7ZpoJZ X-Received: by 2002:a17:906:3ecf:b0:7ac:db70:3ab5 with SMTP id d15-20020a1709063ecf00b007acdb703ab5mr14489369ejj.160.1668526377052; Tue, 15 Nov 2022 07:32:57 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526377; cv=none; d=google.com; s=arc-20160816; b=JOMUnQ+PItFen9/PgVTTUV5u3wu6UIeH7UnjlGw/bMJExKPmO4i/zwjmw/L+EWIQNI 8l8BEpJTpm3bDpbcdWrc04WxQk5g+5d0O+xUFtOkTTDXy5Anzjj7dqoZYCuCa13k59hl PVaMb5EdfQtk1Yh5AsX9QBLRkWEuPYehD7K2juxmCvNhKwl8x0uey+i4F3oSSZxPzzr7 DD4oeBwc+mg8RVbxt2oYEqER8RpmYI2Nf2/nagRghvV2PwL55bYImqcDcWMtfoJNJiP4 LsCMTBanlFmlk6RO1f6jfv6jX2utTf8EKXo8BePTe4qjarpFu/cvr+Vvs5GGnmXrX+0q ZBGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tczgVkko34uNNjGCJDRlpeQPz9HaugPUNs3BO6M1w28=; b=P+eeOLDRnczlMPTveoUi2f4Z/T85xbCWCFwL74prT1OXm9A635Ei/87eI4U6gsLAcb 4G2Cq0Tsi8b5u3XJBggd4slUtFSNAzpus35NUXUbnHUunCUSeGkdUDT6rQeBuBB/y0jq wPnHBsy3f1dJuXA39NU1mn+Uk/Twxo3gKmpT/1aChG9k2Ops0vdgotqTJPid5nwtW342 t28X/fo17FJ+4JAPxwFlocMlX8yfzS0xQCv1SNeCHPvL7j5BA61mN4U6Fcudo3fhM8H7 n1qS1FFL7qdtrrk/+k4SrbKQRdYH+p0dHtufZvyli6NFrKutk1dChB5nuTcwlfpS/0Ce hGkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m2gDNZOw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 25 +++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 6a0f4c0bf7ad..c830124cb483 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -5,10 +5,18 @@ /dts-v1/; +/* PMK8350 is configured to use SID6 instead of 0 */ +#define PMK8350_SID 6 + #include #include "sm6375.dtsi" +#include "pm6125.dtsi" +#include "pmk8350.dtsi" #include "pmr735a.dtsi" +/* PM6125 PON is used and we can't have duplicate labels */ +/delete-node/ &pmk8350_pon; + / { model = "Sony Xperia 10 IV"; compatible = "sony,pdx225", "qcom,sm6375"; @@ -73,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&pmk8350_adc_tm { + status = "okay"; +}; + +&pmk8350_rtc { + status = "okay"; +}; + +&pon_pwrkey { + status = "okay"; +}; + +&pon_resin { + linux,code = ; + status = "okay"; +}; + &qupv3_id_0 { status = "okay"; }; From patchwork Tue Nov 15 15:27:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20437 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2793791wru; Tue, 15 Nov 2022 07:32:58 -0800 (PST) X-Google-Smtp-Source: AA0mqf6mLjssQ6dTZpGWs7p4xY6X5mUe6uucM4jXdUYe9OdUplDa+ddX5wBbqMFWbdatXUPRt9bw X-Received: by 2002:aa7:da1a:0:b0:454:cbef:c161 with SMTP id r26-20020aa7da1a000000b00454cbefc161mr16165026eds.365.1668526378635; Tue, 15 Nov 2022 07:32:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526378; cv=none; d=google.com; s=arc-20160816; b=uTyY21t5IEj93KC/awXZDz7jOMbo3pVEm//EwktLxsZhCSxdK4ayxO8Vzlm/UKOJ8t HCMpoWOv5Jct1dLX20CoLG0nB4BqNbSpsIBC1PIal98Akb83bvJ5YCVlrncydb8FREbJ o2psYPYc09afj/AiZAcqdfI/Zpo39Hmc/uFsC4BZUMacpr7Sir0p9k3ysub4VX8j2/0J c7+G8u6/EGG7GrPwPZ75H8i3LowZ/44AIYP0Xhqjykecx5zjmN8re/nqZBe/mrrHEy1e yVycfj3lMN+3F5sO+9jOJLsroxzjI0KwK/Dj4VR77r+1I905kA7255hiskN6nO+2PQEu VHOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vg8NC6M8db0CO7+c1/ONSYumm0SUtSfLgSyiNkD+2X8=; b=xvXbYS5KpbltWyiI+Xar7OOq5TpGTev7mpyPAFKDOMylEoEZEOtqZWzDiaQJHT1fjm cP2alc/R1I8vEPUuErcvDAetzGm4F5YVfyXBCduYVYK5gh49/Ss41pDaSvba2VmOjSwC 4P3tNBGTdZpVZ3vRHVposLohNH+lHE+tOIEaR7ynkPbFrkgAGDfUY6Ty8sXFPW1DKqet u2e2IgZHFubggI4IX1w4BKkH+zbIqk2Pndh+/CvDFky/Rxubw5S/rd7EhhdPoEyCLD4f vDd0in0cO2GmT5XSJkGJlbnoBaRAqHwfh+6F+FgcJ/IDK06xPmhVG+duyYz8ueZUvymq 5l1Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KMv9NkjC; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 182 ++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index c830124cb483..0f1ddfa28c89 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -106,6 +106,188 @@ &qupv3_id_1 { status = "okay"; }; +&rpm_requests { + regulators-0 { + compatible = "qcom,rpm-pm6125-regulators"; + + pm6125_s5: s5 { + regulator-min-microvolt = <382000>; + regulator-max-microvolt = <1120000>; + }; + + pm6125_s6: s6 { + regulator-min-microvolt = <320000>; + regulator-max-microvolt = <1374000>; + }; + + pm6125_s7: s7 { + regulator-min-microvolt = <1574000>; + regulator-max-microvolt = <2040000>; + }; + + /* + * S8 is VDD_GFX + * L1 is VDD_LPI_CX + */ + + pm6125_l2: l2 { + regulator-min-microvolt = <1170000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l3: l3 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l4: l4 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1300000>; + }; + + pm6125_l5: l5 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3050000>; + }; + + pm6125_l6: l6 { + regulator-min-microvolt = <1080000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l7: l7 { + regulator-min-microvolt = <720000>; + regulator-max-microvolt = <1050000>; + }; + + pm6125_l8: l8 { + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1304000>; + }; + + pm6125_l9: l9 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l10: l10 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l11: l11 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l12: l12 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <2000000>; + }; + + pm6125_l13: l13 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <1980000>; + }; + + pm6125_l14: l14 { + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <1900000>; + }; + + pm6125_l15: l15 { + regulator-min-microvolt = <1650000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l16: l16 { + regulator-min-microvolt = <1620000>; + regulator-max-microvolt = <1980000>; + }; + + /* L17 is VDD_LPI_MX */ + + pm6125_l18: l18 { + regulator-min-microvolt = <830000>; + regulator-max-microvolt = <920000>; + }; + + pm6125_l19: l19 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l20: l20 { + regulator-min-microvolt = <1624000>; + regulator-max-microvolt = <3304000>; + }; + + pm6125_l21: l21 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l22: l22 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + + pm6125_l23: l23 { + regulator-min-microvolt = <3000000>; + regulator-max-microvolt = <3400000>; + }; + + pm6125_l24: l24 { + regulator-min-microvolt = <2704000>; + regulator-max-microvolt = <3544000>; + }; + }; + + regulators-1 { + compatible = "qcom,rpm-pmr735a-regulators"; + + /* + * S1 is VDD_MX + * S2 is VDD_CX + */ + + pmr735a_l1: l1 { + regulator-min-microvolt = <570000>; + regulator-max-microvolt = <650000>; + }; + + pmr735a_l2: l2 { + regulator-min-microvolt = <352000>; + regulator-max-microvolt = <796000>; + }; + + pmr735a_l3: l3 { + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1200000>; + }; + + pmr735a_l4: l4 { + regulator-min-microvolt = <1504000>; + regulator-max-microvolt = <2000000>; + }; + + pmr735a_l5: l5 { + regulator-min-microvolt = <751000>; + regulator-max-microvolt = <824000>; + }; + + pmr735a_l6: l6 { + regulator-min-microvolt = <504000>; + regulator-max-microvolt = <868000>; + }; + + pmr735a_l7: l7 { + regulator-min-microvolt = <2700000>; + regulator-max-microvolt = <3544000>; + }; + }; +}; + &tlmm { gpio-reserved-ranges = <13 4>; }; From patchwork Tue Nov 15 15:27:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Konrad Dybcio X-Patchwork-Id: 20438 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2794114wru; Tue, 15 Nov 2022 07:33:27 -0800 (PST) X-Google-Smtp-Source: AA0mqf46sBGo1Gf42XErk4fdVRl/VMn1CWQUfKFBiNdHVLqtgFGEGmxc09D5i63J7qhLqG2pburE X-Received: by 2002:a17:906:b44:b0:7ad:b8c0:3057 with SMTP id v4-20020a1709060b4400b007adb8c03057mr14407619ejg.440.1668526407835; Tue, 15 Nov 2022 07:33:27 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668526407; cv=none; d=google.com; s=arc-20160816; b=Pwn9gklyMSOLAy57hE6Mmwc47BxgzTvTmbShKe0hmh79zVS4wgJbL2wgJaP6yVB92m vy9WN1actCYDBthszcwY1vPqnggmB9HfjNi6/YHkpbLHSf+TFT1HEckayziZ2rS9rRVI MtOWpKjanougJDULtN+oOuPzaS7NFJMtqBvfk297Q9nlpeSoZ2vnBLheGA5FZqio6hhm 2gCAl/aCxDmo983bOtyA+YqrEYhWYkw9IqzVylYwayG1ky2WzQqSIsQvmRd0eq2jBZRI Gc3qllxddSAC32nleY5AFNVvgifEJvYONVYGYqKJHJS0KsdDshegI0d9Ufb4gRh2AUXg WVzg== ARC-Message-Signature: i=1; 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The OEM that built the Xperia 10 IV for SONY decided to use some kind of a GPIO regulator that needs to be enabled at all times for both the touch panel and the display panel to function. Signed-off-by: Konrad Dybcio --- .../qcom/sm6375-sony-xperia-murray-pdx225.dts | 31 +++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts index 0f1ddfa28c89..d18167bcb41f 100644 --- a/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts +++ b/arch/arm64/boot/dts/qcom/sm6375-sony-xperia-murray-pdx225.dts @@ -81,6 +81,23 @@ &gpi_dma1 { status = "okay"; }; +&i2c8 { + clock-frequency = <400000>; + status = "okay"; + + touchscreen@48 { + compatible = "samsung,s6sy761"; + reg = <0x48>; + interrupt-parent = <&tlmm>; + interrupts = <22 0x2008>; + + vdd-supply = <&pm6125_l13>; + + pinctrl-names = "default"; + pinctrl-0 = <&ts_int_default &ts_avdd_default>; + }; +}; + &pmk8350_adc_tm { status = "okay"; }; @@ -290,6 +307,20 @@ pmr735a_l7: l7 { &tlmm { gpio-reserved-ranges = <13 4>; + + ts_int_default: ts-int-default-state { + pins = "gpio22"; + function = "gpio"; + drive-strength = <8>; + bias-pull-up; + }; + + ts_avdd_default: ts-avdd-default-state { + pins = "gpio59"; + function = "gpio"; + drive-strength = <8>; + output-high; + }; }; &usb_1 {