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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB4F.mail.protection.outlook.com (10.167.242.73) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Sun, 4 Feb 2024 12:13:15 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 4 Feb 2024 06:13:12 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 1/6] cpufreq: amd-pstate: initialize new core precision boost state Date: Sun, 4 Feb 2024 20:12:52 +0800 Message-ID: <51d8381943c3cfa7841775b02a414355f6baa20c.1707047943.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4F:EE_|DS0PR12MB7655:EE_ X-MS-Office365-Filtering-Correlation-Id: 3939e072-265f-41c0-4248-08dc257aaa92 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:15.7248 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3939e072-265f-41c0-4248-08dc257aaa92 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7655 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970454944145371 X-GMAIL-MSGID: 1789970454944145371 From: Perry Yuan Add gloal global_params to represent current CPU Performance Boost(cpb) state for cpu frequency scaling, both active and passive modes all can support CPU cores frequency boosting control which is based on the BIOS setting, while BIOS turn on the "Core Performance Boost", it will allow OS control each core highest perf limitation from OS side. If core performance boost is disabled while a core is in a boosted P-state, the core transitions to the highest performance non-boosted P-state, that is the same as the nominal frequency limit. Reported-by: Artem S. Tashkinov" Closes: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 61 +++++++++++++++++------------------- 1 file changed, 28 insertions(+), 33 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 9a1e194d5cf8..921324ab9580 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -65,6 +65,19 @@ static struct cpufreq_driver amd_pstate_epp_driver; static int cppc_state = AMD_PSTATE_UNDEFINED; static bool cppc_enabled; +/** + * struct global_params - Global parameters, mostly tunable via sysfs. + * @cpb_boost: Whether or not to use boost CPU P-states. + * @cpb_supported: Whether or not CPU boost P-states are available + * based on the MSR_K7_HWCR bit[25] state + */ +struct global_params { + bool cpb_boost; + bool cpb_supported; +}; + +static struct global_params global; + /* * AMD Energy Preference Performance (EPP) * The EPP is used in the CCLK DPM controller to drive @@ -632,43 +645,21 @@ static int amd_get_lowest_nonlinear_freq(struct amd_cpudata *cpudata) return lowest_nonlinear_freq * 1000; } -static int amd_pstate_set_boost(struct cpufreq_policy *policy, int state) +static int amd_pstate_boost_init(struct amd_cpudata *cpudata) { - struct amd_cpudata *cpudata = policy->driver_data; + u64 boost_val; int ret; - if (!cpudata->boost_supported) { - pr_err("Boost mode is not supported by this processor or SBIOS\n"); - return -EINVAL; - } - - if (state) - policy->cpuinfo.max_freq = cpudata->max_freq; - else - policy->cpuinfo.max_freq = cpudata->nominal_freq; - - policy->max = policy->cpuinfo.max_freq; - - ret = freq_qos_update_request(&cpudata->req[1], - policy->cpuinfo.max_freq); - if (ret < 0) + ret = rdmsrl_on_cpu(cpudata->cpu, MSR_K7_HWCR, &boost_val); + if (ret) { + pr_err_once("failed to read initial CPU boost state!\n"); return ret; + } - return 0; -} - -static void amd_pstate_boost_init(struct amd_cpudata *cpudata) -{ - u32 highest_perf, nominal_perf; - - highest_perf = READ_ONCE(cpudata->highest_perf); - nominal_perf = READ_ONCE(cpudata->nominal_perf); - - if (highest_perf <= nominal_perf) - return; + global.cpb_supported = !((boost_val >> 25) & 0x1); + global.cpb_boost = global.cpb_supported; - cpudata->boost_supported = true; - current_pstate_driver->boost_enabled = true; + return ret; } static void amd_perf_ctl_reset(unsigned int cpu) @@ -701,6 +692,9 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -750,7 +744,6 @@ static int amd_pstate_cpu_init(struct cpufreq_policy *policy) policy->driver_data = cpudata; - amd_pstate_boost_init(cpudata); if (!current_pstate_driver->adjust_perf) current_pstate_driver->adjust_perf = amd_pstate_adjust_perf; @@ -1118,6 +1111,9 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) if (ret) goto free_cpudata1; + /* initialize cpu cores boot state */ + amd_pstate_boost_init(cpudata); + min_freq = amd_get_min_freq(cpudata); max_freq = amd_get_max_freq(cpudata); nominal_freq = amd_get_nominal_freq(cpudata); @@ -1168,7 +1164,6 @@ static int amd_pstate_epp_cpu_init(struct cpufreq_policy *policy) return ret; WRITE_ONCE(cpudata->cppc_cap1_cached, value); } - amd_pstate_boost_init(cpudata); return 0; From patchwork Sun Feb 4 12:12:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 196485 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp319993dyb; Sun, 4 Feb 2024 04:14:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHIB9EZ/J84HbqtWyA3szIvjvjqHHjdE2e3YfgMTI84P5YZ7QNcBi4XIUkCGDjTiCCJmKjl X-Received: by 2002:a05:6a20:93a7:b0:19e:4e58:5026 with SMTP id x39-20020a056a2093a700b0019e4e585026mr8483936pzh.4.1707048893575; Sun, 04 Feb 2024 04:14:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXDKA9fLjMS4qRHJklYhQy7rdN38zdSNKgKdLDpIeWIxAVzBaKvj9R/qxTm9+LnWs3PMBA8jvvmiKHXpJuifcHe5k3M6w== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF0001AB51.mail.protection.outlook.com (10.167.242.75) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Sun, 4 Feb 2024 12:13:18 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 4 Feb 2024 06:13:15 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 2/6] cpufreq: amd-pstate: implement cpb_boost sysfs entry for boost control Date: Sun, 4 Feb 2024 20:12:53 +0800 Message-ID: <20e12e10aac1854507eaf512591694cbc0789c43.1707047943.git.perry.yuan@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB51:EE_|IA1PR12MB6577:EE_ X-MS-Office365-Filtering-Correlation-Id: 6f27dbc5-3b11-43c3-de91-08dc257aac7b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:18.9335 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 6f27dbc5-3b11-43c3-de91-08dc257aac7b X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB51.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6577 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970500976281996 X-GMAIL-MSGID: 1789970500976281996 From: Perry Yuan With this new sysfs entry `cpb_boost`created, user can change CPU boost state dynamically under `active`, `guided` and `passive` modes. And the highest perf and frequency will also be updated as the boost state changing. 0): check current boost state cat /sys/devices/system/cpu/amd_pstate/cpb_boost 1): disable CPU boost sudo bash -c "echo 0 > /sys/devices/system/cpu/amd_pstate/cpb_boost" 2): enable CPU boost sudo bash -c "echo 1 > /sys/devices/system/cpu/amd_pstate/cpb_boost" Link: https://bugzilla.kernel.org/show_bug.cgi?id=217931 Link: https://bugzilla.kernel.org/show_bug.cgi?id=217618 Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 97 ++++++++++++++++++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 921324ab9580..018ea7cdda2b 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1030,6 +1030,101 @@ static ssize_t status_store(struct device *a, struct device_attribute *b, return ret < 0 ? ret : count; } +static int amd_cpu_boost_update(struct amd_cpudata *cpudata, u32 on) +{ + struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu); + struct cppc_perf_ctrls perf_ctrls; + u32 highest_perf, nominal_perf; + int ret; + + if (!policy) + return -ENODATA; + + highest_perf = READ_ONCE(cpudata->highest_perf); + nominal_perf = READ_ONCE(cpudata->nominal_perf); + + if (boot_cpu_has(X86_FEATURE_CPPC)) { + u64 value = READ_ONCE(cpudata->cppc_req_cached); + + value &= ~GENMASK_ULL(7, 0); + value |= on ? highest_perf : nominal_perf; + WRITE_ONCE(cpudata->cppc_req_cached, value); + + wrmsrl_on_cpu(cpudata->cpu, MSR_AMD_CPPC_REQ, value); + + } else { + perf_ctrls.max_perf = on ? highest_perf : nominal_perf; + ret = cppc_set_epp_perf(cpudata->cpu, &perf_ctrls, 1); + if (ret) { + pr_debug("failed to set energy perf value (%d)\n", ret); + return ret; + } + } + + if (on) + policy->cpuinfo.max_freq = cpudata->max_freq; + else + policy->cpuinfo.max_freq = cpudata->nominal_freq; + + policy->max = policy->cpuinfo.max_freq; + + if (cppc_state == AMD_PSTATE_PASSIVE) { + ret = freq_qos_update_request(&cpudata->req[1], + policy->cpuinfo.max_freq); + } + + cpufreq_cpu_release(policy); + + return ret; +} + +static ssize_t cpb_boost_show(struct device *dev, + struct device_attribute *attr, char *buf) +{ + return sysfs_emit(buf, "%u\n", global.cpb_boost); +} + +static ssize_t cpb_boost_store(struct device *dev, struct device_attribute *b, + const char *buf, size_t count) +{ + bool new_state; + ssize_t ret; + int cpu; + + mutex_lock(&amd_pstate_driver_lock); + if (!global.cpb_supported) { + pr_err("Boost mode is not supported by this processor or SBIOS\n"); + return -EINVAL; + } + + ret = kstrtobool(buf, &new_state); + if (ret) + return -EINVAL; + + global.cpb_boost = !!new_state; + + for_each_possible_cpu(cpu) { + + struct cpufreq_policy *policy = cpufreq_cpu_get(cpu); + struct amd_cpudata *cpudata = policy->driver_data; + + if (!cpudata) { + pr_err("cpudata is NULL\n"); + ret = -ENODATA; + cpufreq_cpu_put(policy); + goto err_exit; + } + + amd_cpu_boost_update(cpudata, global.cpb_boost); + refresh_frequency_limits(policy); + cpufreq_cpu_put(policy); + } + +err_exit: + mutex_unlock(&amd_pstate_driver_lock); + return ret < 0 ? ret : count; +} + cpufreq_freq_attr_ro(amd_pstate_max_freq); cpufreq_freq_attr_ro(amd_pstate_lowest_nonlinear_freq); @@ -1037,6 +1132,7 @@ cpufreq_freq_attr_ro(amd_pstate_highest_perf); cpufreq_freq_attr_rw(energy_performance_preference); cpufreq_freq_attr_ro(energy_performance_available_preferences); static DEVICE_ATTR_RW(status); +static DEVICE_ATTR_RW(cpb_boost); static struct freq_attr *amd_pstate_attr[] = { &amd_pstate_max_freq, @@ -1056,6 +1152,7 @@ static struct freq_attr *amd_pstate_epp_attr[] = { static struct attribute *pstate_global_attributes[] = { &dev_attr_status.attr, + &dev_attr_cpb_boost.attr, NULL }; From patchwork Sun Feb 4 12:12:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 196486 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp319994dyb; Sun, 4 Feb 2024 04:14:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxvERrVgkeb84exaK0RMvJNFRiNjzFd2zjXbok+7CEffyZSMiBHo9p1lKA+yHY4YJ2Lme7 X-Received: by 2002:a05:6102:2a70:b0:46d:1e7f:f8c3 with SMTP id hp16-20020a0561022a7000b0046d1e7ff8c3mr1206731vsb.21.1707048893516; Sun, 04 Feb 2024 04:14:53 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXRz6C9S80Ib6XLrMqpweNbLdJNXzDISmTunEg8y1+oQG/UeLdAYmiKGhoxd5FwBumAaEd34MzBWciRIhSTFADJcj8TSA== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:22.5865 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e96db40c-02b0-416c-e2ab-08dc257aaea6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PR12MB7674 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970500899012222 X-GMAIL-MSGID: 1789970500899012222 From: Perry Yuan When CPU core Precision Boost state changed, the max frequency will also need to be updated according to the current boost state, if boost is disabled now, the max perf will be limited to nominal perf values. otherwise the max frequency will be showed wrongly. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 018ea7cdda2b..107883cf0877 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -599,6 +599,10 @@ static int amd_get_max_freq(struct amd_cpudata *cpudata) nominal_perf = READ_ONCE(cpudata->nominal_perf); max_perf = READ_ONCE(cpudata->highest_perf); + /* when boost is off, the highest perf will be limited to nominal_perf */ + if (!global.cpb_boost) + max_perf = nominal_perf; + boost_ratio = div_u64(max_perf << SCHED_CAPACITY_SHIFT, nominal_perf); From patchwork Sun Feb 4 12:12:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 196487 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp320118dyb; Sun, 4 Feb 2024 04:15:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IHtdc8ImjFvOlSsI3x08LUybdopZxpuFuEARXkNMuN46CrOnrA5Ug/455t/0mwxkvoCQ4RL X-Received: by 2002:a05:6870:7813:b0:219:3cc5:4892 with SMTP id hb19-20020a056870781300b002193cc54892mr4461729oab.5.1707048913105; Sun, 04 Feb 2024 04:15:13 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCXiVhG+TedCUXqfFE4o4DUeZK8PJGTAe9mzQezpSvQ8JcAVJ5dcJOWYL1JAjui+SQurUfuiChAlda85YhsrJ1YOjD9KNA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by MN1PEPF0000ECD7.mail.protection.outlook.com (10.167.242.136) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7249.19 via Frontend Transport; Sun, 4 Feb 2024 12:13:25 +0000 Received: from pyuan-Chachani-VN.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Sun, 4 Feb 2024 06:13:21 -0600 From: Perry Yuan To: , , , , , CC: , , , , , Subject: [PATCH v2 4/6] cpufreq: amd-pstate: fix the MSR highest perf will be reset issue while cpb boost off Date: Sun, 4 Feb 2024 20:12:55 +0800 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MN1PEPF0000ECD7:EE_|PH7PR12MB6786:EE_ X-MS-Office365-Filtering-Correlation-Id: 809e9b7a-65dc-431e-5b27-08dc257ab024 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:25.0709 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 809e9b7a-65dc-431e-5b27-08dc257ab024 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD7.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6786 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970520973411648 X-GMAIL-MSGID: 1789970520973411648 From: Perry Yuan Select the min perf to fix the highest perf value while update pstate CPPC request MSR register, here we need to limit the max perf value when CPU boost is disabled in case of that highest perf value in the MSR will be reset to original highest perf value which cause the BOOST control failed. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 107883cf0877..02a76b8fb298 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -443,6 +443,7 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, u32 des_perf, u32 max_perf, bool fast_switch, int gov_flags) { u64 prev = READ_ONCE(cpudata->cppc_req_cached); + u32 nominal_perf = READ_ONCE(cpudata->nominal_perf); u64 value = prev; des_perf = clamp_t(unsigned long, des_perf, min_perf, max_perf); @@ -458,6 +459,10 @@ static void amd_pstate_update(struct amd_cpudata *cpudata, u32 min_perf, value &= ~AMD_CPPC_DES_PERF(~0L); value |= AMD_CPPC_DES_PERF(des_perf); + /* limit the max perf when core performance boost feature is disabled */ + if (!global.cpb_boost) + max_perf = min_t(unsigned long, nominal_perf, max_perf); + value &= ~AMD_CPPC_MAX_PERF(~0L); value |= AMD_CPPC_MAX_PERF(max_perf); From patchwork Sun Feb 4 12:12:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 196488 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp320251dyb; Sun, 4 Feb 2024 04:15:31 -0800 (PST) X-Google-Smtp-Source: AGHT+IH8Iuj5TLOf7n3+K8PJiUEZlgoPq1RFOCCImbjmgF9O54YAeIE8VloxHVcTIf9UVWKtPR5M X-Received: by 2002:a17:90a:7c06:b0:296:1943:35a1 with SMTP id v6-20020a17090a7c0600b00296194335a1mr7693209pjf.35.1707048931388; Sun, 04 Feb 2024 04:15:31 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCWxDxuzJlY/kJkJUtUkLlwonYzhBF7kslEfNSqCfZaGKCOkuxaqW9UDmjorQco3lHPNMoPQH0ZjWoucr8NovyrNhmtQnA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:28.1411 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 1eaca03a-3ce4-474a-d2ba-08dc257ab1f8 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB8131 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970540735624986 X-GMAIL-MSGID: 1789970540735624986 From: Perry Yuan Introduce AMD CPU frequency boosting control sysfs entry which used for switching boost on and boost off. If core performance boost is disabled while a core is in a boosted P-state, the core automatically transitions to the highest performance non-boosted P-state The highest perf and frequency will be limited by the setting value. Signed-off-by: Perry Yuan --- Documentation/admin-guide/pm/amd-pstate.rst | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/Documentation/admin-guide/pm/amd-pstate.rst b/Documentation/admin-guide/pm/amd-pstate.rst index 1cf40f69278c..abea29ba3d54 100644 --- a/Documentation/admin-guide/pm/amd-pstate.rst +++ b/Documentation/admin-guide/pm/amd-pstate.rst @@ -385,6 +385,17 @@ control its functionality at the system level. They are located in the to the operation mode represented by that string - or to be unregistered in the "disable" case. +``cpb_boost`` + Specifies whether core performance boost is requested to be enabled or disabled + If core performance boost is disabled while a core is in a boosted P-state, the + core automatically transitions to the highest performance non-boosted P-state. + AMD Core Performance Boost(CPB) is controlled by this new attribute file which + allow user to change all cores frequency boosting state. It supports both + ``active``, ``passive`` and ``guided`` mode control with below value write to it. + + "0" Disable Core performance Boosting + "1" Enable Core performance Boosting + ``cpupower`` tool support for ``amd-pstate`` =============================================== From patchwork Sun Feb 4 12:12:57 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Yuan, Perry" X-Patchwork-Id: 196489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:168b:b0:106:860b:bbdd with SMTP id ma11csp320385dyb; Sun, 4 Feb 2024 04:15:54 -0800 (PST) X-Google-Smtp-Source: AGHT+IFQTGHf4pyVQWKZAwzw3XmcSVAj9+7d9i5oA9U/QiWx+FweTQfNgzZjpdPjf1nV0qmILH7O X-Received: by 2002:a05:6a20:9f47:b0:19a:4418:1e86 with SMTP id ml7-20020a056a209f4700b0019a44181e86mr8648456pzb.58.1707048954086; Sun, 04 Feb 2024 04:15:54 -0800 (PST) X-Forwarded-Encrypted: i=2; AJvYcCUq/ZkXFkCC55NasEUBmSLxm2FmM50rk7Jq0sLTt7qOMGfsay/mZ0HukF2LWrFYW/B+gPgbAizfM6nTvp6bGuXJx/z/YQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Feb 2024 12:13:31.3129 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: bc7b8f1f-c431-4935-d081-08dc257ab3dc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: MN1PEPF0000ECD8.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB7733 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789970564080391614 X-GMAIL-MSGID: 1789970564080391614 With new freqency boost interface supported, legacy boost control doesn't make sense any more which only support passive mode. so it can remove the legacy set_boost interface from amd-pstate driver in case of there is conflict with new boost control logic. Signed-off-by: Perry Yuan --- drivers/cpufreq/amd-pstate.c | 1 - include/linux/amd-pstate.h | 1 - 2 files changed, 2 deletions(-) diff --git a/drivers/cpufreq/amd-pstate.c b/drivers/cpufreq/amd-pstate.c index 02a76b8fb298..4e377efdd4ed 100644 --- a/drivers/cpufreq/amd-pstate.c +++ b/drivers/cpufreq/amd-pstate.c @@ -1492,7 +1492,6 @@ static struct cpufreq_driver amd_pstate_driver = { .exit = amd_pstate_cpu_exit, .suspend = amd_pstate_cpu_suspend, .resume = amd_pstate_cpu_resume, - .set_boost = amd_pstate_set_boost, .name = "amd-pstate", .attr = amd_pstate_attr, }; diff --git a/include/linux/amd-pstate.h b/include/linux/amd-pstate.h index 446394f84606..66d939a344b1 100644 --- a/include/linux/amd-pstate.h +++ b/include/linux/amd-pstate.h @@ -80,7 +80,6 @@ struct amd_cpudata { struct amd_aperf_mperf prev; u64 freq; - bool boost_supported; /* EPP feature related attributes*/ s16 epp_policy;