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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789812778467461717 X-GMAIL-MSGID: 1789812778467461717 Document the PCIe Controllers on the X1E80100 platform. They are similar to the ones found on SM8550, but they don't have SF QTB clock. Reviewed-by: Krzysztof Kozlowski Acked-by: Manivannan Sadhasivam Signed-off-by: Abel Vesa --- .../devicetree/bindings/pci/qcom,pcie.yaml | 29 ++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml index a93ab3b54066..7381e38b7398 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml @@ -41,6 +41,7 @@ properties: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 - items: - enum: - qcom,pcie-sm8650 @@ -227,6 +228,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: properties: reg: @@ -826,6 +828,32 @@ allOf: items: - const: pci # PCIe core reset + - if: + properties: + compatible: + contains: + enum: + - qcom,pcie-x1e80100 + then: + properties: + clocks: + maxItems: 7 + clock-names: + items: + - const: aux # Auxiliary clock + - const: cfg # Configuration clock + - const: bus_master # Master AXI clock + - const: bus_slave # Slave AXI clock + - const: slave_q2a # Slave Q2A clock + - const: noc_aggr # Aggre NoC PCIe AXI clock + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock + resets: + maxItems: 2 + reset-names: + items: + - const: pci # PCIe core reset + - const: link_down # PCIe link down reset + - if: properties: compatible: @@ -884,6 +912,7 @@ allOf: - qcom,pcie-sm8450-pcie0 - qcom,pcie-sm8450-pcie1 - qcom,pcie-sm8550 + - qcom,pcie-x1e80100 then: oneOf: - properties: From patchwork Fri Feb 2 18:26:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Abel Vesa X-Patchwork-Id: 195984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:9bc1:b0:106:209c:c626 with SMTP id op1csp619844dyc; Fri, 2 Feb 2024 10:28:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IEhdgTFI9W9x/VlvA3HMwtqZAB3v6aCz1DFcVCWgdyUu6PV7bDMN9s1otHDqBG02A3y/AxK X-Received: by 2002:ac8:5a93:0:b0:42a:b346:4e10 with SMTP id c19-20020ac85a93000000b0042ab3464e10mr3397126qtc.39.1706898483401; Fri, 02 Feb 2024 10:28:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706898483; cv=pass; d=google.com; s=arc-20160816; b=tN+NQxynj2vLLLbkoi47bCrmAfWlPnZAgpUwo6Z/PvRVoYnqTUa9CnCy0YcpLSyox7 dHC44LGUVPtJOZHusW0STKTgbGuRAzoFUlWN1j4ngAwa4EH5TvBTAof7VKDzmvPcVtby dY7wVgCZypuT0+1yi/+dQV58LfuIBLcQtsB9z+25ZgrO6wM3vBA6wYYJaZbD086khFON 39SPDrfdc2+BpQMGzqCQ03uWQ5UN0Zuq9sWxaN0/H6GWx+nWU/AvF9f5vd5Es9Htf+mF NjBpc9L494tazMnFgsrbcJKa8O73sKopGsYb2+08disHP9cly2+DlAkMH+qiEIRzD+zD UgNA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=DhcdvKEbv720I24gdx4dqUT7cWiwM4tuBobtp1tISMw=; fh=w2gMXb6abTMi2bnyqymgH8Ai7/06r5SnsUqza7PXL40=; b=dgwhHS2Q3H4W/iKcGeF5J7H1myoo1K9gVuM4QWQoiGtrdfwsGqLS2kxw2/p5eeg6hd SUffBvT7ELDKAzv4LSO8Rdxeduly1JJuBNwib7MPvwXUrTakvexvd3w+ri7MCzkBzezK noLQKivE9KM9LreELL+bm/S/FrFp3pj80WDZDdxoFCnLjXAMzniU4vQGSOcyr3z1zlvS Zj/6rHVd/v7AHZld2XEdknfu4Vp/7Js5o+ggznFD+4ouddQCulrl1iV/vbXBLsmzvfNs vxWkMvipE6u0dXuMxrOBw53Iw+IvEXC/noMXraZWwkXEVuVQUx6lC5ncGMRQ938x3eUy fHpw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fuVe7HEJ; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-50324-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-50324-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org X-Forwarded-Encrypted: i=1; AJvYcCVGkMqch6ExVWH455uD6vIMUbYce+5q1iOGB/CzzhZGM3gyhH0rRSI/jarckWuWAz3hNHE0prc1VY07MRohhp2HjWU/kg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789812784391571959 X-GMAIL-MSGID: 1789812784391571959 Add the compatible and the driver data for X1E80100 PCIe controller. There are 5 controller instances found on this platform, out of which 2 are Gen3 with speeds of up to 8.0GT/s, while the other 3 are Gen4 with speeds of up to 16GT/s. The version of the controller is 1.38.0 for all instances, but they are compatible with 1.9.0 config. The max link width is x8 for one controller, x4 for two of others and x2 for the two left. Reviewed-by: Manivannan Sadhasivam Signed-off-by: Abel Vesa --- drivers/pci/controller/dwc/pcie-qcom.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 2ce2a3bd932b..b7467f9dfea9 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1642,6 +1642,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-x1e80100", .data = &cfg_1_9_0 }, { } };