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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id jx13-20020a170903138d00b001d76fb8e0a2sm574509plb.185.2024.02.01.19.58.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 19:58:49 -0800 (PST) From: Monk Chiang To: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com Cc: Monk Chiang Subject: [PATCH 1/2] RISC-V: Support scheduling for sifive p400 series Date: Fri, 2 Feb 2024 11:58:44 +0800 Message-Id: <20240202035845.112201-1-monk.chiang@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789758149731988759 X-GMAIL-MSGID: 1789758149731988759 Add sifive p400 series scheduler module. For more information see https://www.sifive.com/cores/performance-p450-470. gcc/ChangeLog: * config/riscv/riscv.md: Include sifive-p400.md. * config/riscv/sifive-p400.md: New file. * config/riscv/riscv-cores.def (RISCV_TUNE): Add parameter. * config/riscv/riscv-opts.h (enum riscv_microarchitecture_type): Add sifive_p400. * config/riscv/riscv.cc (sifive_p400_tune_info): New. * config/riscv/riscv.h (TARGET_SFB_ALU): Update. * doc/invoke.texi (RISC-V Options): Add sifive-p400-series --- gcc/config/riscv/riscv-cores.def | 1 + gcc/config/riscv/riscv-opts.h | 1 + gcc/config/riscv/riscv.cc | 17 +++ gcc/config/riscv/riscv.h | 1 + gcc/config/riscv/riscv.md | 3 +- gcc/config/riscv/sifive-p400.md | 174 +++++++++++++++++++++++++++++++ gcc/doc/invoke.texi | 4 +- 7 files changed, 198 insertions(+), 3 deletions(-) create mode 100644 gcc/config/riscv/sifive-p400.md diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index a07a79e2cb7..0785e8f3fbd 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -37,6 +37,7 @@ RISCV_TUNE("rocket", generic, rocket_tune_info) RISCV_TUNE("sifive-3-series", generic, rocket_tune_info) RISCV_TUNE("sifive-5-series", generic, rocket_tune_info) RISCV_TUNE("sifive-7-series", sifive_7, sifive_7_tune_info) +RISCV_TUNE("sifive-p400-series", sifive_p400, sifive_p400_tune_info) RISCV_TUNE("sifive-p600-series", sifive_p600, sifive_p600_tune_info) RISCV_TUNE("thead-c906", generic, thead_c906_tune_info) RISCV_TUNE("generic-ooo", generic_ooo, generic_ooo_tune_info) diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 25951665b13..4edddbadc37 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -55,6 +55,7 @@ extern enum riscv_isa_spec_class riscv_isa_spec; enum riscv_microarchitecture_type { generic, sifive_7, + sifive_p400, sifive_p600, generic_ooo }; diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index cead76fe1a2..4b24e4b9a0a 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -447,6 +447,23 @@ static const struct riscv_tune_param sifive_7_tune_info = { NULL, /* vector cost */ }; +/* Costs to use when optimizing for Sifive p400 Series. */ +static const struct riscv_tune_param sifive_p400_tune_info = { + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */ + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_mul */ + {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ + {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ + {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ + 3, /* issue_rate */ + 4, /* branch_cost */ + 3, /* memory_cost */ + 4, /* fmv_cost */ + true, /* slow_unaligned_access */ + false, /* use_divmod_expansion */ + RISCV_FUSE_LUI_ADDI | RISCV_FUSE_AUIPC_ADDI, /* fusible_ops */ + &generic_vector_cost, /* vector cost */ +}; + /* Costs to use when optimizing for Sifive p600 Series. */ static const struct riscv_tune_param sifive_p600_tune_info = { {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* fp_add */ diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index e0cb3ba08d4..669308cc96d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -898,6 +898,7 @@ extern enum riscv_cc get_riscv_cc (const rtx use); #define TARGET_SFB_ALU \ ((riscv_microarchitecture == sifive_7) \ + || (riscv_microarchitecture == sifive_p400) \ || (riscv_microarchitecture == sifive_p600)) #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 2a164a03dbd..39b29795cd6 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -687,7 +687,7 @@ ;; Microarchitectures we know how to tune for. ;; Keep this in sync with enum riscv_microarchitecture. (define_attr "tune" - "generic,sifive_7,sifive_p600,generic_ooo" + "generic,sifive_7,sifive_p400,sifive_p600,generic_ooo" (const (symbol_ref "((enum attr_tune) riscv_microarchitecture)"))) ;; Describe a user's asm statement. @@ -3850,6 +3850,7 @@ (include "pic.md") (include "generic.md") (include "sifive-7.md") +(include "sifive-p400.md") (include "sifive-p600.md") (include "thead.md") (include "generic-ooo.md") diff --git a/gcc/config/riscv/sifive-p400.md b/gcc/config/riscv/sifive-p400.md new file mode 100644 index 00000000000..cc244d3c3e6 --- /dev/null +++ b/gcc/config/riscv/sifive-p400.md @@ -0,0 +1,174 @@ +;; Scheduling description for Sifive p400. + +;; Sifive p400 series is a triple-issue, superscalar, out-of-order processor. + +;; CPU execution units: +;; ialu Integer Units: all arithmetic and logic. +;; +;; bru Branch Resolution Unit: all branches. +;; +;; st Memory Write Unit: all writes to memory. +;; +;; ld Memory Read Unit: all reads from memory. +;; +;; imul Integer Multiply Unit +;; +;; idiv Integer Divide Unit +;; +;; system System Unit: all coprocessor accesses. +;; +;; fpu Floating Point Unit +;; +;; fmul Floating Point Multiply Unit +;; +;; fdiv Floating Point Divide Unit + +;; Four automata are defined to reduce number of states +;; which a single large automaton will have. +(define_automaton "sifive_p400_iex,sifive_p400_fex,sifive_p400_mem,sifive_p400_div") + +;; The Sifive p400 has six pipelines: +;; A-pipe Load, Store +;; B-pipe ALU, Branch +;; M-pipe ALU, MUL, DIV and I2F(integer to float instruction) +;; C-pipe ALU, Conditional move and system for coprocessor accesses +;; F-pipe FPU, MUL, F2I(float to integer instruction) +;; FM-pipe FPU, MUL, DIV + +(define_cpu_unit "sifive_p400_A" "sifive_p400_mem") +(define_cpu_unit "sifive_p400_B" "sifive_p400_iex") +(define_cpu_unit "sifive_p400_M" "sifive_p400_iex") +(define_cpu_unit "sifive_p400_C" "sifive_p400_iex") +(define_cpu_unit "sifive_p400_F" "sifive_p400_fex") +(define_cpu_unit "sifive_p400_FM" "sifive_p400_fex") + +;; Load and store unit. +(define_cpu_unit "sifive_p400_ld" "sifive_p400_mem") +(define_cpu_unit "sifive_p400_st" "sifive_p400_mem") + +;; Branch unit. +(define_cpu_unit "sifive_p400_bru" "sifive_p400_iex") + +;; Integer and multiply unit. +(define_cpu_unit "sifive_p400_ialu" "sifive_p400_iex") +(define_cpu_unit "sifive_p400_imul" "sifive_p400_iex") +(define_cpu_unit "sifive_p400_system" "sifive_p400_iex") + +;; Divide unit. +(define_cpu_unit "sifive_p400_idiv" "sifive_p400_div") +(define_cpu_unit "sifive_p400_fdiv" "sifive_p400_div") + +;; Float and multiply unit. +(define_cpu_unit "sifive_p400_fmul" "sifive_p400_fex") +(define_cpu_unit "sifive_p400_fpu" "sifive_p400_fex") + +;; ALU instruction can use pipeline C, B and M. +(define_reservation "p400_int_pipe" "(sifive_p400_C|sifive_p400_B|sifive_p400_M)") +;; FPU instruction can use pipeline F and FM. +(define_reservation "p400_float_pipe" "(sifive_p400_F|sifive_p400_FM)") + +(define_insn_reservation "sifive_p400_load" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "load")) + "sifive_p400_A,sifive_p400_ld*2") + +(define_insn_reservation "sifive_p400_fpload" 4 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fpload")) + "sifive_p400_A,sifive_p400_ld*3") + +(define_insn_reservation "sifive_p400_store" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "store")) + "sifive_p400_A+sifive_p400_st") + +(define_insn_reservation "sifive_p400_fpstore" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fpstore")) + "sifive_p400_A+sifive_p400_st") + +(define_insn_reservation "sifive_p400_branch" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "branch,jump,call")) + "sifive_p400_B+sifive_p400_bru") + +(define_insn_reservation "sifive_p400_sfb_alu" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "sfb_alu")) + "sifive_p400_C+sifive_p400_bru+sifive_p400_ialu") + +(define_insn_reservation "sifive_p400_atomic" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "atomic")) + "sifive_p400_C,sifive_p400_system*2") + +(define_insn_reservation "sifive_p400_mul" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "imul")) + "sifive_p400_M,sifive_p400_imul*2") + +(define_insn_reservation "sifive_p400_div" 31 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "idiv")) + "sifive_p400_M, sifive_p400_idiv*5") + +(define_insn_reservation "sifive_p400_alu" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "unknown,arith,logical,shift,slt,multi,bitmanip,clz,ctz,rotate")) + "p400_int_pipe+sifive_p400_ialu") + +(define_insn_reservation "sifive_p400_cpop" 3 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "cpop")) + "p400_int_pipe,sifive_p400_ialu*2") + +(define_insn_reservation "sifive_p400_load_immediate" 1 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "nop,const,auipc,move")) + "p400_int_pipe") + +(define_insn_reservation "sifive_p400_fma" 4 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fadd,fmul,fmadd")) + "p400_float_pipe,sifive_p400_fmul*3") + +(define_insn_reservation "sifive_p400_i2f" 2 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "mtc,fcvt_i2f")) + "sifive_p400_M,sifive_p400_ialu") + +(define_insn_reservation "sifive_p400_f2i" 2 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "mfc,fcmp,fcvt_f2i")) + "sifive_p400_F,sifive_p400_fpu") + +(define_insn_reservation "sifive_p400_fmove" 2 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fmove,fcvt")) + "p400_float_pipe,sifive_p400_fpu") + +(define_insn_reservation "sifive_p400_fdiv_s" 18 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "SF")) + "sifive_p400_FM, sifive_p400_fdiv*5") + +(define_insn_reservation "sifive_p400_fdiv_d" 31 + (and (eq_attr "tune" "sifive_p400") + (eq_attr "type" "fdiv,fsqrt") + (eq_attr "mode" "DF")) + "sifive_p400_FM, sifive_p400_fdiv*5") + +(define_bypass 1 "sifive_p400_load,sifive_p400_alu,sifive_p400_mul,sifive_p400_sfb_alu" + "sifive_p400_alu,sifive_p400_branch") + +(define_bypass 1 "sifive_p400_load,sifive_p400_alu,sifive_p400_mul, + sifive_p400_f2i,sifive_p400_fmove,sifive_p400_sfb_alu" + "sifive_p400_store" "riscv_store_data_bypass_p") + +(define_bypass 1 "sifive_p400_i2f" + "sifive_p400_fma,sifive_p400_f2i,sifive_p400_fmove,sifive_p400_fdiv_s,sifive_p400_fdiv_d") + +(define_bypass 1 "sifive_p400_f2i" + "sifive_p400_branch,sifive_p400_sfb_alu,sifive_p400_mul, + sifive_p400_div,sifive_p400_alu,sifive_p400_cpop") diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index e9c691d63da..f8645822ca4 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30714,8 +30714,8 @@ Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, Optimize the output for the given processor, specified by microarchitecture or particular CPU name. Permissible values for this option are: @samp{rocket}, @samp{sifive-3-series}, @samp{sifive-5-series}, @samp{sifive-7-series}, -@samp{thead-c906}, @samp{size}, @samp{sifive-p600-series}, -and all valid options for @option{-mcpu=}. +@samp{thead-c906}, @samp{size}, @samp{sifive-p400-series}, +@samp{sifive-p600-series}, and all valid options for @option{-mcpu=}. When @option{-mtune=} is not specified, use the setting from @option{-mcpu}, the default is @samp{rocket} if both are not specified. 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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id jx13-20020a170903138d00b001d76fb8e0a2sm574509plb.185.2024.02.01.19.58.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 19:58:51 -0800 (PST) From: Monk Chiang To: gcc-patches@gcc.gnu.org, kito.cheng@sifive.com Cc: Monk Chiang Subject: [PATCH 2/2] RISC-V: Add sifive-p450, sifive-p67 to -mcpu Date: Fri, 2 Feb 2024 11:58:45 +0800 Message-Id: <20240202035845.112201-2-monk.chiang@sifive.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20240202035845.112201-1-monk.chiang@sifive.com> References: <20240202035845.112201-1-monk.chiang@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789758150548837126 X-GMAIL-MSGID: 1789758150548837126 gcc/ChangeLog: * config/riscv/riscv-cores.def: Add sifive-p450, sifive-p670. * doc/invoke.texi (RISC-V Options): Add sifive-p450, sifive-p670. gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-sifive-p450.c: New test. * gcc.target/riscv/mcpu-sifive-p670.c: New test. --- gcc/config/riscv/riscv-cores.def | 9 +++++ gcc/doc/invoke.texi | 3 +- .../gcc.target/riscv/mcpu-sifive-p450.c | 34 ++++++++++++++++ .../gcc.target/riscv/mcpu-sifive-p670.c | 40 +++++++++++++++++++ 4 files changed, 85 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 0785e8f3fbd..57928bccdc8 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -76,6 +76,15 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-x280", "rv64imafdcv_zfh_zba_zbb_zvfh_zvl512b", "sifive-7-series") +RISCV_CORE("sifive-p450", "rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs", + "sifive-p400-series") +RISCV_CORE("sifive-p670", "rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_" + "ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_" + "zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_" + "zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg", + "sifive-p600-series") RISCV_CORE("thead-c906", "rv64imafdc_xtheadba_xtheadbb_xtheadbs_xtheadcmo_" "xtheadcondmov_xtheadfmemidx_xtheadmac_" diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index f8645822ca4..71339b8b30f 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -30707,7 +30707,8 @@ by particular CPU name. Permissible values for this option are: @samp{sifive-e20}, @samp{sifive-e21}, @samp{sifive-e24}, @samp{sifive-e31}, @samp{sifive-e34}, @samp{sifive-e76}, @samp{sifive-s21}, @samp{sifive-s51}, @samp{sifive-s54}, @samp{sifive-s76}, -@samp{sifive-u54}, @samp{sifive-u74}, and @samp{sifive-x280}. +@samp{sifive-u54}, @samp{sifive-u74}, @samp{sifive-x280}, @samp{sifive-xp450}, +@samp{sifive-x670}. @opindex mtune @item -mtune=@var{processor-string} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c new file mode 100644 index 00000000000..563041821e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p450.c @@ -0,0 +1,34 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=sifive-p450 -mabi=lp64d" } */ +/* SiFive p450 => rv64imafdc_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_c) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbs)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c new file mode 100644 index 00000000000..8dfd490f440 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-sifive-p670.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=sifive-p670 -mabi=lp64d" } */ +/* SiFive p670 => rv64imafdcv_za64rs_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_zicsr_zifencei_zihintntl_zihintpause_zihpm_zfhmin_zba_zbb_zbs_zvl128b_zvbb_zvknc_zvkng_zvksc_zvksg */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && (__riscv_flen == 64) \ + && defined(__riscv_c) \ + && defined(__riscv_za64rs) \ + && defined(__riscv_zic64b) \ + && defined(__riscv_zicbom) \ + && defined(__riscv_zicbop) \ + && defined(__riscv_zicboz) \ + && defined(__riscv_ziccamoa) \ + && defined(__riscv_ziccif) \ + && defined(__riscv_zicclsm) \ + && defined(__riscv_ziccrse) \ + && defined(__riscv_zicsr) \ + && defined(__riscv_zifencei) \ + && defined(__riscv_zihintntl) \ + && defined(__riscv_zihintpause) \ + && defined(__riscv_zihpm) \ + && defined(__riscv_zfhmin) \ + && defined(__riscv_zba) \ + && defined(__riscv_zbb) \ + && defined(__riscv_zbs) \ + && defined(__riscv_zvl128b) \ + && defined(__riscv_zvbb) \ + && defined(__riscv_zvknc) \ + && defined(__riscv_zvkng) \ + && defined(__riscv_zvksc) \ + && defined(__riscv_zvksg)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}