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Thu, 01 Feb 2024 10:30:26 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCWPxLRHwJnG71yuUhivG/Ed9sMCzqJ70Kw/+v8sZgZcIEeNLyMLrW3BuRXquOnPRHJS21n4dMXUsBLAf/JZhzoVGMYa9cZxe6zp/zj+a7dJJJjK4QtwVLeHhvDkZCTWEuBaMaK9mti9c+Dk5U1++pslPZCmyi3PiaOD7sejkZIxDMYaDHqN45hY3cy3Fcwb1CvMdzwbjeQtooVc/2ykAg2P+u5ETT22RvAxxQ3u/7sGetw= Received: from localhost ([136.62.192.75]) by smtp.gmail.com with ESMTPSA id z5-20020a05683008c500b006e11d2e358bsm56737otg.40.2024.02.01.10.30.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 10:30:26 -0800 (PST) From: Sam Protsenko To: Krzysztof Kozlowski Cc: Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v3] arm64: dts: exynos: Add SPI nodes for Exynos850 Date: Thu, 1 Feb 2024 12:30:25 -0600 Message-Id: <20240201183025.14566-1-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789024601824286315 X-GMAIL-MSGID: 1789724012884463987 Some USI blocks can be configured as SPI controllers. Add corresponding SPI nodes to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko Reviewed-by: Tudor Ambarus Link: https://lore.kernel.org/r/20240125013858.3986-4-semen.protsenko@linaro.org [krzysztof: order properties according to DTS coding style] Signed-off-by: Krzysztof Kozlowski --- Changes in v3: - Fix dtschema warnings by specifying "spi" as a first clock Changes in v2: - Sorted pinctrl properties properly arch/arm64/boot/dts/exynos/exynos850.dtsi | 54 +++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index e7e1171a3864..2ba67c3d0681 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -738,6 +738,24 @@ usi_spi_0: usi@139400c0 { <&cmu_peri CLK_GOUT_SPI0_IPCLK>; clock-names = "pclk", "ipclk"; status = "disabled"; + + spi_0: spi@13940000 { + compatible = "samsung,exynos850-spi"; + reg = <0x13940000 0x30>; + clocks = <&cmu_peri CLK_GOUT_SPI0_PCLK>, + <&cmu_peri CLK_GOUT_SPI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 5>, <&pdma0 4>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi0_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp0: usi@11d000c0 { @@ -779,6 +797,24 @@ serial_1: serial@11d00000 { clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_1: spi@11d00000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d00000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI0_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI0_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 12>, <&pdma0 13>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi1_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; usi_cmgp1: usi@11d200c0 { @@ -820,6 +856,24 @@ serial_2: serial@11d20000 { clock-names = "uart", "clk_uart_baud0"; status = "disabled"; }; + + spi_2: spi@11d20000 { + compatible = "samsung,exynos850-spi"; + reg = <0x11d20000 0x30>; + clocks = <&cmu_cmgp CLK_GOUT_CMGP_USI1_PCLK>, + <&cmu_cmgp CLK_GOUT_CMGP_USI1_IPCLK>; + clock-names = "spi", "spi_busclk0"; + dmas = <&pdma0 14>, <&pdma0 15>; + dma-names = "tx", "rx"; + interrupts = ; + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + num-cs = <1>; + samsung,spi-src-clk = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; }; }; };