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(fttx-pool-217.61.148.248.bambit.de [217.61.148.248]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id 07579406E6; Thu, 1 Feb 2024 18:24:16 +0000 (UTC) From: Frank Wunderlich To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Frank Wunderlich , Sam Shih , Daniel Golle , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, Conor Dooley Subject: [PATCH v4 1/2] dt-bindings: reset: mediatek: add MT7988 infracfg reset IDs Date: Thu, 1 Feb 2024 19:24:08 +0100 Message-Id: <20240201182409.39878-2-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201182409.39878-1-linux@fw-web.de> References: <20240201182409.39878-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mail-ID: f86ec7b2-db69-458e-813c-2cef7dd7b5cc X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789724223991944066 X-GMAIL-MSGID: 1789724223991944066 From: Frank Wunderlich Add reset constants for using as index in driver and dts. Value is starting again from 0 because resets are used in another device than existing constants. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley --- v4: - add info about restarting ids from 0 to commit message v3: - add pcie reset id as suggested by angelo v2: - add missing commit message and SoB - change value of infrareset to 0 --- include/dt-bindings/reset/mediatek,mt7988-resets.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/dt-bindings/reset/mediatek,mt7988-resets.h b/include/dt-bindings/reset/mediatek,mt7988-resets.h index 493301971367..0eb152889a89 100644 --- a/include/dt-bindings/reset/mediatek,mt7988-resets.h +++ b/include/dt-bindings/reset/mediatek,mt7988-resets.h @@ -10,4 +10,10 @@ /* ETHWARP resets */ #define MT7988_ETHWARP_RST_SWITCH 0 +/* INFRA resets */ +#define MT7988_INFRA_RST0_PEXTP_MAC_SWRST 0 +#define MT7988_INFRA_RST1_THERM_CTRL_SWRST 1 + + #endif /* _DT_BINDINGS_RESET_CONTROLLER_MT7988 */ + From patchwork Thu Feb 1 18:24:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Wunderlich X-Patchwork-Id: 195436 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2719:b0:106:209c:c626 with SMTP id hl25csp366315dyb; Thu, 1 Feb 2024 10:38:13 -0800 (PST) X-Google-Smtp-Source: AGHT+IFeTH81JOGi6ADBfTgYCELYLjNGdGtXnECHBcZmFdZs7O/m2dbxu1dH6E6RiNSdvZnDMWvW X-Received: by 2002:a05:6a20:968a:b0:19c:9eea:e731 with SMTP id hp10-20020a056a20968a00b0019c9eeae731mr5014342pzc.40.1706812693551; Thu, 01 Feb 2024 10:38:13 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706812693; cv=pass; d=google.com; s=arc-20160816; b=H0529OfKWIFIgkUVtlhkG2tWbFbKv+WEU7txMl/sx27OghrViO9OQH9/nw+Hv9p+do jchTwq5P3A5mZm9v8ZOJvEc3mhVZp0wOy5mhpVgse7fhZemn6flwF9OSb+pXeamZdiLe 8QLcOUJqgsOk8No4ulRZ6wkafOvq0aconVo19OHHbYWTiZ1UX2WQCgUhoHXurVDO/wRT F0C2pg6VZkQhEhTJT8db0zpcMsTTzIBHIK9v+RAxpoMR+yO2wa27Gv+KFvAtgjHzZ3T2 8UPrBE4+chAiWIaCUomo8cQJgF+PII7Xn+C0fnUIId515ag3WAPldFS82n+zgzWRJ7+e O3Kw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jawm/pvTHWX0WYgxucSztSNdUiVaRemAzUoNvh+bK2k=; fh=EVAYwmfiVUDvOkwODbVnw2sMnxDb8UfqyeNxwDQpKeg=; b=nOkv9v+8gOL2n+jZW2KuDBk8W47AF8V8qIsxFqTCIpcHBtJLrcQJcT2+2aLF1haLEz 4JP0PRgToUcY2v2Jmbuk7aH1OhxTQCC06PeUNSkylQEqLMjFRlGGDSg4Qifxb7QfwfIb NaKUSURxzMzwphYuTNmXR0ga2ajtbRS4ToVVinQJhI7jm3O+Jh9v1V50iNMBDftT0FXd vvSJr/RqAZMcpiIj6CUc7UFcD0vAvQ9Ie495uA8tL7MxVS30t3Pmsra6OnRxthXBpLCe OhMMfSupk4QJYYA+0I2xhpeA2BLtrmPJxIge7KG5pfeAwfwz2YNA1OyhEUPKqdkQGlOX oUGg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@mailerdienst.de header.s=20200217 header.b=eGCnhr4H; arc=pass (i=1 spf=pass spfdomain=fw-web.de dkim=pass dkdomain=mailerdienst.de); spf=pass (google.com: domain of linux-kernel+bounces-48706-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48706-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=1; AJvYcCUP2xuq+r4Eyk7+m84Bx5G58JmT78QJVVyo0cF5PUtPKwfN5JFwQ2QGrV7WCu40raxG8psPKUo87P0XRimew5r0n64fpA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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(fttx-pool-217.61.148.248.bambit.de [217.61.148.248]) by mxbox1.masterlogin.de (Postfix) with ESMTPSA id D30CC40533; Thu, 1 Feb 2024 18:24:16 +0000 (UTC) From: Frank Wunderlich To: Michael Turquette , Stephen Boyd , Matthias Brugger , AngeloGioacchino Del Regno , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Frank Wunderlich , Sam Shih , Daniel Golle , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v4 2/2] clk: mediatek: add infracfg reset controller for mt7988 Date: Thu, 1 Feb 2024 19:24:09 +0100 Message-Id: <20240201182409.39878-3-linux@fw-web.de> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240201182409.39878-1-linux@fw-web.de> References: <20240201182409.39878-1-linux@fw-web.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Mail-ID: 55057060-11c3-4130-9e0b-b79a9f6df589 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789722827105044926 X-GMAIL-MSGID: 1789722827105044926 From: Frank Wunderlich Infracfg can also operate as reset controller, add support for it. Signed-off-by: Frank Wunderlich Reviewed-by: AngeloGioacchino Del Regno --- v4: unchanged v3: - start with RST0 (LVTS is in RST1) - rename reset offset to contain SOC to not collide with constants defined in reset.h --- drivers/clk/mediatek/clk-mt7988-infracfg.c | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/mediatek/clk-mt7988-infracfg.c b/drivers/clk/mediatek/clk-mt7988-infracfg.c index 8011ef278bea..449041f8abbc 100644 --- a/drivers/clk/mediatek/clk-mt7988-infracfg.c +++ b/drivers/clk/mediatek/clk-mt7988-infracfg.c @@ -14,6 +14,10 @@ #include "clk-gate.h" #include "clk-mux.h" #include +#include + +#define MT7988_INFRA_RST0_SET_OFFSET 0x70 +#define MT7988_INFRA_RST1_SET_OFFSET 0x80 static DEFINE_SPINLOCK(mt7988_clk_lock); @@ -249,12 +253,31 @@ static const struct mtk_gate infra_clks[] = { GATE_INFRA3(CLK_INFRA_133M_PCIE_CK_P3, "infra_133m_pcie_ck_p3", "sysaxi_sel", 31), }; +static u16 infra_rst_ofs[] = { + MT7988_INFRA_RST0_SET_OFFSET, + MT7988_INFRA_RST1_SET_OFFSET, +}; + +static u16 infra_idx_map[] = { + [MT7988_INFRA_RST0_PEXTP_MAC_SWRST] = 0 * RST_NR_PER_BANK + 6, + [MT7988_INFRA_RST1_THERM_CTRL_SWRST] = 1 * RST_NR_PER_BANK + 9, +}; + +static struct mtk_clk_rst_desc infra_rst_desc = { + .version = MTK_RST_SET_CLR, + .rst_bank_ofs = infra_rst_ofs, + .rst_bank_nr = ARRAY_SIZE(infra_rst_ofs), + .rst_idx_map = infra_idx_map, + .rst_idx_map_nr = ARRAY_SIZE(infra_idx_map), +}; + static const struct mtk_clk_desc infra_desc = { .clks = infra_clks, .num_clks = ARRAY_SIZE(infra_clks), .mux_clks = infra_muxes, .num_mux_clks = ARRAY_SIZE(infra_muxes), .clk_lock = &mt7988_clk_lock, + .rst_desc = &infra_rst_desc, }; static const struct of_device_id of_match_clk_mt7988_infracfg[] = {