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[2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id o12-20020ac87c4c000000b0042be8dbb129si27038qtv.166.2024.02.01.10.12.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 10:12:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-48662-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=christina-quast.de); spf=pass (google.com: domain of linux-kernel+bounces-48662-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48662-ouuuleilei=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id D56A91C29F0C for ; Thu, 1 Feb 2024 18:11:39 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id D408B12E1DB; Thu, 1 Feb 2024 18:07:20 +0000 (UTC) Received: from mail.someserver.de (mail.someserver.de [116.202.193.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8050884FC5; Thu, 1 Feb 2024 18:07:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.193.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810839; cv=none; b=lhmOxoCR6j9xG30P71NDE43OYBogv2Sahw1MOflrNVBGKJdHjP9u/7HaCQB40l1wMp4f/eEel5S2anzX3vgJJlwUwB8HnJh0nRBNUOsU7Soun0NS2sO2N5JALXZEdz8gayxJEcsFv9QZ+tQAjVF6aHOGJ/vYimuKbflChKlQsqo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810839; c=relaxed/simple; bh=I9yo8gFF9g6Nktp5khK01f/99bXfCpCeui/xCrTFEX0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jaeqw0/DX8LyMACjAD6mrdbcIz4pYRKBWCFCG3ZBMpXtzxZ9FtnUyN2ofn6v7Q3NXiKnBrpozmsSo97HYZF5ECKasOAPURAIUCzpbLqGmW400oBpq8qj55DrKRWncVNAg6px67UKO37LRd50tBJQ/Lw6C6KzLMagDv0SnbtIRkw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de; spf=pass smtp.mailfrom=christina-quast.de; arc=none smtp.client-ip=116.202.193.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=christina-quast.de Received: from localhost (unknown [195.162.191.218]) by mail.someserver.de (Postfix) with ESMTPSA id 2965DA21AE; Thu, 1 Feb 2024 19:07:13 +0100 (CET) From: Christina Quast Date: Thu, 01 Feb 2024 19:06:58 +0100 Subject: [PATCH v2 1/3] DONOTMERGE: rust: prelude: add bit function Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240201-rockchip-rust-phy_depend-v2-1-c5fa4faab924@christina-quast.de> References: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> In-Reply-To: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> To: Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , FUJITA Tomonori , Trevor Gross , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiko Stuebner Cc: rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Christina Quast X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706810819; l=1166; i=contact@christina-quast.de; s=20240130; h=from:subject:message-id; bh=I9yo8gFF9g6Nktp5khK01f/99bXfCpCeui/xCrTFEX0=; b=PD/auZkWvS/a6RAELm9LZMt+cqhgGaqOca8QQUD5tdAWmf0dbh8OFZXYaJmqZgB58v2xzsXPY 6aq5k52d6jBD1X+2SRUI45jUSSAeNaaKZovXt/2kXeZa7O2MuqHekKw X-Developer-Key: i=contact@christina-quast.de; a=ed25519; pk=aoQfinjbnr265vCkIZdYteLDcmIqLBhY1m74WfFUU9E= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789721185352118387 X-GMAIL-MSGID: 1789721185352118387 In order to create masks easily, the define BIT() is used in C code. This commit adds the same functionality to the rust kernel. Do not merge this commit, because rust/kernel/types.rs in Rust-for-Linux already contains this functionality and will be merged into next-net soon. But this driver does not compile without this commit, so I am adding it to the patchset to get more feedback on the actual driver. Signed-off-by: Christina Quast --- rust/kernel/prelude.rs | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/rust/kernel/prelude.rs b/rust/kernel/prelude.rs index ae21600970b3..16e483de2f27 100644 --- a/rust/kernel/prelude.rs +++ b/rust/kernel/prelude.rs @@ -38,3 +38,19 @@ pub use super::init::{InPlaceInit, Init, PinInit}; pub use super::current; + +/// Returns a `u32` number that has only the `n`th bit set. +/// +/// # Arguments +/// +/// * `n` - A `u32` that specifies the bit position (zero-based index) +/// +/// # Example +/// +/// ``` +/// let b = bit(2); +/// assert_eq!(b, 4); +#[inline] +pub const fn bit(n: u32) -> u32 { + 1 << n +} From patchwork Thu Feb 1 18:06:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christina Quast X-Patchwork-Id: 195427 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2719:b0:106:209c:c626 with SMTP id hl25csp346532dyb; Thu, 1 Feb 2024 10:12:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IHvGjF3GvkGMFTe7Qr7ru6W6nAs07dn5iNzGwyRTPIAbfNSA7Rq3rTnByiYJWOroS49cbcs X-Received: by 2002:a17:903:445:b0:1d9:5ef2:abdd with SMTP id iw5-20020a170903044500b001d95ef2abddmr1055511plb.0.1706811124168; Thu, 01 Feb 2024 10:12:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706811124; cv=pass; d=google.com; s=arc-20160816; b=oBvZI6LBa3LoN5D5mYm3m8Mpk8PnVgzVe31iVnn1634TjH2ut08FPmMF6vO5i9HWJb cDqY5/SQnjz7tDe4PyODiK5kR+dpJunnbgVPI1zBF5zh1YKlsbE6H68p49oGjYzDTKWT NIAb3p2MkXq1VTUf5brAkdt1KncQd9NRdv0gtCKfodc+zSlCCmL7gyJfhykIiABbuj4K 9qJ0h4GLzLvhrn+S+J4YO5KA+PX//HKnHveSIcTYZ9iTXIRQUB2D44DJBT0P+FMSdpoI RdrLFS0aq6jvQu++hXId9FmBb3JblnQVt9cw0j5+AZv9TlVobTUbWcJo082+vuwpSXUG Armw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from; bh=rOGJnW1Y3sstBbNLAHZIrTq5TeNI341gGvKrgGutEOM=; fh=Pcd3UrSyAeDLAEZ7a5WrgAThGo2hSbGD6wbAigO4HKk=; b=TIgcpI+NfoHDiDCwBhmnoDK3grK4ZsxoRn8XYd5e8SvYhBnOG4sGhVj3dI2qPZ/221 t8WIH+cKsmH7FBQIzrscYw3oKJ26+tTYr6k+yX5XdqPzYK7DImBhPE3DbM2P+R8Uu0aT jiXgX3U2q1nP8aeqOU+uGMfDESLKntWVaL0akvtIz8t1lOaNTp1VHyxawevRj+O+/tCI nO7LzeV7YhimSze7nnFFcLdHQx2VTs0qxTGlxBltGwTiekytAlFaTBys5wc7bTV+Fsf2 EYMdKPZf4zMT9orcgG9T2evgrYYnV7oQd0UpwI/n/7l5+XVte6Eq9OzDLlihk7Q9x99h FRJg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=christina-quast.de); spf=pass (google.com: domain of linux-kernel+bounces-48664-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48664-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=1; AJvYcCW55ZCpqbRdzmrbNPkCRMszxAlYoGeypKBRLs7oyuo08HQCW6/pERo4mH7JEN9rWTyl1PZe+U35KnRoUcKFaSMkTn3MHA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id t11-20020a170902bc4b00b001d8c8b6693fsi179292plz.382.2024.02.01.10.12.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 10:12:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-48664-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=christina-quast.de); spf=pass (google.com: domain of linux-kernel+bounces-48664-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48664-ouuuleilei=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id E948929AF17 for ; Thu, 1 Feb 2024 18:12:03 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 45E1112FB19; Thu, 1 Feb 2024 18:07:22 +0000 (UTC) Received: from mail.someserver.de (mail.someserver.de [116.202.193.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 92BD912D162; Thu, 1 Feb 2024 18:07:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.193.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810840; cv=none; b=pkILYfYFNi0HBtzkjay0rnbJ49sWc9EiexE1DD7dIAD1mP6LVy2qKllt2t8B6LPWYikpQuwaBc85tJhBlokfX7Qy6cBwjVWFNzU4jhf9x/3WEOhZovTcs3va2vn91zNqiaH+8Z+6YzTtT05+qR19H6ANVQ9rOlHcprWgbWbGAmM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810840; c=relaxed/simple; bh=lj9jzLLyVHFhew0Zi2auFkzyMGCjvKyZGt3bltSvs9k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k4VGjZ2pnk5iCCMCGeMU/0p8uDuMlUNDG+fSbj1/PQD184tSW0/7JrDGfNpzKZ5e6So9D27to0iNNLujv5e8d4y/29D/G7ZW3YPjsOJ6qLgouAXGOQh+Yqpz6hMXcA02pCG4k7IwLSi+e7Bm/y0QZ3M6EUsPGDPraGB1X2T1pJU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de; spf=pass smtp.mailfrom=christina-quast.de; arc=none smtp.client-ip=116.202.193.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=christina-quast.de Received: from localhost (unknown [195.162.191.218]) by mail.someserver.de (Postfix) with ESMTPSA id 8B6DAA2250; Thu, 1 Feb 2024 19:07:15 +0100 (CET) From: Christina Quast Date: Thu, 01 Feb 2024 19:06:59 +0100 Subject: [PATCH v2 2/3] rust: phy: add some phy_driver and genphy_ functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240201-rockchip-rust-phy_depend-v2-2-c5fa4faab924@christina-quast.de> References: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> In-Reply-To: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> To: Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , FUJITA Tomonori , Trevor Gross , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiko Stuebner Cc: rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Christina Quast X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706810819; l=2422; i=contact@christina-quast.de; s=20240130; h=from:subject:message-id; bh=lj9jzLLyVHFhew0Zi2auFkzyMGCjvKyZGt3bltSvs9k=; b=aBY8aB9sq9C6dAXsUFZ7GKm0DaKOL3Rg4HPRhXog0o3VGGiSAUmMpGA4nPU0r6SNJlN/kCQ8Q 6lt+pqrQgCmB3oQRdIWJxLCdbPCslYHVrYtUjsrYQoPoH+xjpDn+Imd X-Developer-Key: i=contact@christina-quast.de; a=ed25519; pk=aoQfinjbnr265vCkIZdYteLDcmIqLBhY1m74WfFUU9E= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789721180999921496 X-GMAIL-MSGID: 1789721180999921496 Those functions are need for the rockchip_rust.rs implementation. Added functions: genphy_config_aneg config_init Getter functions for mdix and speed. Signed-off-by: Christina Quast --- rust/kernel/net/phy.rs | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/rust/kernel/net/phy.rs b/rust/kernel/net/phy.rs index e457b3c7cb2f..373a4d358e9f 100644 --- a/rust/kernel/net/phy.rs +++ b/rust/kernel/net/phy.rs @@ -95,6 +95,22 @@ pub fn phy_id(&self) -> u32 { unsafe { (*phydev).phy_id } } + /// Gets the current crossover of the PHY. + pub fn mdix(&self) -> u8 { + let phydev = self.0.get(); + // SAFETY: The struct invariant ensures that we may access + // this field without additional synchronization. + unsafe { (*phydev).mdix } + } + + /// Gets the speed of the PHY. + pub fn speed(&mut self) -> u32 { + let phydev = self.0.get(); + // SAFETY: The struct invariant ensures that we may access + // this field without additional synchronization. + unsafe { (*phydev).speed as u32 } + } + /// Gets the state of PHY state machine states. pub fn state(&self) -> DeviceState { let phydev = self.0.get(); @@ -300,6 +316,15 @@ pub fn genphy_read_abilities(&mut self) -> Result { // So it's just an FFI call. to_result(unsafe { bindings::genphy_read_abilities(phydev) }) } + + /// Writes BMCR + pub fn genphy_config_aneg(&mut self) -> Result { + let phydev = self.0.get(); + // SAFETY: `phydev` is pointing to a valid object by the type invariant of `Self`. + // So it's just an FFI call. + // second param = false => autoneg not requested + to_result(unsafe { bindings::__genphy_config_aneg(phydev, false) }) + } } /// Defines certain other features this PHY supports (like interrupts). @@ -583,6 +608,12 @@ fn soft_reset(_dev: &mut Device) -> Result { Err(code::ENOTSUPP) } + /// Called to initialize the PHY, + /// including after a reset + fn config_init(_dev: &mut Device) -> Result { + Err(code::ENOTSUPP) + } + /// Probes the hardware to determine what abilities it has. fn get_features(_dev: &mut Device) -> Result { Err(code::ENOTSUPP) From patchwork Thu Feb 1 18:07:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christina Quast X-Patchwork-Id: 195429 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2719:b0:106:209c:c626 with SMTP id hl25csp347042dyb; Thu, 1 Feb 2024 10:12:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IG0uplMYHEXLrKO0o/rJcOYChtZRINrQEvPk0cL8tnv1pnPbGRd0u8ZrQqZ5Oinz7SLiX9x X-Received: by 2002:a50:8e56:0:b0:55f:e682:c933 with SMTP id 22-20020a508e56000000b0055fe682c933mr52522edx.12.1706811154775; Thu, 01 Feb 2024 10:12:34 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706811154; cv=pass; d=google.com; s=arc-20160816; b=sr4N5pPNKcI626uvYmjS0W6VLhLCg6tJNZsC/bkBe63oAnsudkKuBI4z8hCYPOi+Xw vvazfbnSCMPhVCCnes+O4x9pARAEqcY7wE8GdzaIWFivjEysFhoYZcIEqY8OH13YYi7n fAOyPncoJCPFXODm0a/qeWBkcbH41hDq9X0juOsb5aVeXK+sEHu4NMyh3Z6ADN8aD+RN soWlGN0d7u9JexqFgHHrforLjLfZZfuX4HjhelQMA8WpFT6sRxrlDsO2PUJspVgsFACI YLF/JUBDc6Z7nI8L7ZQ8sjp5MXnL4eJtqkHgnD/Vg0iaTOxtsU7Bc1ig5b42ClbmCPZ6 +BGw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from; bh=QW0Iq8WrmfF0jKtoXjhnSM5OqhTb4BFR3CmPjcDNEW8=; fh=z4XZ7PphyZ1eNRGpQp9PgXQa92ZiAhNGhVnSRYnQ8Yo=; b=sPRbFOFrfTzWYQRkE0+EL9DzfWyFXkn8Z3RtLVGulqzTYLzblm256eJA7NvCmphot6 bo190S2JwFWVCG6nUYP9yDD97VNz2Md+UH2RjAMzY8tdRnsYRlH6fVfkDXR842Vda5Tz RGTkxwcv6AAdz8BlG5yjWDllsLJjVjypXmIgyAN7Lq3YdzUywgp5bn6LLrIdcMYperZU +8p1LDOQwZqL2boTtV39gm5GZGlGJ98zzog0zhsfn8Pee96EeA1379v98MXQgYGHKTzA YUvEwFDsgXV8s/6IqWx9nQaKAPo0NzEzu4hm4Wv76eJSzdEWW+xqmdcByWJX/NmQ7dAf eV1w==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=christina-quast.de); spf=pass (google.com: domain of linux-kernel+bounces-48665-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48665-ouuuleilei=gmail.com@vger.kernel.org" X-Forwarded-Encrypted: i=1; AJvYcCVoOU4WAOjYdivzV3iAVDZ9eaG8dsu2btMOcF+oibWkbkz4/TLpB1upDzrUUV/TKtc7aL1hRjjyBf4ybVsuAptTyla2Rg== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id ca4-20020aa7cd64000000b0055c68b9f4adsi34229edb.491.2024.02.01.10.12.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Feb 2024 10:12:34 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-48665-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=christina-quast.de); spf=pass (google.com: domain of linux-kernel+bounces-48665-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-48665-ouuuleilei=gmail.com@vger.kernel.org" Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 2FCD51F23D7C for ; Thu, 1 Feb 2024 18:12:34 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 81DFA12FB0A; Thu, 1 Feb 2024 18:07:24 +0000 (UTC) Received: from mail.someserver.de (mail.someserver.de [116.202.193.223]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 67A8512E1CC; Thu, 1 Feb 2024 18:07:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=116.202.193.223 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810842; cv=none; b=SnqKSweXWaUWi2iiuuJfo1gn0qh1drJ799Y9Fiiur22RLC7LNamnrEzQYLCcZIM2e9gGzaONzmScH0rS0j/iIjcajmaLIvcRZDrZFTxNJlkKtx0qp51Uw0huATIU6OAqbrdiIWwYYgVY4oPS0oR6pQm5bdOo74w697/rTtuIRbA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706810842; c=relaxed/simple; bh=TIHsrpiXhvakc3QpotZKPzxEDzOuO24UX7NpNCsypps=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ny9nyHI3Ou9wgX9nys79M/sOep77TZ2j9nCOlS1oLotC70thNXlp1togM6kc58pkEKa2Cdu5leWQh+BX61qzB0L42WqOrRreYnA2T8bZkzqPGQk5Qn2vE2k0BiS/SGngyYUEkl7K2qOIFeYHxRShXFZ4jWSY/hgWyqCY5qmsSnw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de; spf=pass smtp.mailfrom=christina-quast.de; arc=none smtp.client-ip=116.202.193.223 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=christina-quast.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=christina-quast.de Received: from localhost (unknown [195.162.191.218]) by mail.someserver.de (Postfix) with ESMTPSA id F41BCA2267; Thu, 1 Feb 2024 19:07:17 +0100 (CET) From: Christina Quast Date: Thu, 01 Feb 2024 19:07:00 +0100 Subject: [PATCH v2 3/3] net: phy: add Rust Rockchip PHY driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240201-rockchip-rust-phy_depend-v2-3-c5fa4faab924@christina-quast.de> References: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> In-Reply-To: <20240201-rockchip-rust-phy_depend-v2-0-c5fa4faab924@christina-quast.de> To: Miguel Ojeda , Alex Gaynor , Wedson Almeida Filho , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , FUJITA Tomonori , Trevor Gross , Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Heiko Stuebner Cc: rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, Christina Quast X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706810819; l=6330; i=contact@christina-quast.de; s=20240130; h=from:subject:message-id; bh=TIHsrpiXhvakc3QpotZKPzxEDzOuO24UX7NpNCsypps=; b=8X+Cl8CgP8FACgRIhTspxgnky8uPVFD6oK9+YPkEb03a9uYnKVWs2Fjil6lGl/w6frseON75r cp6NdHHykN+DubHZ8prPcfHHGD5OQHP108x7AX4hJtENdpJQ/MTXYUM X-Developer-Key: i=contact@christina-quast.de; a=ed25519; pk=aoQfinjbnr265vCkIZdYteLDcmIqLBhY1m74WfFUU9E= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789721213304839718 X-GMAIL-MSGID: 1789721213304839718 This is the Rust implementation of drivers/net/phy/rockchip.c. The features are equivalent. You can choose C or Rust version kernel configuration. Signed-off-by: Christina Quast --- drivers/net/phy/Kconfig | 8 +++ drivers/net/phy/Makefile | 4 ++ drivers/net/phy/rockchip_rust.rs | 131 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 143 insertions(+) diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig index 9e2672800f0b..8b73edb7e836 100644 --- a/drivers/net/phy/Kconfig +++ b/drivers/net/phy/Kconfig @@ -362,6 +362,14 @@ config ROCKCHIP_PHY help Currently supports the integrated Ethernet PHY. +config ROCKCHIP_RUST_PHY + bool "Rust driver for Rockchip Ethernet PHYs" + depends on RUST_PHYLIB_ABSTRACTIONS && ROCKCHIP_PHY + help + Uses the Rust reference driver for Rockchip PHYs (rockchip_rust.ko). + The features are equivalent. It supports the integrated Ethernet PHY. + + config SMSC_PHY tristate "SMSC PHYs" select CRC16 diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile index 6097afd44392..045d2913bf2e 100644 --- a/drivers/net/phy/Makefile +++ b/drivers/net/phy/Makefile @@ -94,7 +94,11 @@ obj-$(CONFIG_NXP_TJA11XX_PHY) += nxp-tja11xx.o obj-$(CONFIG_QSEMI_PHY) += qsemi.o obj-$(CONFIG_REALTEK_PHY) += realtek.o obj-$(CONFIG_RENESAS_PHY) += uPD60620.o +ifdef CONFIG_ROCKCHIP_RUST_PHY +obj-$(CONFIG_ROCKCHIP_PHY) += rockchip_rust.o +else obj-$(CONFIG_ROCKCHIP_PHY) += rockchip.o +endif obj-$(CONFIG_SMSC_PHY) += smsc.o obj-$(CONFIG_STE10XP) += ste10Xp.o obj-$(CONFIG_TERANETICS_PHY) += teranetics.o diff --git a/drivers/net/phy/rockchip_rust.rs b/drivers/net/phy/rockchip_rust.rs new file mode 100644 index 000000000000..17a1f94da8c1 --- /dev/null +++ b/drivers/net/phy/rockchip_rust.rs @@ -0,0 +1,131 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (C) 2024 Christina Quast + +//! Rust Rockchip PHY driver +//! +//! C version of this driver: [`drivers/net/phy/rockchip.c`](./rockchip.c) +use kernel::{ + c_str, + net::phy::{self, DeviceId, Driver}, + prelude::*, + uapi, +}; + +kernel::module_phy_driver! { + drivers: [PhyRockchip], + device_table: [ + DeviceId::new_with_driver::(), + ], + name: "rust_asix_phy", + author: "FUJITA Tomonori ", + description: "Rust Asix PHYs driver", + license: "GPL", +} + + +const MII_INTERNAL_CTRL_STATUS: u16 = 17; +const SMI_ADDR_TSTCNTL: u16 = 20; +const SMI_ADDR_TSTWRITE: u16 = 23; + +const MII_AUTO_MDIX_EN: u16 = bit(7); +const MII_MDIX_EN: u16 = bit(6); + +const TSTCNTL_WR: u16 = bit(14) | bit(10); + +const TSTMODE_ENABLE: u16 = 0x400; +const TSTMODE_DISABLE: u16 = 0x0; + +const WR_ADDR_A7CFG: u16 = 0x18; + +struct PhyRockchip; + +impl PhyRockchip { + /// Helper function for helper_integrated_phy_analog_init + fn helper_init_tstmode(dev: &mut phy::Device) -> Result { + // Enable access to Analog and DSP register banks + dev.write(SMI_ADDR_TSTCNTL, TSTMODE_ENABLE)?; + dev.write(SMI_ADDR_TSTCNTL, TSTMODE_DISABLE)?; + dev.write(SMI_ADDR_TSTCNTL, TSTMODE_ENABLE) + } + + /// Helper function for helper_integrated_phy_analog_init + fn helper_close_tstmode(dev: &mut phy::Device) -> Result { + dev.write(SMI_ADDR_TSTCNTL, TSTMODE_DISABLE) + } + + /// Helper function for rockchip_config_init + fn helper_integrated_phy_analog_init(dev: &mut phy::Device) -> Result { + Self::helper_init_tstmode(dev)?; + dev.write(SMI_ADDR_TSTWRITE, 0xB)?; + dev.write(SMI_ADDR_TSTCNTL, TSTCNTL_WR | WR_ADDR_A7CFG)?; + Self::helper_close_tstmode(dev) + } + + /// Helper function for config_init + fn helper_config_init(dev: &mut phy::Device) -> Result { + let val = !MII_AUTO_MDIX_EN & dev.read(MII_INTERNAL_CTRL_STATUS)?; + dev.write(MII_INTERNAL_CTRL_STATUS, val)?; + Self::helper_integrated_phy_analog_init(dev) + } + + fn helper_set_polarity(dev: &mut phy::Device, polarity: u8) -> Result { + let reg = !MII_AUTO_MDIX_EN & dev.read(MII_INTERNAL_CTRL_STATUS)?; + let val = match polarity as u32 { + // status: MDI; control: force MDI + uapi::ETH_TP_MDI => Some(reg & !MII_MDIX_EN), + // status: MDI-X; control: force MDI-X + uapi::ETH_TP_MDI_X => Some(reg | MII_MDIX_EN), + // uapi::ETH_TP_MDI_AUTO => control: auto-select + // uapi::ETH_TP_MDI_INVALID => status: unknown; control: unsupported + _ => None, + }; + if let Some(v) = val { + if v != reg { + return dev.write(MII_INTERNAL_CTRL_STATUS, v); + } + } + Ok(()) + + } +} + +#[vtable] +impl Driver for PhyRockchip { + const FLAGS: u32 = 0; + const NAME: &'static CStr = c_str!("Rockchip integrated EPHY"); + const PHY_DEVICE_ID: DeviceId = DeviceId::new_with_custom_mask(0x1234d400, 0xfffffff0); + + fn link_change_notify(dev: &mut phy::Device) { + // If mode switch happens from 10BT to 100BT, all DSP/AFE + // registers are set to default values. So any AFE/DSP + // registers have to be re-initialized in this case. + if dev.state() == phy::DeviceState::Running && dev.speed() == uapi::SPEED_100 { + if let Err(e) = Self::helper_integrated_phy_analog_init(dev) { + pr_err!("rockchip: integrated_phy_analog_init err: {:?}", e); + } + } + } + + fn soft_reset(dev: &mut phy::Device) -> Result { + dev.genphy_soft_reset() + } + + fn config_init(dev: &mut phy::Device) -> Result { + PhyRockchip::helper_config_init(dev) + } + + fn config_aneg(dev: &mut phy::Device) -> Result { + PhyRockchip::helper_set_polarity(dev, dev.mdix())?; + dev.genphy_config_aneg() + } + + fn suspend(dev: &mut phy::Device) -> Result { + dev.genphy_suspend() + } + + fn resume(dev: &mut phy::Device) -> Result { + let _ = dev.genphy_resume(); + + PhyRockchip::helper_config_init(dev) + } +}