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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig3062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 1/5] mmc: sdhci_am654: Add tuning algorithm for delay chain Date: Wed, 31 Jan 2024 15:50:40 -0600 Message-ID: <20240131215044.3163469-2-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789644618175390146 X-GMAIL-MSGID: 1789644618175390146 Currently the sdhci_am654 driver only supports one tuning algorithm which should be used only when DLL is enabled. The ITAPDLY is selected from the largest passing window and the buffer is viewed as a circular buffer. The new algorithm should be used when the delay chain is enabled. The ITAPDLY is selected from the largest passing window and the buffer is not viewed as a circular buffer. This implementation is based off of the following paper: [1]. Also add support for multiple failing windows. [1] https://www.ti.com/lit/an/spract9/spract9.pdf Fixes: 13ebeae68ac9 ("mmc: sdhci_am654: Add support for software tuning") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 128 +++++++++++++++++++++++++++------ 1 file changed, 108 insertions(+), 20 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index d659c59422e1..a3798c9912f6 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -149,10 +149,17 @@ struct sdhci_am654_data { int strb_sel; u32 flags; u32 quirks; + bool dll_enable; #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) }; +struct window { + u8 start; + u8 end; + u8 length; +}; + struct sdhci_am654_driver_data { const struct sdhci_pltfm_data *pdata; u32 flags; @@ -290,10 +297,13 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); - if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) + if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { sdhci_am654_setup_dll(host, clock); - else + sdhci_am654->dll_enable = true; + } else { sdhci_am654_setup_delay_chain(sdhci_am654, timing); + sdhci_am654->dll_enable = false; + } regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); @@ -408,39 +418,117 @@ static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) return 0; } -#define ITAP_MAX 32 +#define ITAPDLY_LENGTH 32 +#define ITAPDLY_LAST_INDEX 31 +static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window + *fail_window, u8 num_fails, bool circular_buffer) +{ + struct device *dev = mmc_dev(host->mmc); + struct window pass_window, first_fail, last_fail; + u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; + int prev_end_fail = -1; + u8 i; + + memset(&pass_window, 0, sizeof(pass_window)); + memset(&first_fail, 0, sizeof(first_fail)); + memset(&last_fail, 0, sizeof(last_fail)); + + if (!num_fails) { + itap = ITAPDLY_LAST_INDEX >> 1; + } else if (fail_window->length == ITAPDLY_LENGTH) { + dev_err(dev, "No passing ITAPDLY, return 0\n"); + itap = 0; + } else { + for (i = 0; i < num_fails; i++) { + start_fail = fail_window[i].start; + end_fail = fail_window[i].end; + + if (i == 0) { + first_fail.start = start_fail; + first_fail.end = end_fail; + first_fail.length = fail_window[0].length; + } + + if (i == num_fails - 1) { + last_fail.start = start_fail; + last_fail.end = end_fail; + last_fail.length = fail_window[i].length; + } + + pass_length = start_fail - (prev_end_fail + 1); + if (pass_length > pass_window.length) { + pass_window.start = prev_end_fail + 1; + pass_window.length = pass_length; + } + prev_end_fail = end_fail; + } + + if (!circular_buffer) { + if (ITAPDLY_LAST_INDEX - end_fail > pass_window.length) { + pass_window.start = end_fail + 1; + pass_window.length = ITAPDLY_LAST_INDEX - end_fail; + } + } else { + pass_length = ITAPDLY_LAST_INDEX - end_fail + first_fail.start; + if (pass_length > pass_window.length) { + pass_window.start = last_fail.end + 1; + pass_window.length = pass_length; + } + } + + if (!circular_buffer) + itap = pass_window.start + (pass_window.length >> 1); + else + itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; + + if (itap < 0 || itap > ITAPDLY_LAST_INDEX) + itap = 0; + } + + return itap; +} + static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, u32 opcode) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); - int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; - u32 itap; + struct window fail_window[ITAPDLY_LENGTH]; + u8 prev_pass = 1; + u8 fail_index = 0; + u8 curr_pass, itap; + + memset(fail_window, 0, sizeof(fail_window[0]) * ITAPDLY_LENGTH); /* Enable ITAPDLY */ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 1 << ITAPDLYENA_SHIFT); - for (itap = 0; itap < ITAP_MAX; itap++) { + for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { sdhci_am654_write_itapdly(sdhci_am654, itap); - cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); - if (cur_val && !prev_val) - pass_window = itap; + curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); - if (!cur_val) - fail_len++; + if (!curr_pass && prev_pass) + fail_window[fail_index].start = itap; - prev_val = cur_val; + if (!curr_pass) { + fail_window[fail_index].end = itap; + fail_window[fail_index].length++; + } + + if (curr_pass && !prev_pass) + fail_index++; + + prev_pass = curr_pass; } - /* - * Having determined the length of the failing window and start of - * the passing window calculate the length of the passing window and - * set the final value halfway through it considering the range as a - * circular buffer - */ - pass_len = ITAP_MAX - fail_len; - itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; + + if (fail_window[fail_index].length != 0) + fail_index++; + + itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, + (sdhci_am654->dll_enable ? true : false)); + sdhci_am654_write_itapdly(sdhci_am654, itap); return 0; From patchwork Wed Jan 31 21:50:41 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 194974 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:106:209c:c626 with SMTP id mn5csp46163dyc; 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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig4062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 2/5] mmc: sdhci_am654: Write ITAPDLY for DDR52 timing Date: Wed, 31 Jan 2024 15:50:41 -0600 Message-ID: <20240131215044.3163469-3-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789644580404563539 X-GMAIL-MSGID: 1789644580404563539 For DDR52 timing, DLL is enabled but tuning is not carried out, therefore the ITAPDLY value in PHY CTRL 4 register is not correct. Fix this by writing ITAPDLY after enabling DLL. Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 27 +++++++++++++++------------ 1 file changed, 15 insertions(+), 12 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index a3798c9912f6..ff18a274b6f2 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -170,7 +170,19 @@ struct sdhci_am654_driver_data { #define DLL_CALIB (1 << 4) }; -static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) +static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, + u32 itapdly) +{ + /* Set ITAPCHGWIN before writing to ITAPDLY */ + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, + itapdly << ITAPDLYSEL_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); +} + +static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, + unsigned char timing) { struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); @@ -236,17 +248,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); return; } -} -static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) -{ - /* Set ITAPCHGWIN before writing to ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, - 1 << ITAPCHGWIN_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, - itapdly << ITAPDLYSEL_SHIFT); - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -298,7 +301,7 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { - sdhci_am654_setup_dll(host, clock); + sdhci_am654_setup_dll(host, clock, timing); sdhci_am654->dll_enable = true; } else { sdhci_am654_setup_delay_chain(sdhci_am654, timing); From patchwork Wed Jan 31 21:50:42 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 194978 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:106:209c:c626 with SMTP id mn5csp46450dyc; Wed, 31 Jan 2024 13:55:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IE5yWYUgblKzI5clbp5/mr1LnMOCTgi9hLrKcUKgLMLO884D+1DvatvP/pTA2LH2EPRsgMh X-Received: by 2002:a50:9b57:0:b0:55f:3d12:eb3c with SMTP id a23-20020a509b57000000b0055f3d12eb3cmr2278487edj.14.1706738116138; Wed, 31 Jan 2024 13:55:16 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706738116; cv=pass; d=google.com; s=arc-20160816; b=nDqdVrdSPJYRkZ4oq1Ru6SSx46sPrD2QT6CoM8Z90Uwp4RM9CKNp7jrJFeFREodaNo MY8AQZXjqnVdMRG35038hp0dvYIZBKz3QUmI6ye8i0qbgEOwQ+oBtwRi6LnotKSRjDMn sCFKzzgSqRoZCkLpXs8mA47mNYG6H9vKy1Hlermyurb2l6lGC9SsFGuxgxfqoP0Eqetu XFSzimza/xbL6WKN3dI/QoOSenqs9gVVHBDE/KJ7MULVZhjcCIl4SFEX8hjvjUglWsiV PAxxifT8ewwUFIp0zBCzjsYQt60vPMwBTRkbABLX03A9wz1UZC1wmVhsGxdlaAs0sWWW 4Aew== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=2Kdumh5zzuoRvyue9vxpLhNT0R8HOCdPWNPZeVm94jM=; fh=aPRiIZ+mTw9pVDWgRugOKvnReUIB2qXbUWbP5XhOslM=; b=yX3Nj2rS/thJqcYwe1lKNx0tGRhgP6ww9KhIqR9UEfcBDFyq1FdVO1nYEhQ0uD3fqT jYuzilQjzzA+lbqDmkqxVB0uRu+GgMxQx+E+kFVJTqMJ2dwr7AJGAO3/C7K+WyJhyN9I taGfVk74yPX025wD+s1yoB3lNcUiHTpY/u57WsxmziSI2c5HesYQUqkmi3MmoF10FkhU 4fKnTe34qGORIoB+70hO6mKd88GDxr22+P0v10ckbdPPN7PTr38MrTDGfdqRHR/2w4Gy J1r9CHUEzAHe5uRCuQgjiqSNaXrFcyprjgNqzZx3AfJKSH5a+2/5emUrknGWcYLOV4rV Q7uw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KrppY5x7; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-47207-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-47207-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=1; AJvYcCWBP6lUk2ntaWDz2XJqs4AU4pdtKFf1532eo+kayDkwORhMjTFH2gY4qIhYfUza4wA9dnpQ6tqRU9c5HyPLLX4cbBBQ5w== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig5062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 3/5] mmc: sdhci_am654: Add missing OTAP/ITAP enable Date: Wed, 31 Jan 2024 15:50:42 -0600 Message-ID: <20240131215044.3163469-4-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789644626978828744 X-GMAIL-MSGID: 1789644626978828744 Currently the OTAP/ITAP delay enable functionality is missing in the am654_set_clock function which is used for MMC0 on AM62p and AM64x devices. The OTAP delay is not enabled when timing < SDR25 bus speed mode. The ITAP delay is not enabled for all bus speed modes. Add this OTAP/ITAP delay functionality according to the datasheet [1] OTAPDLYENA and ITAPDLYENA for MMC0. [1] https://www.ti.com/lit/ds/symlink/am62p.pdf Fixes: 8ee5fc0e0b3b ("mmc: sdhci_am654: Update OTAPDLY writes") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 48 +++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 21 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index ff18a274b6f2..5ac82bc70706 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -143,6 +143,7 @@ struct sdhci_am654_data { struct regmap *base; int otap_del_sel[ARRAY_SIZE(td)]; int itap_del_sel[ARRAY_SIZE(td)]; + u8 itap_del_ena[ARRAY_SIZE(td)]; int clkbuf_sel; int trm_icp; int drv_strength; @@ -171,11 +172,13 @@ struct sdhci_am654_driver_data { }; static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, - u32 itapdly) + u32 itapdly, u32 enable) { /* Set ITAPCHGWIN before writing to ITAPDLY */ regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0x1 << ITAPCHGWIN_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, + enable << ITAPDLYENA_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, itapdly << ITAPDLYSEL_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); @@ -249,7 +252,8 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, return; } - sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, @@ -263,8 +267,8 @@ static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); - sdhci_am654_write_itapdly(sdhci_am654, - sdhci_am654->itap_del_sel[timing]); + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], + sdhci_am654->itap_del_ena[timing]); } static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) @@ -273,20 +277,17 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; - u32 otap_del_ena; u32 mask, val; regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); sdhci_set_clock(host, clock); - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; - otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (otap_del_ena << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); /* Write to STRBSEL for HS400 speed mode */ if (timing == MMC_TIMING_MMC_HS400) { @@ -319,14 +320,20 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; + u32 itap_del_ena; u32 mask, val; - /* Setup DLL Output TAP delay */ + /* Setup Output TAP delay */ otap_del_sel = sdhci_am654->otap_del_sel[timing]; mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; - val = (0x1 << OTAPDLYENA_SHIFT) | - (otap_del_sel << OTAPDLYSEL_SHIFT); + val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + + itap_del_ena = sdhci_am654->itap_del_ena[timing]; + + mask |= ITAPDLYENA_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, @@ -503,12 +510,8 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, memset(fail_window, 0, sizeof(fail_window[0]) * ITAPDLY_LENGTH); - /* Enable ITAPDLY */ - regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, - 1 << ITAPDLYENA_SHIFT); - for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); @@ -532,7 +535,7 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, (sdhci_am654->dll_enable ? true : false)); - sdhci_am654_write_itapdly(sdhci_am654, itap); + sdhci_am654_write_itapdly(sdhci_am654, itap, 1); return 0; } @@ -681,9 +684,12 @@ static int sdhci_am654_get_otap_delay(struct sdhci_host *host, host->mmc->caps2 &= ~td[i].capability; } - if (td[i].itap_binding) - device_property_read_u32(dev, td[i].itap_binding, - &sdhci_am654->itap_del_sel[i]); + if (td[i].itap_binding) { + ret = device_property_read_u32(dev, td[i].itap_binding, + &sdhci_am654->itap_del_sel[i]); + if (!ret) + sdhci_am654->itap_del_ena[i] = 0x1; + } } return 0; From patchwork Wed Jan 31 21:50:43 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 194984 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:106:209c:c626 with SMTP id mn5csp49314dyc; Wed, 31 Jan 2024 14:01:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IGpKCNFcygKvaCxk0LwVPIkE7ATyildLopG9do1VeTndx4Hlmh/X3Iot519Uhaw+qEv3kzo X-Received: by 2002:a05:6a20:8012:b0:19e:3006:5dc5 with SMTP id e18-20020a056a20801200b0019e30065dc5mr2647972pza.3.1706738488122; Wed, 31 Jan 2024 14:01:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706738488; cv=pass; d=google.com; s=arc-20160816; b=RigVd5GHAaXxB6rQNiG/UBXlT81uB/yRezMddMd5GZ2W97lNDI3F9bnDB2KCkxGUg1 ua/KyMnmVn34w6A1Q1IhuJzb9i81R+lYko9Y53ZH94SYYDbSg61Qk1M55GkVf92cUxDj dIA3Bvc213gI9KsCDww5gN8XUCtfcupT2M1V5v9+go457NjX0dW/mmNYz5N7UfPE2j4P MeNj1XbaOs8QVbpcMcob40rE2SsxZ5JErR/bDvpbpzKcfsNaND8CEFVcNRgrFhyEbvMF orxp6zCzTphl4iTFJrie5ylw3yU8f5CxMyqflbsXdPqAwHsXfdo9yLGZSDi0gJ7i1g4B ZMpg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=onc9QM9ukgmYukraFs8da86DAT/6E9TriZDUxBTiRZ8=; fh=5kIJk6lw+Iemcq3DaGU9VkDDGXLTlYcaecI6kTuMnBk=; b=l/pl4ZPKTW1Nz/Aclkci1yD8rOJBGRaxd/NDHZ9b08OIJVDalvQHPf3S02UU4uJHcr zCOAkKNB+SyT0+5D25E5iKGqLTjJ7w33LHBkm9N7G0rMn43i71fTFF84l3uawlR32MpF ocv4SnfgjmgYFMOAUa/ekWrLWfCQf/u4aczd0A8HzTFmmKb1yuT/M3CTrvsjF9GVftTK EH7fg9+QwX+DRW6+BXBliS7QMxuy291xHoiyZPRQWSBfXPMU+PchawPWelsmGCnjVh5d ytgZTwWweNu8/KwFsKqyr+FsSKNYn3juks9KKcxcknCJDEk9Q5AIALhH3AvLmgX2LA8D tDKg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=h6ZidhzT; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-47203-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-47203-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=1; AJvYcCXYkNUHDsK9lGJducc2k/K8dxECcxC/GWMmikWUPm81ashUKj8eLR9uzSRAizs8JtriSYPd64RKAbYfuLqa3ZDziPfR1Q== Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig6062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 4/5] mmc: sdhci_am654: Add ITAPDLYSEL in sdhci_j721e_4bit_set_clock Date: Wed, 31 Jan 2024 15:50:43 -0600 Message-ID: <20240131215044.3163469-5-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789645016829710464 X-GMAIL-MSGID: 1789645016829710464 Add ITAPDLYSEL to sdhci_j721e_4bit_set_clock function. This allows to set the correct ITAPDLY for timings that do not carry out tuning. Fixes: 1accbced1c32 ("mmc: sdhci_am654: Add Support for 4 bit IP on J721E") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index 5ac82bc70706..f5dc981c470d 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -321,6 +321,7 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, unsigned char timing = host->mmc->ios.timing; u32 otap_del_sel; u32 itap_del_ena; + u32 itap_del_sel; u32 mask, val; /* Setup Output TAP delay */ @@ -329,12 +330,17 @@ static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; val = (0x1 << OTAPDLYENA_SHIFT) | (otap_del_sel << OTAPDLYSEL_SHIFT); + /* Setup Input TAP delay */ itap_del_ena = sdhci_am654->itap_del_ena[timing]; + itap_del_sel = sdhci_am654->itap_del_sel[timing]; - mask |= ITAPDLYENA_MASK; - val |= (itap_del_ena << ITAPDLYENA_SHIFT); + mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; + val |= (itap_del_ena << ITAPDLYENA_SHIFT) | (itap_del_sel << ITAPDLYSEL_SHIFT); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, + 1 << ITAPCHGWIN_SHIFT); regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); + regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); From patchwork Wed Jan 31 21:50:44 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Judith Mendez X-Patchwork-Id: 194979 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:693c:2685:b0:106:209c:c626 with SMTP id mn5csp46484dyc; Wed, 31 Jan 2024 13:55:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcZwpHZ+aSm8wl7eSFLfMrzIN8q1+o3i1eqkgA9HukvKIjIYJ03H8GuiG4YMSnXrJXaslF X-Received: by 2002:a37:e30d:0:b0:784:93d:c905 with SMTP id y13-20020a37e30d000000b00784093dc905mr748434qki.25.1706738122836; Wed, 31 Jan 2024 13:55:22 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706738122; cv=pass; d=google.com; s=arc-20160816; b=PLq1BIF61jYi68qXnuAxHj1vMhjSrpMx3JPygg/ZXRQpYCEaieKzPY5phIYSI2ELx5 DFuUHYayRnXx2bfENGkg78u2MtMLXZcK/DLCbxZ7vc3mfJtE8DR+krNIB80FYsZhUVub MVMQROfwsgQK5f+6acVwG2N2OdVtuBpJTFpBccpTubC1AS9bkzNygN9PIYB6dRUgXCGQ NBFlG5xsr1LrEEcLIdLDn6d6LWjjvcS2vFjzGdDLjbeanbjwxAMmWZt4b81Mqg8oYBNX MO48PfuTNACSeuK70i9lCKjqWEUSEsLh2/t9XQe/y4ujMT59HRmFPsy0aYXtxYn4731s OoAg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=eHe2J9QDOcqKed5tvQb+FrJvtyyBTVZ3QyddNuzM7mU=; fh=UFvwS7Q4IS8zKuv61d35fP1Guwr+x8R4CaNYz7ZMUf4=; b=o47HLqzGLfoYsnylqjhlzNPPGw2PeKPDm2H4eNrcWQ4wrEMC1CAA1e+wN3YGlsHxy1 vb2qCKwxwDQo9WOqD2PMs6CFRwBNJKnS5OruZxDY8K/tzBhnusoLHxpD75AEjJ9xMypp bZnTUAW0FVoXY+qeBlZGkDCZE2NT7QnRgC8ZesjjBRR37VY9RVIwKoFeqD7sA9DGEIPU nGxn/0V1oUb/9QERdfrp/jofJYvu2IAdZo7+GeZtztmn+IFwNhDIDhgdB6/wZbT0+PFz qIIy0rAl94IiLcid2S2+rTH2tZUtj4AcIVVt+SImGWMZlKpp6qbfu73BRT5+GE9Pljzi gnyQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=MvcbEgxq; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-47209-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-47209-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com X-Forwarded-Encrypted: i=1; AJvYcCUuxhosKnWTU7q+E6AKTvF1I0sH+BDP6gJVC9nzjlGhYA470M8qQvql+eBO6ADNBRQc8CtPHG+JWIp2XagE/JF1QVPIqg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Wed, 31 Jan 2024 15:50:44 -0600 Received: from judy-hp.dhcp.ti.com (judy-hp.dhcp.ti.com [128.247.81.105]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40VLoig7062479; Wed, 31 Jan 2024 15:50:44 -0600 From: Judith Mendez To: Ulf Hansson CC: Adrian Hunter , , , Randolph Sapp , Vignesh Raghavendra Subject: [PATCH v1 5/5] mmc: sdhci_am654: Fix ITAPDLY for HS400 timing Date: Wed, 31 Jan 2024 15:50:44 -0600 Message-ID: <20240131215044.3163469-6-jm@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240131215044.3163469-1-jm@ti.com> References: <20240131215044.3163469-1-jm@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789644634251522235 X-GMAIL-MSGID: 1789644634251522235 While STRB is currently used for DATA and CRC responses, the CMD responses from the device to the host still require ITAPDLY for HS400 timing. Currently what is stored for HS400 is the ITAPDLY from High Speed mode which is incorrect. The ITAPDLY for HS400 speed mode should be the same as ITAPDLY as HS200 timing after tuning is executed. Add the functionality to save ITAPDLY from HS200 tuning and save as HS400 ITAPDLY. Fixes: a161c45f2979 ("mmc: sdhci_am654: Enable DLL only for some speed modes") Signed-off-by: Judith Mendez --- drivers/mmc/host/sdhci_am654.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/mmc/host/sdhci_am654.c b/drivers/mmc/host/sdhci_am654.c index f5dc981c470d..beb0ca88ba1b 100644 --- a/drivers/mmc/host/sdhci_am654.c +++ b/drivers/mmc/host/sdhci_am654.c @@ -151,6 +151,7 @@ struct sdhci_am654_data { u32 flags; u32 quirks; bool dll_enable; + bool hs200_tunning; #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) }; @@ -252,6 +253,10 @@ static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock, return; } + /* HS400 ITAPDLY should be the same as HS200 ITAPDLY*/ + if (timing == MMC_TIMING_MMC_HS400) + sdhci_am654->itap_del_sel[timing] = sdhci_am654->itap_del_sel[timing - 1]; + sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], sdhci_am654->itap_del_ena[timing]); } @@ -311,6 +316,9 @@ static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, sdhci_am654->clkbuf_sel); + + if (timing == MMC_TIMING_MMC_HS200 && sdhci_am654->dll_enable) + sdhci_am654->hs200_tunning = true; } static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, @@ -543,6 +551,10 @@ static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, sdhci_am654_write_itapdly(sdhci_am654, itap, 1); + /* Save ITAPDLY for HS200 */ + if (sdhci_am654->hs200_tunning) + sdhci_am654->itap_del_sel[MMC_TIMING_MMC_HS200] = itap; + return 0; }