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Add flags and acc fields to `struct clk_fixed_factor` to support setting a fixed accuracy. The default if no flag is set is not changed: use the parent clock accuracy. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 28 +++++++++++++++++++++------- include/linux/clk-provider.h | 12 +++++++++++- 2 files changed, 32 insertions(+), 8 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index b3e66202b942..bc2644a9bd7d 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -57,10 +57,22 @@ static int clk_factor_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } +static unsigned long clk_factor_recalc_accuracy(struct clk_hw *hw, + unsigned long parent_accuracy) +{ + struct clk_fixed_factor *fix = to_clk_fixed_factor(hw); + + if (fix->flags & CLK_FIXED_FACTOR_FIXED_ACCURACY) + return fix->acc; + + return parent_accuracy; +} + const struct clk_ops clk_fixed_factor_ops = { .round_rate = clk_factor_round_rate, .set_rate = clk_factor_set_rate, .recalc_rate = clk_factor_recalc_rate, + .recalc_accuracy = clk_factor_recalc_accuracy, }; EXPORT_SYMBOL_GPL(clk_fixed_factor_ops); @@ -81,7 +93,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, const struct clk_hw *parent_hw, int index, unsigned long flags, unsigned int mult, unsigned int div, - bool devm) + unsigned long acc, unsigned int fixflags, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; @@ -105,6 +117,8 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, fix->mult = mult; fix->div = div; fix->hw.init = &init; + fix->acc = acc; + fix->flags = fixflags; init.name = name; init.ops = &clk_fixed_factor_ops; @@ -152,7 +166,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, - flags, mult, div, true); + flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -174,7 +188,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, unsigned long flags, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, true); + -1, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -184,7 +198,7 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, { return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, -1, flags, mult, div, - false); + 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -193,7 +207,7 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, false); + flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); @@ -240,7 +254,7 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, unsigned int mult, unsigned int div) { return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, true); + flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); @@ -267,7 +281,7 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, false); + 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 1293c38ddb7f..7ddc952c8c67 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1084,18 +1084,28 @@ void of_fixed_factor_clk_setup(struct device_node *node); * @hw: handle between common and hardware-specific interfaces * @mult: multiplier * @div: divider + * @acc: fixed accuracy in ppb + * @flags: behavior modifying flags * * Clock with a fixed multiplier and divider. The output frequency is the * parent clock rate divided by div and multiplied by mult. - * Implements .recalc_rate, .set_rate and .round_rate + * Implements .recalc_rate, .set_rate, .round_rate and .recalc_accuracy + * + * Flags: + * * CLK_FIXED_FACTOR_FIXED_ACCURACY - Use the value in @acc instead of the + * parent clk accuracy. */ struct clk_fixed_factor { struct clk_hw hw; unsigned int mult; unsigned int div; + unsigned long acc; + unsigned int flags; }; +#define CLK_FIXED_FACTOR_FIXED_ACCURACY BIT(0) + #define to_clk_fixed_factor(_hw) container_of(_hw, struct clk_fixed_factor, hw) extern const struct clk_ops clk_fixed_factor_ops; From patchwork Wed Jan 31 16:26:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194841 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2006643dyb; Wed, 31 Jan 2024 08:29:49 -0800 (PST) X-Google-Smtp-Source: AGHT+IGJ+gYEvHIIwOk7efuKlPlrnWkVWWWHv1Zo1EW/iZQwimrLOJMPxVxsMAhe/aEqt+Y4NtVs X-Received: by 2002:a17:90a:4a8c:b0:295:1e7d:bc14 with SMTP id f12-20020a17090a4a8c00b002951e7dbc14mr2178885pjh.20.1706718589263; Wed, 31 Jan 2024 08:29:49 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718589; cv=pass; d=google.com; s=arc-20160816; b=Rto1x7+b1P4nBI0k/19aj+IfdLDKcbhFaaF5tIh92an5FK6MOePwQf89/zlrzHbVl3 94sxoH4f5HkJH0/QseHJ9fLkrRfRgk+R1xTCeTZ3j6GGJTfHPnLEcSm4O4lh7kMk7Lef I4IxUo0kGA5zmRy55IdHP5DZ3E8Kf1g+7bF1I3F9ceEly9h/MXKk8hkteKEk8JKwXoJs IP78UnUJ+0/+rTHNybIjMBvcyn38G/nuzGbKc95c3LL7yLcM5+YMI/AsOdKmZQrGFub3 fH7fAcHCX3nNF9AhHgffvgVOr7Gm17T/TMgAjSTUlGrdvhsu/yHySj7U3qq7+taCm5GH GAGw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Hzzlts4PGXFUuRWYcplGsnHuTe6WB3sA9fR+Y6Zs2Sk=; fh=aLo7RW8bM70QMrW4gBXXMxyHXYCyWzNp0NZWfkvIKsE=; b=u4pR8A8vHyd8OMJQxDTYOiDS4mq9H5H3sw0wPzH1wM1xAC2UbFRnPFjEVzQb7OKSZb RrQh5pYHRGqX8lSdw1d2Nx+3848cLJCVU0gvU2tfxiwsKEOdRMGZkGTer3UX6zbtJ6fu 1Br2LNi9y/mMsOGaGpDTKAM/1JwvZbxAHEzgN7dsogU4a6AV9W8ZQ5isVHR98JH1AHVg vcwZxpJ2JDpGvFxCnMLfXjQ/lfn9cLhy8RtFWRT7QfyIqYN9/0RnZxoTaI4GEvkYDzHB wTwJGeNBUhEQi+jRNVLBg+fkMczTalqDd/Lwg0ssZSZEWQuL7tZY54mjs5ElMEUN9Y98 DEEg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=SzYBhPWp; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46788-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46788-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWlSwZH0tDkMsSpZvQAIE7Vk1x7sMvfbWTgANNkRwpkTuGDxyZo03Kw4P26PQTCWFSOuWUgSaT+tKrEMZqZ6LoRBGmDmw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718432; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Hzzlts4PGXFUuRWYcplGsnHuTe6WB3sA9fR+Y6Zs2Sk=; b=SzYBhPWpA4X6wCUe2ZEbjoYwFwrGRQrtLskTrnIRjixtJRB8RhM5uwwU7j9TkvYzfIV7bn qwxV+sgyrQF6RJHodAU56PNskLBwmRj3otq0GKCuVRV3RmRgjtWL0oqaavq7JnAD0QkemO IimGQID78GmdeympTPwJYZJ9ziJczBW/50tfAGM+Vn20Wfm+1KgNmaKDIM9laBSOMjwebj rADK85oOcqT+Ioovgvxcw+r3wrRBNYv3QvRWo3hlBLJsfHTklEoxhGchkzag+sHi462cTr 902rVRqtrqDq2bN8z9qFRnM5qpqAj6Ylt2c1qWZMbcVoEe5Ie4ZHIJIq59q2oA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:15 +0100 Subject: [PATCH v4 02/18] clk: fixed-factor: add fwname-based constructor functions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-2-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624151349982170 X-GMAIL-MSGID: 1789624151349982170 Add four functions to register clk_hw based on the fw_name field in clk_parent_data, ie the value in the DT property `clock-names`. There are variants for devm or not and passing an accuracy or not passing one: - clk_hw_register_fixed_factor_fwname - clk_hw_register_fixed_factor_with_accuracy_fwname - devm_clk_hw_register_fixed_factor_fwname - devm_clk_hw_register_fixed_factor_with_accuracy_fwname The `struct clk_parent_data` init is extracted from __clk_hw_register_fixed_factor to each calling function. It is required to allow each function to pass whatever field they want, not only index. Signed-off-by: Théo Lebrun --- drivers/clk/clk-fixed-factor.c | 85 +++++++++++++++++++++++++++++++++++------- include/linux/clk-provider.h | 14 +++++++ 2 files changed, 85 insertions(+), 14 deletions(-) diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c index bc2644a9bd7d..fe0500a1af3e 100644 --- a/drivers/clk/clk-fixed-factor.c +++ b/drivers/clk/clk-fixed-factor.c @@ -91,13 +91,12 @@ static void devm_clk_hw_register_fixed_factor_release(struct device *dev, void * static struct clk_hw * __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, const char *name, const char *parent_name, - const struct clk_hw *parent_hw, int index, + const struct clk_hw *parent_hw, const struct clk_parent_data *pdata, unsigned long flags, unsigned int mult, unsigned int div, unsigned long acc, unsigned int fixflags, bool devm) { struct clk_fixed_factor *fix; struct clk_init_data init = { }; - struct clk_parent_data pdata = { .index = index }; struct clk_hw *hw; int ret; @@ -128,7 +127,7 @@ __clk_hw_register_fixed_factor(struct device *dev, struct device_node *np, else if (parent_hw) init.parent_hws = &parent_hw; else - init.parent_data = &pdata; + init.parent_data = pdata; init.num_parents = 1; hw = &fix->hw; @@ -165,7 +164,9 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, index, + const struct clk_parent_data pdata = { .index = index }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_index); @@ -187,8 +188,10 @@ struct clk_hw *devm_clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { + const struct clk_parent_data pdata = { .index = -1 }; + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, - -1, flags, mult, div, 0, 0, true); + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_parent_hw); @@ -196,9 +199,10 @@ struct clk_hw *clk_hw_register_fixed_factor_parent_hw(struct device *dev, const char *name, const struct clk_hw *parent_hw, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, - parent_hw, -1, flags, mult, div, - 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, parent_hw, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_parent_hw); @@ -206,11 +210,37 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, false); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, false); } EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_fwname); + +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, false); +} +EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname); + struct clk *clk_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) @@ -253,16 +283,43 @@ struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div) { - return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, -1, - flags, mult, div, 0, 0, true); + const struct clk_parent_data pdata = { .index = -1 }; + + return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL, + &pdata, flags, mult, div, 0, 0, true); } EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, 0, 0, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_fwname); + +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc) +{ + const struct clk_parent_data pdata = { .index = -1, .fw_name = fw_name }; + + return __clk_hw_register_fixed_factor(dev, np, name, NULL, NULL, + &pdata, flags, mult, div, acc, + CLK_FIXED_FACTOR_FIXED_ACCURACY, true); +} +EXPORT_SYMBOL_GPL(devm_clk_hw_register_fixed_factor_with_accuracy_fwname); + #ifdef CONFIG_OF static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) { struct clk_hw *hw; const char *clk_name = node->name; + const struct clk_parent_data pdata = { .index = 0 }; u32 div, mult; int ret; @@ -280,8 +337,8 @@ static struct clk_hw *_of_fixed_factor_clk_setup(struct device_node *node) of_property_read_string(node, "clock-output-names", &clk_name); - hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, 0, - 0, mult, div, 0, 0, false); + hw = __clk_hw_register_fixed_factor(NULL, node, clk_name, NULL, NULL, + &pdata, 0, mult, div, 0, 0, false); if (IS_ERR(hw)) { /* * Clear OF_POPULATED flag so that clock registration can be diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h index 7ddc952c8c67..4a537260f655 100644 --- a/include/linux/clk-provider.h +++ b/include/linux/clk-provider.h @@ -1116,10 +1116,24 @@ void clk_unregister_fixed_factor(struct clk *clk); struct clk_hw *clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); void clk_hw_unregister_fixed_factor(struct clk_hw *hw); struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev, const char *name, const char *parent_name, unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div); +struct clk_hw *devm_clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *dev, + struct device_node *np, const char *name, const char *fw_name, + unsigned long flags, unsigned int mult, unsigned int div, + unsigned long acc); struct clk_hw *devm_clk_hw_register_fixed_factor_index(struct device *dev, const char *name, unsigned int index, unsigned long flags, unsigned int mult, unsigned int div); From patchwork Wed Jan 31 16:26:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194843 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2006672dyb; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718433; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=7eiFG62+hOSXiOhbfv9iGOn+0mEfhbeiuUK+9YHU1ZU=; b=IOPpK276Vnr4e/P2oPnaLT2bMmWFOLMmhPVczm6uFvBlJQxaYvkkRxRO+f0QvGpGl154Yu 9pwyv3nRIqjSfIslVue5xKt4q6KiQXX0FnddvvwB5dD4hQvLiZdu1/NnK5wyZyaAOF77az P3k44VwKXKHK0jAJagi+APrR6VYZRAeHRX56MCi3zH2aeL1NBHbdwoYB57NWxY7JRaHzkq O0qHP/Zel30neBIYowQoxnpUyIxbuYYNhMzCI4tKks/8svjt6zC0cYQVB1L1dHe2S8Rqqv x5/GRqFmkAg4TBGXFR8StH2tpmwY9wQIUrB1YwwaKLVd+56e7eSvINAoYXNFCw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:16 +0100 Subject: [PATCH v4 03/18] dt-bindings: pinctrl: allow pin controller device without unit address Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-3-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624154734796584 X-GMAIL-MSGID: 1789624154734796584 Allow a pin controller device to have no address, therefore no unit address. The previous $nodename was enforcing a unit address, but scripts/dtc/checks.c enforced that names with unit addresses have reg or ranges: Warning (unit_address_vs_reg): .../pinctrl@0: node has a unit name, but no reg or ranges property Fix pinctrl.yaml to adopt a (pinctrl|pinmux)(-[a-z]+)? node name when neither reg nor ranges are required. Use [a-z]+ to avoid conflicts with pinctrl-consumer.yaml. Signed-off-by: Théo Lebrun --- Documentation/devicetree/bindings/pinctrl/pinctrl.yaml | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml index d471563119a9..3d977b54e260 100644 --- a/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/pinctrl.yaml @@ -26,9 +26,6 @@ description: | controller device. properties: - $nodename: - pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" - "#pinctrl-cells": description: > Number of pin control cells in addition to the index within the pin @@ -42,4 +39,19 @@ properties: This property can be set either globally for the pin controller or in child nodes for individual pin group control. +if: + anyOf: + - required: + - reg + - required: + - ranges +then: + properties: + $nodename: + pattern: "^(pinctrl|pinmux)(@[0-9a-f]+)?$" +else: + properties: + $nodename: + pattern: "^(pinctrl|pinmux)(-[a-z]+)?$" + additionalProperties: true From patchwork Wed Jan 31 16:26:17 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194840 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2006574dyb; Wed, 31 Jan 2024 08:29:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IEXCNX6GY2d+uxJcWyD6Swobc0YXyErOgg6g8Hcg97N0bcFuOuYxtB0oKl0hJSDziYDHPIq X-Received: by 2002:a17:902:d904:b0:1d8:d3bf:b367 with SMTP id c4-20020a170902d90400b001d8d3bfb367mr2089554plz.29.1706718580275; Wed, 31 Jan 2024 08:29:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718580; cv=pass; d=google.com; s=arc-20160816; b=OUqwAWnO25YB8r/rHrdKyQjtyO0wFAUTxiKyG2SIRp0P3XEusOTPF8j2RCiOWj9wY8 y2Nf9qG34y2BqPWdK9HkSsF1FplFBEX4GiF3OVwJhvuiXIGsW+wgaZecJRbHdmzN2V1k 26+azOzvBBs9MIlt5r0qXAndGfTKM1wKurt0e3FxNYRR6QPy2JxfkhFrJxygEMFyojm6 7k7DhEA9a8e7IL2DUo/wTjb0g8Pup5YLsqVZeHmZcthcVS7utZFZfYeHnfNQO8x1wWki TGCUlooW3QPJIbCa7R5FufEJQ0JBrZO11m6xw05UlHK4kco2o3zaEyDgE6pU9lVuJQV9 mALw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=NiU9JeTONi6SPpWxtrTKBBxl6LhAdersmwuDpjHhYPA=; fh=HFig/pKocV6SXRBN9qIlf/zCijFV+B3eVbbTXReFxSY=; b=BlGQUPXhqEyaNvJ9QwKCxNIcyUHmaLTfnj5uarDq74Pp3mUBaMD+runqbTmBbnQFRn jGGe6OSzq0rsa4i2Z0jgVBQsYgMxnr+nnNcsFsR/06QP/NkjhoDIesZsp9UxMhG2F6J0 KxbJi8CxtqCjLacb2cvJ/ew2kl8ClcNdLMazzTzcQ6L2pG7KJLIGgwp1Y4FM37Q0wmEd ABNbZ/qqbjCt52OjUuLccSvAYypXLgTxVUgJo+nLaA2gr/uVtgmO0rPl6RxQ98WeD1WP /VIXd8DUCyJs6ei6+VbCnp2qp7EkNXslUSLvpOKRB5N0LgpvSvLN9pgRt454KmXhg7xD 5YDw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="XdC/ybVa"; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46790-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46790-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWHopPal7KiJq5+07a0SviNZ87lKh+3RzZXlxPtYytoXVNP1lTIQCXPV3EvBD9RUSJu5T9pdYLY9+XTN2txnNfZ1dgWuQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718434; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NiU9JeTONi6SPpWxtrTKBBxl6LhAdersmwuDpjHhYPA=; b=XdC/ybVaJgze3rlc55aeI7jIFbcIdjhJtrbVll+GoEUT7jvPSXul1qHL33F3a05beujHtF SxRZkFeySJPB/x2vT/Xs5LFjBlL+AqyYLVJACbwsIgCDEha2h3dXQuup7eTLkVRkf/Qudl EM+Z1JLx9XCLQLGgT02gNXYiMQmvJtt1GAhyCl+3lfc8HHhEOTTGa5XTFY7p4njO+0Xy+1 sdF8DWxYjHmXhuBY1oFdFkk4tFrbOipx/tV6wu0paRm47HNPueQ1QX+QWkLMTFEX2lIhl3 UgiLUu/WjrRZkmyzw45+CsydZ2wig+9UjrXp4vUvxDIY9m3+lW6TtFjZd4bFgQ== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:17 +0100 Subject: [PATCH v4 04/18] dt-bindings: clock: mobileye,eyeq5-clk: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-4-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624142236591558 X-GMAIL-MSGID: 1789624142236591558 Add DT schema bindings for the EyeQ5 clock controller driver. Signed-off-by: Théo Lebrun --- .../bindings/clock/mobileye,eyeq5-clk.yaml | 52 ++++++++++++++++++++++ MAINTAINERS | 2 + include/dt-bindings/clock/mobileye,eyeq5-clk.h | 22 +++++++++ 3 files changed, 76 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml new file mode 100644 index 000000000000..44eff4618ca7 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/mobileye,eyeq5-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 clock controller + +description: + The EyeQ5 clock controller handles 10 read-only PLLs derived from the main + crystal clock. It also exposes one divider clock, a child of one of the PLLs. + Its registers live in a shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-clk + + reg: + minItems: 2 + maxItems: 2 + + reg-names: + items: + - const: plls + - const: ospi + + "#clock-cells": + const: 1 + + clocks: + maxItems: 1 + description: + Input parent clock to all PLLs. Expected to be the main crystal. + + clock-names: + items: + - const: ref + +required: + - compatible + - reg + - reg-names + - "#clock-cells" + - clocks + - clock-names + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 260bcfc6da8f..42db14d184be 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14786,10 +14786,12 @@ M: Gregory CLEMENT M: Théo Lebrun L: linux-mips@vger.kernel.org S: Maintained +F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h MODULE SUPPORT diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h new file mode 100644 index 000000000000..26d8930335e4 --- /dev/null +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H +#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H + +#define EQ5C_PLL_CPU 0 +#define EQ5C_PLL_VMP 1 +#define EQ5C_PLL_PMA 2 +#define EQ5C_PLL_VDI 3 +#define EQ5C_PLL_DDR0 4 +#define EQ5C_PLL_PCI 5 +#define EQ5C_PLL_PER 6 +#define EQ5C_PLL_PMAC 7 +#define EQ5C_PLL_MPC 8 +#define EQ5C_PLL_DDR1 9 + +#define EQ5C_DIV_OSPI 10 + +#endif From patchwork Wed Jan 31 16:26:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194842 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2006653dyb; Wed, 31 Jan 2024 08:29:50 -0800 (PST) X-Google-Smtp-Source: AGHT+IEcJEvzTrIaQPhLycWyXLcJc/FPGsoKNWJlxw2i9DoR9jEtj7rdViPQ9OYwD4TvA0HVzRCp X-Received: by 2002:a05:6871:340a:b0:214:e186:4d3f with SMTP id nh10-20020a056871340a00b00214e1864d3fmr2070184oac.26.1706718590296; Wed, 31 Jan 2024 08:29:50 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718590; cv=pass; d=google.com; s=arc-20160816; b=eoLfBXOVJ6CLZJKPo9I9hkpH4E+NGz3kO5V3E7r7GZG8TOHP17YLQn6sYiLOB0WyX8 MuOBDCZu2LZbSVlgXAj1kiCcDjakDcIPSbQbBVpG223I2alRdyJwjZMKFEq2krJTMu+1 L5uSuB5yiA2HpHWp5WVKV3VtaydR2Mndtxu2fvynAuXm9pWmHEACsV6AIRJ1Uy228sWZ vmftY/kWpJ5zhERjLyLka5eD+Cc9OjZ7+Dstt8BX/yKtzx3t4fXGtV4TOB2XYwQYraQ5 IDL+Nivvf6wzoKtVTiItw0/nBMb4oqUqrBT3Q3OROvYzp7hkXyUOYOZlmmWA7j6qgEbx cylA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=pjr4Vnej4PwH+rguhrbjhD7u4xdrgrLHVVHhEAIkmuI=; fh=ArA+lvvVlGmT/TplU1zMgTyRxi1ubUec6MptMf08jdk=; b=SkpmOat7gDExapSErdF8K8UZJL3jmlxg2M5d/4ieQuAZwJfn1rYb1j08OZ1T4ejsht 49SA0/3LWYUydyQPzXz56VbyADSV9qROSqwnOVThv70NHLVQ3Siq4GY9c8BGMFv1vRzU Zu4xU8N9vDHbuygf7V+yxQocsRTRvgQF++hpPDEXsxIaWM9EsoBV/tNpXoSiX29Vw9xk /vcmiVlMsPekI0M20kwMOKpMAa8J0Vd9dFnWtBAqasNJbhuzVRkd6e4h+jySQxP76m8v 8b3ga7DeErHaKmA+4mNbVLl4RwvOhpvlNDJrJcI1hDM4IN/HPoCarS50sLc2XqGoT/Je W6ug==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=hO4O5qsr; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46791-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46791-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWJIdEdsIk6op9ttAG4nAgs3bpjZC4npeGf+SMldOkH65MX6FMvxR2K8+KBRcO/yaCTcIJYRMF4qRdfMCsMNQaxewaQsw== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Théo Lebrun --- .../bindings/reset/mobileye,eyeq5-reset.yaml | 44 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 45 insertions(+) diff --git a/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml new file mode 100644 index 000000000000..6b412f867d0d --- /dev/null +++ b/Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml @@ -0,0 +1,44 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/mobileye,eyeq5-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 reset controller + +description: + The EyeQ5 reset driver handles three reset domains. Its registers live in a + shared region called OLB. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +properties: + compatible: + const: mobileye,eyeq5-reset + + reg: + minItems: 3 + maxItems: 3 + + reg-names: + items: + - const: d0 + - const: d1 + - const: d2 + + "#reset-cells": + const: 2 + description: + The first cell is the domain (0 to 2 inclusive) and the second one is the + reset index inside that domain. + +required: + - compatible + - reg + - reg-names + - "#reset-cells" + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index 42db14d184be..e81c4db22df3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14788,6 +14788,7 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S From patchwork Wed Jan 31 16:26:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194846 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2007658dyb; Wed, 31 Jan 2024 08:31:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFvdwJ4LfulkvAoqVuqBqcoJw9g1sStf/PTWNE7St36/MQvVJpsacbrEfdpX7vr4YWQ6zTv X-Received: by 2002:a05:6a20:2d2c:b0:19e:34c8:41e1 with SMTP id g44-20020a056a202d2c00b0019e34c841e1mr2400956pzl.26.1706718677911; Wed, 31 Jan 2024 08:31:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718677; cv=pass; d=google.com; s=arc-20160816; b=VRjHw7JT7q6Tq66xRDANp5VM3AZ6SVS1nde/UtHsi7BIUdEdlRCKTJ5+jBA4IkZlwf yAc7W8k8oXGX8XKZI4zIlBxqheioVl+JVwekweYqrMFToM34GvXJCZsbr3WGigGtIgR7 1u776W9gMqs7b7IWx76DxtV+L7s9dasqlhgJE0cUkV3tq5tDFm6b6m26PTpwdXchRTW3 n7CNOAvmDvu1BSi8uhu7IOTdFM536Mh9HyNiPTCIcsofxYMMpdBq8LrGdpD25QYCjBZT Y9prfJC0GgJY4cInVMcZbhH5KXKbYQjDOoSAXC7Ee1hTLyg4acrGq3blNLSBFrhXweRq uOcw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=1lYG+4WAZ4wREntAb7qiLyWaW807YoI2Ojoj+scYjxY=; fh=arojRr/5NxIdQAsY0m+dpS1jsOZE659H5+sQHb+FCf0=; b=wCaGpLrav76pg1lN5Jkd2uxDBb9srTxcJTUCZesu2p+uj47UIl2FVGsmRtd3wUdQKV 8QDicIgPezuQBpANBUh8QRAEh/PaN+b9vyyxuH72/qIpWCbSeU9FxwJRX6UMjvrltKsm GWGLI+vGj++LMIX4QEllm4PSnypjnNqAReo/ajc5DlD8pkbmh8ALPWbWs+ERfbFOrtJo WjTN34krAEyEfD+uXuubYbuP5nxOgyF9suuXsoubChoO8j8NC0R+iEBkRr6lTwLAwzMn ZxcOB4ASorKjVRnqgwZS8YzR+qR15cEhzJAlRepnR8lRiOYyjPstOsztK2Ej7ZucTTj/ 7QDQ==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=dPu2XLIW; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46792-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46792-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWctGUv682P5+E6HPt1ywFT/cOGGiWifNp3hZHA5zcQMDcRUtMvPCNjUOQfBg9A8fQxQPcVvyqevanUa+Zsus+44RaYpg== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718435; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1lYG+4WAZ4wREntAb7qiLyWaW807YoI2Ojoj+scYjxY=; b=dPu2XLIWnpBi40Qf7fV2F7F/Y1jdJ/PGQaboIFCDakfPtc1BcGSOrUYu6EZqkVOXvhwUVv GNHBjw3oYIx6LIP8R5dcLI9jsvsf0QSITebA2JZRhcv/P6URCOvJ3zkXL8t4D26Cn+bPkZ t/OTLk4Io7MVgF/6705dcbH37OecDShyDZ71K1muET6VMcUOIqNclWtVnv5j1dpLJb63cA e/WuJRZxr2208x9l0vhe9sBI4k0uPhQR2otnoTroHDQ8rFct7/DpUQPddPVIDVOBvbnXMX bdV+8k2NHwyCZA6zCizVZPc2S0om4tgEFce9jk9BkSmuOn2MJxi3tqNzV+NsMw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:19 +0100 Subject: [PATCH v4 06/18] dt-bindings: pinctrl: mobileye,eyeq5-pinctrl: add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-6-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624244390863236 X-GMAIL-MSGID: 1789624244390863236 Add dt-schema type bindings for the Mobileye EyeQ5 pin controller. Signed-off-by: Théo Lebrun Reviewed-by: Rob Herring --- .../bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml | 242 +++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 243 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml new file mode 100644 index 000000000000..5f00604bf48c --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml @@ -0,0 +1,242 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 pin controller + +description: > + The EyeQ5 pin controller handles the two pin banks of the system. It belongs + to a system-controller block called OLB. + + Pin control is about bias (pull-down, pull-up), drive strength and muxing. Pin + muxing supports two functions for each pin: first is GPIO, second is + pin-dependent. + + Pins and groups are bijective. + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +$ref: pinctrl.yaml# + +properties: + compatible: + enum: + - mobileye,eyeq5-pinctrl + + reg: + maxItems: 1 + +patternProperties: + "-pins?$": + type: object + description: Pin muxing configuration. + $ref: pinmux-node.yaml# + additionalProperties: false + properties: + pins: true + function: + enum: [gpio, + # Bank A + timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0, + spi1, refclk0, + # Bank B + timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0] + bias-disable: true + bias-pull-down: true + bias-pull-up: true + drive-strength: true + required: + - pins + - function + allOf: + - if: + properties: + function: + const: gpio + then: + properties: + pins: + items: # PA0 - PA28, PB0 - PB22 + pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$' + - if: + properties: + function: + const: timer0 + then: + properties: + pins: + items: + enum: [PA0, PA1] + - if: + properties: + function: + const: timer1 + then: + properties: + pins: + items: + enum: [PA2, PA3] + - if: + properties: + function: + const: timer2 + then: + properties: + pins: + items: + enum: [PA4, PA5] + - if: + properties: + function: + const: timer5 + then: + properties: + pins: + items: + enum: [PA6, PA7, PA8, PA9] + - if: + properties: + function: + const: uart0 + then: + properties: + pins: + items: + enum: [PA10, PA11] + - if: + properties: + function: + const: uart1 + then: + properties: + pins: + items: + enum: [PA12, PA13] + - if: + properties: + function: + const: can0 + then: + properties: + pins: + items: + enum: [PA14, PA15] + - if: + properties: + function: + const: can1 + then: + properties: + pins: + items: + enum: [PA16, PA17] + - if: + properties: + function: + const: spi0 + then: + properties: + pins: + items: + enum: [PA18, PA19, PA20, PA21, PA22] + - if: + properties: + function: + const: spi1 + then: + properties: + pins: + items: + enum: [PA23, PA24, PA25, PA26, PA27] + - if: + properties: + function: + const: refclk0 + then: + properties: + pins: + items: + enum: [PA28] + - if: + properties: + function: + const: timer3 + then: + properties: + pins: + items: + enum: [PB0, PB1] + - if: + properties: + function: + const: timer4 + then: + properties: + pins: + items: + enum: [PB2, PB3] + - if: + properties: + function: + const: timer6 + then: + properties: + pins: + items: + enum: [PB4, PB5, PB6, PB7] + - if: + properties: + function: + const: uart2 + then: + properties: + pins: + items: + enum: [PB8, PB9] + - if: + properties: + function: + const: can2 + then: + properties: + pins: + items: + enum: [PB10, PB11] + - if: + properties: + function: + const: spi2 + then: + properties: + pins: + items: + enum: [PB12, PB13, PB14, PB15, PB16] + - if: + properties: + function: + const: spi3 + then: + properties: + pins: + items: + enum: [PB17, PB18, PB19, PB20, PB21] + - if: + properties: + function: + const: mclk0 + then: + properties: + pins: + items: + enum: [PB22] + +required: + - compatible + - reg + +additionalProperties: false diff --git a/MAINTAINERS b/MAINTAINERS index e81c4db22df3..15c9987af637 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14788,6 +14788,7 @@ L: linux-mips@vger.kernel.org S: Maintained F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml +F: Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig From patchwork Wed Jan 31 16:26:20 2024 Content-Type: text/plain; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718436; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KfF9UjR1RJ0Efc0NY0CaMI2Wy+q2hxRGYq2bx2zOXf0=; b=jlf1jxKDDwakyKV0EZBVfcpX91XhVNtFf6uNBpiNsa+ajpz1YjXybHMNlVIUPo9IMLOfue r6w4TWls4xcFUxeu7WhBIP6KT35TR4LyrulEDgKvQoOe7uF5D8q6VXNV70A0HnO1o80JJF snFjESSE3rco/d2ISegBhPlAFXwX6yZ/45bDTW2z2TnsN3s9ZjZFJ0/UOeF0HCD+fR4kbg 4aquosYOZKsZM3dZClqoeuZA1t5MX5VwVHtULenCVCBslzF8eOS2Emss6R3KBBUeLBGA7L 75K5qM7D8A00f18R8hU2tlma+icKhFr7ZT6brlfIVMzOx+4DkbczwLormhKh7g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:20 +0100 Subject: [PATCH v4 07/18] dt-bindings: soc: mobileye: add EyeQ5 OLB system controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-7-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624188225769259 X-GMAIL-MSGID: 1789624188225769259 Add documentation to describe the "Other Logic Block" syscon. Signed-off-by: Théo Lebrun --- .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 89 ++++++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 90 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml new file mode 100644 index 000000000000..92d8e30fdc27 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mobileye EyeQ5 SoC system controller + +maintainers: + - Grégory Clement + - Théo Lebrun + - Vladimir Kondratiev + +description: + OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks, + resets, pinctrl are being handled from here. + +properties: + compatible: + items: + - const: mobileye,eyeq5-olb + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^clock-controller@[0-9a-f]+$": + $ref: /schemas/clock/mobileye,eyeq5-clk.yaml# + + "^reset-controller@[0-9a-f]+$": + $ref: /schemas/reset/mobileye,eyeq5-reset.yaml# + + "^pinctrl@[0-9a-f]+$": + $ref: /schemas/pinctrl/mobileye,eyeq5-pinctrl.yaml# + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - ranges + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + system-controller@e00000 { + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; + reg = <0x0 0xe00000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x0 0xe00000 0x400>; + + clocks: clock-controller@2c { + compatible = "mobileye,eyeq5-clk"; + reg = <0x02C 0x50>, <0x11C 0x04>; + reg-names = "plls", "ospi"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; + + reset: reset-controller@0 { + compatible = "mobileye,eyeq5-reset"; + reg = <0x000 0x0C>, <0x200 0x34>, <0x120 0x04>; + reg-names = "d0", "d1", "d2"; + #reset-cells = <2>; + }; + + pinctrl: pinctrl@b0 { + compatible = "mobileye,eyeq5-pinctrl"; + reg = <0x0B0 0x30>; + }; + }; + }; diff --git a/MAINTAINERS b/MAINTAINERS index 15c9987af637..886de494df31 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14790,6 +14790,7 @@ F: Documentation/devicetree/bindings/clock/mobileye,eyeq5-clk.yaml F: Documentation/devicetree/bindings/mips/mobileye.yaml F: Documentation/devicetree/bindings/pinctrl/mobileye,eyeq5-pinctrl.yaml F: Documentation/devicetree/bindings/reset/mobileye,eyeq5-reset.yaml +F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S From patchwork Wed Jan 31 16:26:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194849 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2007940dyb; Wed, 31 Jan 2024 08:31:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IE6e0SZ9bRIHnt5QT+eulVTWX6d0NdMT3t87VphwWKYyKcOVn7sfWmVz2yHkJ85r0bR0Ubj X-Received: by 2002:a05:6870:a2cb:b0:203:d7a8:b4ff with SMTP id w11-20020a056870a2cb00b00203d7a8b4ffmr2359028oak.33.1706718698384; Wed, 31 Jan 2024 08:31:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718698; cv=pass; d=google.com; s=arc-20160816; b=nqqOyMWb2+WrcFzQjQojkIiGm+h/PJcjfQGFJHI86KYfnjyWQg9YjdUWhUj2HVD1eQ fhcywRc0B/wCmERQ4naPAnTlopuzEG/ujsFMn1bDzzZ/gD/3MGXUAloy45eRAUUaPJCu dBnIhGRBKrp8FL30LbcJL0q7bOzyFviXaOVjvNsNuvAFZTk5PLXS19aHvC/sJJT8wdUu qgR9FyQU8i2jnsYW/v34Eur5hkNkcUVoMwgXs962plS6KdrwvU/4EIbtezxMcMh8Jf+q pC+Cez9/eUZHDB5oXrnR3ejhWrE61Dw6kQLe/h1H8suLorTyH0PTUdiynsNZWkvaT6eE 9wPw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=6wWAKjXHYLvs9ydAuurhRS1f37EpyPYXy2YxK+NL2h4=; fh=6LR7Bk5bsdz2zM6M/JlGjSC42L4k/rxKYQN0++TwtOg=; b=wXI6tQ1neEIBXoqVc4jbfXXUbGL5W7t/3A/8k+4YSOjH+LxFoesQsUIJgUd2FHWExW 7iJfeED4gdUK3fdLsMO3EMy93RySuVEVTDmBJB5Zjgp/rlTI+xCpxXnus0jEovJZx0fN pjXEQOQk1ZHZ/IEj4eoIvSPuhYqwgI4lL6f+TNGcWErD1LnxMyWM9n7/c6wpME8byp2B iRWdn9eqkT96m8qN9oSbHfwq2Aqv55KgyleqBuo0Q08hd9wRHOalyX5YdxPvKlsmS8tz PJ0ER4RxLYrCkr053ZnVRyJZeGlfZ0ravdO038Z9tl+Nd2OougJpQBZveUOxkt5W2/dn LYRA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=ECq5363t; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46794-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46794-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCVU8DnUU7+MfOjImRuajYLWpdv6OWwZotBNSQcBy5dXhiyqSLFHTLl8EplVHh+xhHqDwzahU/vLRVOgxmblcF79LggZ7A== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id s69-20020a637748000000b005b96d038729si3854803pgc.728.2024.01.31.08.31.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 08:31:38 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-46794-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=ECq5363t; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46794-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46794-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 30A9C286861 for ; Wed, 31 Jan 2024 16:31:10 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1E2E213D504; Wed, 31 Jan 2024 16:27:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="ECq5363t" Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B9EBF12AAFD; Wed, 31 Jan 2024 16:27:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718442; cv=none; b=Xl6R+yz8pcQB55M3jIs7cCTNVjW+V+BVGD+xpm5DZLT7wVfjYDCt+OpsGZKc4Wpv88Ww2nAzraK0wfqc8b0USBhXYXJB0dNT/CmOUo04sWljpZSwuZjxmxzdXVB84GZfah5MeSigVwZEPKoo9RrYmqyLZ0+Cvpm8iLwCYZaONi4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718442; c=relaxed/simple; bh=Kh2fWI2Rf7ml04o+X4yBLYXyNCY7UwwPkcCMOvHEMZ4=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oImykRwP8jk6sUxlZ7oaJnq97hfJp8uv8LuZ+cJ/SQoDQ/pdZ/q3hW2jboYyQx2Lpl4eI5cx+K+rhnwdvOacHfbdgVIih9UM8vAs1mGJxinHe/vGiKhIgemCxeIpVQfpzVWxZRqlpJ5JfbO+G/TJQJKDcr20OV0GGRtOss+lze8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=ECq5363t; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 6F3634000E; Wed, 31 Jan 2024 16:27:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6wWAKjXHYLvs9ydAuurhRS1f37EpyPYXy2YxK+NL2h4=; b=ECq5363tjSXFzsC2ArPoiyIFJw5eh/anM00XeJxYgFi1lScpPJJY1xEC/rrlFL/EbNeOiw CN8XOT0oDGEB8D3KhHPzIdZC07/hzdIYBBNBBBwkCe7ODGx8Mdal9bvNsIBo1NCTkT/ooO pVuQxb3m84ZkWSz0O9qMldR4NmOPgwPXoXqJ0qqzRzku9XpHsfqqK5WSrxHrq1pkY3uh3L h71YRsZ6rKVKJGlT50klzL2hjE23VaEbkda1dMUiPggOSTR+gF/Ip+nsSG1LDE6/nb9sWK ykg91nEGdOloPV5yyyNgE6Ib3c6GF77RxDZI/7ri/tTOoJs+O4jODgNl7URarg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:21 +0100 Subject: [PATCH v4 08/18] clk: eyeq5: add platform driver, and init routine at of_clk_init() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-8-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624265682316250 X-GMAIL-MSGID: 1789624265682316250 Add the Mobileye EyeQ5 clock controller driver. It might grow to add support for other platforms from Mobileye. It handles 10 read-only PLLs derived from the main crystal on board. It exposes a table-based divider clock used for OSPI. Other platform clocks are not configurable and therefore kept as fixed-factor devicetree nodes. Two PLLs are required early on and are therefore registered at of_clk_init(). Those are pll-cpu for the GIC timer and pll-per for the UARTs. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/clk/Kconfig | 11 ++ drivers/clk/Makefile | 1 + drivers/clk/clk-eyeq5.c | 289 ++++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 302 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 886de494df31..1d621e14dc95 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14794,6 +14794,7 @@ F: Documentation/devicetree/bindings/soc/mobileye/ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S +F: drivers/clk/clk-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig index 50af5fc7f570..d5043ce2a75c 100644 --- a/drivers/clk/Kconfig +++ b/drivers/clk/Kconfig @@ -218,6 +218,17 @@ config COMMON_CLK_EN7523 This driver provides the fixed clocks and gates present on Airoha ARM silicon. +config COMMON_CLK_EYEQ5 + bool "Clock driver for the Mobileye EyeQ5 platform" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + default MACH_EYEQ5 + help + This driver provides the clocks found on the Mobileye EyeQ5 SoC. Its + registers live in a shared register region called OLB. It provides 10 + read-only PLLs derived from the main crystal clock which must be constant + and one divider clock based on one PLL. + config COMMON_CLK_FSL_FLEXSPI tristate "Clock driver for FlexSPI on Layerscape SoCs" depends on ARCH_LAYERSCAPE || COMPILE_TEST diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile index 14fa8d4ecc1f..81c4d11ca437 100644 --- a/drivers/clk/Makefile +++ b/drivers/clk/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_ARCH_CLPS711X) += clk-clps711x.o obj-$(CONFIG_COMMON_CLK_CS2000_CP) += clk-cs2000-cp.o obj-$(CONFIG_ARCH_SPARX5) += clk-sparx5.o obj-$(CONFIG_COMMON_CLK_EN7523) += clk-en7523.o +obj-$(CONFIG_COMMON_CLK_EYEQ5) += clk-eyeq5.o obj-$(CONFIG_COMMON_CLK_FIXED_MMIO) += clk-fixed-mmio.o obj-$(CONFIG_COMMON_CLK_FSL_FLEXSPI) += clk-fsl-flexspi.o obj-$(CONFIG_COMMON_CLK_FSL_SAI) += clk-fsl-sai.o diff --git a/drivers/clk/clk-eyeq5.c b/drivers/clk/clk-eyeq5.c new file mode 100644 index 000000000000..9598139e0383 --- /dev/null +++ b/drivers/clk/clk-eyeq5.c @@ -0,0 +1,289 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * PLL clock driver for the Mobileye EyeQ5 platform. + * + * This controller handles 10 read-only PLLs, all derived from the same main + * crystal clock. It also exposes one divider clock, a child of one of the + * PLLs. The parent clock is expected to be constant. This driver's registers + * live in a shared region called OLB. Two PLLs must be initialized by + * of_clk_init(). + * + * We use eq5c_ as prefix, as-in "EyeQ5 Clock", but way shorter. + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#define pr_fmt(fmt) "clk-eyeq5: " fmt + +#include +#include +#include +#include +#include +#include + +#include + +/* In frac mode, it enables fractional noise canceling DAC. Else, no function. */ +#define PCSR0_DAC_EN BIT(0) +/* Fractional or integer mode */ +#define PCSR0_DSM_EN BIT(1) +#define PCSR0_PLL_EN BIT(2) +/* All clocks output held at 0 */ +#define PCSR0_FOUTPOSTDIV_EN BIT(3) +#define PCSR0_POST_DIV1 GENMASK(6, 4) +#define PCSR0_POST_DIV2 GENMASK(9, 7) +#define PCSR0_REF_DIV GENMASK(15, 10) +#define PCSR0_INTIN GENMASK(27, 16) +#define PCSR0_BYPASS BIT(28) +/* Bits 30..29 are reserved */ +#define PCSR0_PLL_LOCKED BIT(31) + +#define PCSR1_RESET BIT(0) +#define PCSR1_SSGC_DIV GENMASK(4, 1) +/* Spread amplitude (% = 0.1 * SPREAD[4:0]) */ +#define PCSR1_SPREAD GENMASK(9, 5) +#define PCSR1_DIS_SSCG BIT(10) +/* Down-spread or center-spread */ +#define PCSR1_DOWN_SPREAD BIT(11) +#define PCSR1_FRAC_IN GENMASK(31, 12) + +static struct clk_hw_onecell_data *eq5c_clk_data; + +struct eq5c_pll { + int index; + const char *name; + u32 reg; /* next 8 bytes are r0 and r1 */ +}; + +/* Required early for the GIC timer (pll-cpu) and UARTs (pll-per). */ +static const struct eq5c_pll eq5c_early_plls[] = { + { .index = EQ5C_PLL_CPU, .name = "pll-cpu", .reg = 0x00, }, + { .index = EQ5C_PLL_PER, .name = "pll-per", .reg = 0x30, }, +}; + +static const struct eq5c_pll eq5c_plls[] = { + { .index = EQ5C_PLL_VMP, .name = "pll-vmp", .reg = 0x08, }, + { .index = EQ5C_PLL_PMA, .name = "pll-pma", .reg = 0x10, }, + { .index = EQ5C_PLL_VDI, .name = "pll-vdi", .reg = 0x18, }, + { .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x20, }, + { .index = EQ5C_PLL_PCI, .name = "pll-pci", .reg = 0x28, }, + { .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x38, }, + { .index = EQ5C_PLL_MPC, .name = "pll-mpc", .reg = 0x40, }, + { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x48, }, +}; + +#define EQ5C_OSPI_DIV_CLK_NAME "div-ospi" +#define EQ5C_OSPI_DIV_WIDTH 4 + +#define EQ5C_NB_CLKS (ARRAY_SIZE(eq5c_early_plls) + ARRAY_SIZE(eq5c_plls) + 1) + +static const struct clk_div_table eq5c_ospi_div_table[] = { + { .val = 0, .div = 2 }, + { .val = 1, .div = 4 }, + { .val = 2, .div = 6 }, + { .val = 3, .div = 8 }, + { .val = 4, .div = 10 }, + { .val = 5, .div = 12 }, + { .val = 6, .div = 14 }, + { .val = 7, .div = 16 }, + {} /* sentinel */ +}; + +static int eq5c_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult, + unsigned long *div, unsigned long *acc) +{ + if (r0 & PCSR0_BYPASS) { + *mult = 1; + *div = 1; + *acc = 0; + return 0; + } + + if (!(r0 & PCSR0_PLL_LOCKED)) + return -EINVAL; + + *mult = FIELD_GET(PCSR0_INTIN, r0); + *div = FIELD_GET(PCSR0_REF_DIV, r0); + if (r0 & PCSR0_FOUTPOSTDIV_EN) + *div *= FIELD_GET(PCSR0_POST_DIV1, r0) * + FIELD_GET(PCSR0_POST_DIV2, r0); + + /* Fractional mode, in 2^20 (0x100000) parts. */ + if (r0 & PCSR0_DSM_EN) { + *div *= 0x100000; + *mult = *mult * 0x100000 + FIELD_GET(PCSR1_FRAC_IN, r1); + } + + if (!*mult || !*div) + return -EINVAL; + + /* Spread spectrum. */ + if (!(r1 & (PCSR1_RESET | PCSR1_DIS_SSCG))) { + /* + * Spread is 1/1000 parts of frequency, accuracy is half of + * that. To get accuracy, convert to ppb (parts per billion). + */ + u32 spread = FIELD_GET(PCSR1_SPREAD, r1); + *acc = spread * 500000; + if (r1 & PCSR1_DOWN_SPREAD) { + /* + * Downspreading: the central frequency is half a + * spread lower. + */ + *mult *= 2000 - spread; + *div *= 2000; + } + } else { + *acc = 0; + } + + return 0; +} + +static int eq5c_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + void __iomem *base_plls, *base_ospi; + struct clk_hw *hw; + int i; + + if (IS_ERR(eq5c_clk_data)) + return PTR_ERR(eq5c_clk_data); + else if (!eq5c_clk_data) + return -EINVAL; + + base_plls = devm_platform_ioremap_resource_byname(pdev, "plls"); + base_ospi = devm_platform_ioremap_resource_byname(pdev, "ospi"); + if (!base_plls || !base_ospi) + return -ENODEV; + + for (i = 0; i < ARRAY_SIZE(eq5c_plls); i++) { + const struct eq5c_pll *pll = &eq5c_plls[i]; + unsigned long mult, div, acc; + u32 r0, r1; + int ret; + + r0 = readl(base_plls + pll->reg); + r1 = readl(base_plls + pll->reg + sizeof(r0)); + + ret = eq5c_pll_parse_registers(r0, r1, &mult, &div, &acc); + if (ret) { + dev_warn(dev, "failed parsing state of %s\n", pll->name); + continue; + } + + hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev, np, + pll->name, "ref", 0, mult, div, acc); + eq5c_clk_data->hws[pll->index] = hw; + if (IS_ERR(hw)) { + dev_err(dev, "failed registering %s: %ld\n", + pll->name, PTR_ERR(hw)); + } + } + + hw = clk_hw_register_divider_table_parent_hw(dev, EQ5C_OSPI_DIV_CLK_NAME, + eq5c_clk_data->hws[EQ5C_PLL_PER], 0, + base_ospi, 0, EQ5C_OSPI_DIV_WIDTH, 0, + eq5c_ospi_div_table, NULL); + eq5c_clk_data->hws[EQ5C_DIV_OSPI] = hw; + if (IS_ERR(hw)) { + dev_err(dev, "failed registering %s: %ld\n", + EQ5C_OSPI_DIV_CLK_NAME, PTR_ERR(hw)); + } + + return 0; +} + +static const struct of_device_id eq5c_match_table[] = { + { .compatible = "mobileye,eyeq5-clk" }, + {} +}; +MODULE_DEVICE_TABLE(of, eq5c_match_table); + +static struct platform_driver eq5c_driver = { + .probe = eq5c_probe, + .driver = { + .name = "clk-eyeq5", + .of_match_table = eq5c_match_table, + }, +}; + +builtin_platform_driver(eq5c_driver); + +static void __init eq5c_init(struct device_node *np) +{ + void __iomem *base_plls, *base_ospi; + int index_plls, index_ospi; + int i, ret; + + eq5c_clk_data = kzalloc(struct_size(eq5c_clk_data, hws, EQ5C_NB_CLKS), + GFP_KERNEL); + if (!eq5c_clk_data) { + ret = -ENOMEM; + goto err; + } + + eq5c_clk_data->num = EQ5C_NB_CLKS; + + /* + * Mark all clocks as deferred. We register some now and others at + * platform device probe. + */ + for (i = 0; i < EQ5C_NB_CLKS; i++) + eq5c_clk_data->hws[i] = ERR_PTR(-EPROBE_DEFER); + + index_plls = of_property_match_string(np, "reg-names", "plls"); + index_ospi = of_property_match_string(np, "reg-names", "ospi"); + if (index_plls < 0 || index_ospi < 0) { + ret = -ENODEV; + goto err; + } + + base_plls = of_iomap(np, index_plls); + base_ospi = of_iomap(np, index_ospi); + if (!base_plls || !base_ospi) { + ret = -ENODEV; + goto err; + } + + for (i = 0; i < ARRAY_SIZE(eq5c_early_plls); i++) { + const struct eq5c_pll *pll = &eq5c_early_plls[i]; + unsigned long mult, div, acc; + struct clk_hw *hw; + u32 r0, r1; + + r0 = readl(base_plls + pll->reg); + r1 = readl(base_plls + pll->reg + sizeof(r0)); + + ret = eq5c_pll_parse_registers(r0, r1, &mult, &div, &acc); + if (ret) { + pr_warn("failed parsing state of %s\n", pll->name); + continue; + } + + hw = clk_hw_register_fixed_factor_with_accuracy_fwname(NULL, + np, pll->name, "ref", 0, mult, div, acc); + eq5c_clk_data->hws[pll->index] = hw; + if (IS_ERR(hw)) { + pr_err("failed registering %s: %ld\n", + pll->name, PTR_ERR(hw)); + } + } + + ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, eq5c_clk_data); + if (ret) { + pr_err("failed registering clk provider: %d\n", ret); + goto err; + } + + return; + +err: + kfree(eq5c_clk_data); + /* Signal to platform driver probe that we failed init. */ + eq5c_clk_data = ERR_PTR(ret); +} + +CLK_OF_DECLARE_DRIVER(eq5c, "mobileye,eyeq5-clk", eq5c_init); From patchwork Wed Jan 31 16:26:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194847 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2007696dyb; Wed, 31 Jan 2024 08:31:20 -0800 (PST) X-Google-Smtp-Source: AGHT+IF4QthgzmBIFR/yfkWjIvcJfsAXUhDAXUZiW0Imx+4A/CiMy7iVhMUq9puGc3qZX9tdiNvv X-Received: by 2002:a05:6214:2589:b0:681:7d81:705b with SMTP id fq9-20020a056214258900b006817d81705bmr2424349qvb.4.1706718680658; Wed, 31 Jan 2024 08:31:20 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718680; cv=pass; d=google.com; s=arc-20160816; b=zzThFbAsP1rQZXvQtR6snofjcW+DovihVMckrAuDiSKo521gmzjaN2Jh7cZM9is84C eZqfMoLvv/RQOBWeXWluGgYtnLXE8boHh+4dNsBZlDoCdtjtVg8+thT89o43BI5E5CYo X/4WsyzTZ3Sxy1hdiKnt5bpzZ9DV/LK1oi0t16lmE4Pa0sKPeaVUCQ4UjK/n7QlQ/aDI GNsRHKXia8sWOtpHIIdDQuC54wplpdfVxz1RnFzyVdsX1VXbAdNNA1FmAe1klLPFkz45 4JAL2VYgcZPkvfHFWnrqNoVDIL40jxSljC2Nzyrdq+JjVRfEA1i9LFYYMs9Of+ULL7Zx oiFw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=upfj24gVT/veWe/jt2WpVMTfu8Jv9s5AFqkQcjOFxU8=; fh=oi0WTz0GA8heBrEjVF0EGz1LfKKJhtCBWQ2nOg+qaRI=; b=JWK+OJX3nhzSG3I2dFIVFUacyREvhduzYtexsdTrwL4J5TYtruz5W0bsN/H9E+BEa9 /FLh6v+mCZkjR3C7Ou4DWu5AkSgJ5jIG32/4Q6QT/pk8T+fFUG8sHyrTxUgjg20Yfrtv p56E6ztNh2ymWkMgMvEz/fnIBK5e22/5q6QXvJHZeQAgljJ64cYRE3Ak3JetUnMD0N0D mB59d56egA5J6WyWj1GnuSjuWMtEd63PSy0nJDm6eOzAvXnCh01VlmPLQL0S7VliNNqw 3ENz/ZWbZlrfnX9hNMCG8TqJa6fYquACsO2zMlxHWyfGtNxB3T3JqeQAVN/zsszfGSi1 gaww==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=J8MIa1Ae; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46795-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46795-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCXukRkHGmaNPlO8gTr5ptpTfzRKv6Wo7r92M/+3L6ZKnzL8CLQB4D7kKEnqoUrfgAH+ZCWhchzKVmLUXYVNx/0N/FyQww== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id gv9-20020a056214262900b0068c65b5065csi2980842qvb.303.2024.01.31.08.31.20 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 08:31:20 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-46795-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=J8MIa1Ae; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46795-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46795-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 648441C25EB8 for ; Wed, 31 Jan 2024 16:31:20 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 91C1913D51F; Wed, 31 Jan 2024 16:27:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="J8MIa1Ae" Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9280D12CD87; Wed, 31 Jan 2024 16:27:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718442; cv=none; b=SZ92+hDc47r5VgpmpKhtOsCVPSXtPlcEE1ZlJTFgypamejKnAw7d+q7pdlj8LsoPybpH2Kbs2Z3D/EluLYTNY1HL9yPuG6+HYB7d+2dSKbkLD5BNJs+rn5jyhnW3HVknhu+Z9tERvqTpdUfrJkTE/D1si6sP2w5sMHtF6u78noI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718442; c=relaxed/simple; bh=Zz0IimLVNcJHf7q6qgxG8tMencR1tlz76iMV6+xph6M=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=X9UDWufYuvNtSbi+xBWTejs7rsR9tmSrwAYrhXTE9z1fPyKkdIB8Oksyleq856VKo2L/PysW4FkjnxQgpslIqYwZzScZenbnQSWN1zRmzGmkZsMdCZRJwxHSLC+nsA6YwWBn9RvvzIhg2pK5+H2D7d9L+6Jw3F7DZ8RI5q6DsjU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=J8MIa1Ae; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 2431F4000C; Wed, 31 Jan 2024 16:27:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718437; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=upfj24gVT/veWe/jt2WpVMTfu8Jv9s5AFqkQcjOFxU8=; b=J8MIa1AeHcTtC2YPa5w6dDIgXe3SwD9rSLg4EAFg2IT7RImENZafNPVuwS/4DpEhMPRRU/ c68DfX8pqRfB4iee2/7wydqw0wu6sq2r0XCqI5TbWRNC+CwbcE/kixV2H6l3Yx6gQ/Qv1+ /RH1so1kvFh+43T5WsexWMY4+JJg6im5udAmOGqI7J/CexMtwhFsGDYHQHTfv8sEEBlnTb 9nhE+z+v3+qEY+xfJR8Oz8EYpqZuB6lj/Kwzxx/qas+RVMNVxohaHOAh+punYVuwe4aDy7 /SZK1rofYxQizZMyWtTaPy0+0NQ21vx7DGyzLQkHecaN8FuDgAgxTNiEIkci3g== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:22 +0100 Subject: [PATCH v4 09/18] reset: eyeq5: add platform driver Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-9-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624247372925703 X-GMAIL-MSGID: 1789624247372925703 Add the Mobileye EyeQ5 reset controller driver. It belongs to a syscon region called OLB. It might grow to add later support of other platforms from Mobileye. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/reset/Kconfig | 12 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-eyeq5.c | 342 ++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 356 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 1d621e14dc95..72edb390a046 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14795,6 +14795,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq5.c +F: drivers/reset/reset-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index ccd59ddd7610..80bfde54c076 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,18 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. +config RESET_EYEQ5 + bool "Mobileye EyeQ5 reset controller" + depends on MFD_SYSCON + depends on MACH_EYEQ5 || COMPILE_TEST + default MACH_EYEQ5 + help + This enables the Mobileye EyeQ5 reset controller. + + It has three domains, with a varying number of resets in each of them. + Registers are located in a shared register region called OLB accessed + through a syscon & regmap. + config RESET_HSDK bool "Synopsys HSDK Reset Driver" depends on HAS_IOMEM diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 8270da8a4baa..4fabe0070390 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -11,6 +11,7 @@ obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) += reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) += reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) += reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_EYEQ5) += reset-eyeq5.o obj-$(CONFIG_RESET_HSDK) += reset-hsdk.o obj-$(CONFIG_RESET_IMX7) += reset-imx7.o obj-$(CONFIG_RESET_INTEL_GW) += reset-intel-gw.o diff --git a/drivers/reset/reset-eyeq5.c b/drivers/reset/reset-eyeq5.c new file mode 100644 index 000000000000..f9d3935dd420 --- /dev/null +++ b/drivers/reset/reset-eyeq5.c @@ -0,0 +1,342 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Reset driver for the Mobileye EyeQ5 platform. + * + * The registers are located in a syscon region called OLB. We handle three + * reset domains. Domains 0 and 2 look similar in that they both use one bit + * per reset line. Domain 1 has a register per reset. + * + * We busy-wait after updating a reset in domains 0 or 1. The reason is hardware + * logic built-in self-test (LBIST) that might be enabled. + * + * We use eq5r_ as prefix, as-in "EyeQ5 Reset", but way shorter. + * + * Known resets in domain 0: + * 3. CAN0 + * 4. CAN1 + * 5. CAN2 + * 6. SPI0 + * 7. SPI1 + * 8. SPI2 + * 9. SPI3 + * 10. UART0 + * 11. UART1 + * 12. UART2 + * 13. I2C0 + * 14. I2C1 + * 15. I2C2 + * 16. I2C3 + * 17. I2C4 + * 18. TIMER0 + * 19. TIMER1 + * 20. TIMER2 + * 21. TIMER3 + * 22. TIMER4 + * 23. WD0 + * 24. EXT0 + * 25. EXT1 + * 26. GPIO + * 27. WD1 + * + * Known resets in domain 1: + * 0. VMP0 (Vector Microcode Processors) + * 1. VMP1 + * 2. VMP2 + * 3. VMP3 + * 4. PMA0 (Programmable Macro Array) + * 5. PMA1 + * 6. PMAC0 + * 7. PMAC1 + * 8. MPC0 (Multi-threaded Processing Clusters) + * 9. MPC1 + * + * Known resets in domain 2: + * 0. PCIE0_CORE + * 1. PCIE0_APB + * 2. PCIE0_LINK_AXI + * 3. PCIE0_LINK_MGMT + * 4. PCIE0_LINK_HOT + * 5. PCIE0_LINK_PIPE + * 6. PCIE1_CORE + * 7. PCIE1_APB + * 8. PCIE1_LINK_AXI + * 9. PCIE1_LINK_MGMT + * 10. PCIE1_LINK_HOT + * 11. PCIE1_LINK_PIPE + * 12. MULTIPHY + * 13. MULTIPHY_APB + * 15. PCIE0_LINK_MGMT + * 16. PCIE1_LINK_MGMT + * 17. PCIE0_LINK_PM + * 18. PCIE1_LINK_PM + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/* Domain 0 register offsets */ +#define D0_SARCR0 (0x004) +#define D0_SARCR1 (0x008) + +/* Domain 1 masks */ +#define D1_ACRP_PD_REQ BIT(0) +#define D1_ACRP_ST_POWER_DOWN BIT(27) +#define D1_ACRP_ST_ACTIVE BIT(29) + +/* Vendor-provided timeout values. D1 has a long timeout because of LBIST. */ +#define D0_TIMEOUT_POLL 10 +#define D1_TIMEOUT_POLL 40000 + +/* + * Masks for valid reset lines in each domain. This array is also used to get + * the domain and reset counts. + */ +static const u32 eq5r_valid_masks[] = { 0x0FFFFFF8, 0x00001FFF, 0x0007BFFF }; + +#define EQ5R_DOMAIN_COUNT ARRAY_SIZE(eq5r_valid_masks) + +struct eq5r_private { + struct mutex mutexes[EQ5R_DOMAIN_COUNT]; + void __iomem *base_d0; + void __iomem *base_d1; + void __iomem *base_d2; + struct reset_controller_dev rcdev; +}; + +#define rcdev_to_priv(rcdev) container_of(rcdev, struct eq5r_private, rcdev) + +static int eq5r_busy_wait_withlock(struct eq5r_private *priv, + struct device *dev, u32 domain, u32 offset, + bool assert) +{ + unsigned int val, mask; + int i; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + for (i = 0; i < D0_TIMEOUT_POLL; i++) { + val = readl(priv->base_d0 + D0_SARCR1); + val = !(val & BIT(offset)); + if (val == assert) + return 0; + udelay(1); + } + break; + case 1: + mask = assert ? D1_ACRP_ST_POWER_DOWN : D1_ACRP_ST_ACTIVE; + for (i = 0; i < D1_TIMEOUT_POLL; i++) { + val = readl(priv->base_d1 + 4 * offset); + if (val & mask) + return 0; + udelay(1); + } + break; + case 2: + return 0; /* No busy waiting for domain 2. */ + default: + WARN_ON(1); + return -EINVAL; + } + + dev_dbg(dev, "%u-%u: timeout\n", domain, offset); + return -ETIMEDOUT; +} + +static void eq5r_assert_withlock(struct eq5r_private *priv, u32 domain, + u32 offset) +{ + void __iomem *reg; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + reg = priv->base_d0 + D0_SARCR0; + writel(readl(reg) & ~BIT(offset), reg); + break; + case 1: + reg = priv->base_d1 + 4 * offset; + writel(readl(reg) | D1_ACRP_PD_REQ, reg); + break; + case 2: + reg = priv->base_d2; + writel(readl(reg) & ~BIT(offset), reg); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_assert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + + dev_dbg(rcdev->dev, "%u-%u: assert request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + eq5r_assert_withlock(priv, domain, offset); + return eq5r_busy_wait_withlock(priv, rcdev->dev, domain, offset, true); +} + +static void eq5r_deassert_withlock(struct eq5r_private *priv, u32 domain, + u32 offset) +{ + void __iomem *reg; + + lockdep_assert_held(&priv->mutexes[domain]); + + switch (domain) { + case 0: + reg = priv->base_d0 + D0_SARCR0; + writel(readl(reg) | BIT(offset), reg); + break; + case 1: + reg = priv->base_d1 + 4 * offset; + writel(readl(reg) & ~D1_ACRP_PD_REQ, reg); + break; + case 2: + reg = priv->base_d2; + writel(readl(reg) | BIT(offset), reg); + break; + default: + WARN_ON(1); + } +} + +static int eq5r_deassert(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + + dev_dbg(rcdev->dev, "%u-%u: deassert request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + eq5r_deassert_withlock(priv, domain, offset); + return eq5r_busy_wait_withlock(priv, rcdev->dev, domain, offset, false); +} + +static int eq5r_status(struct reset_controller_dev *rcdev, unsigned long id) +{ + struct eq5r_private *priv = rcdev_to_priv(rcdev); + u32 offset = id & GENMASK(7, 0); + u32 domain = id >> 8; + u32 val; + + dev_dbg(rcdev->dev, "%u-%u: status request\n", domain, offset); + + guard(mutex)(&priv->mutexes[domain]); + + switch (domain) { + case 0: + val = readl(priv->base_d0 + D0_SARCR1); + return !(val & BIT(offset)); + case 1: + val = readl(priv->base_d1 + 4 * offset); + return !(val & D1_ACRP_ST_ACTIVE); + case 2: + val = readl(priv->base_d2); + return !(val & BIT(offset)); + default: + return -EINVAL; + } +} + +static const struct reset_control_ops eq5r_ops = { + .assert = eq5r_assert, + .deassert = eq5r_deassert, + .status = eq5r_status, +}; + +static int eq5r_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + u32 domain, offset; + + if (WARN_ON(reset_spec->args_count != 2)) + return -EINVAL; + + domain = reset_spec->args[0]; + offset = reset_spec->args[1]; + + if (domain >= EQ5R_DOMAIN_COUNT || offset > 31 || + !(eq5r_valid_masks[domain] & BIT(offset))) { + dev_err(rcdev->dev, "%u-%u: invalid reset\n", domain, offset); + return -EINVAL; + } + + return (domain << 8) | offset; +} + +static int eq5r_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *np = dev->of_node; + struct eq5r_private *priv; + int ret, i; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->base_d0 = devm_platform_ioremap_resource_byname(pdev, "d0"); + if (IS_ERR(priv->base_d0)) + return PTR_ERR(priv->base_d0); + + priv->base_d1 = devm_platform_ioremap_resource_byname(pdev, "d1"); + if (IS_ERR(priv->base_d1)) + return PTR_ERR(priv->base_d1); + + priv->base_d2 = devm_platform_ioremap_resource_byname(pdev, "d2"); + if (IS_ERR(priv->base_d2)) + return PTR_ERR(priv->base_d2); + + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + mutex_init(&priv->mutexes[i]); + + priv->rcdev.ops = &eq5r_ops; + priv->rcdev.owner = THIS_MODULE; + priv->rcdev.dev = dev; + priv->rcdev.of_node = np; + priv->rcdev.of_reset_n_cells = 2; + priv->rcdev.of_xlate = eq5r_of_xlate; + + priv->rcdev.nr_resets = 0; + for (i = 0; i < EQ5R_DOMAIN_COUNT; i++) + priv->rcdev.nr_resets += __builtin_popcount(eq5r_valid_masks[i]); + + ret = devm_reset_controller_register(dev, &priv->rcdev); + if (ret) { + dev_err(dev, "Failed registering reset controller: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id eq5r_match_table[] = { + { .compatible = "mobileye,eyeq5-reset" }, + {} +}; + +static struct platform_driver eq5r_driver = { + .probe = eq5r_probe, + .driver = { + .name = "eyeq5-reset", + .of_match_table = eq5r_match_table, + }, +}; + +builtin_platform_driver(eq5r_driver); From patchwork Wed Jan 31 16:26:23 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194855 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2009994dyb; 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It might grow to add later support of other platforms from Mobileye. It belongs to a syscon region called OLB. Existing pins and their function live statically in the driver code rather than in the devicetree, see compatible match data. Signed-off-by: Théo Lebrun --- MAINTAINERS | 1 + drivers/pinctrl/Kconfig | 15 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-eyeq5.c | 567 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 584 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 72edb390a046..c0bb5cb0c7cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14795,6 +14795,7 @@ F: arch/mips/boot/dts/mobileye/ F: arch/mips/configs/eyeq5_defconfig F: arch/mips/mobileye/board-epm5.its.S F: drivers/clk/clk-eyeq5.c +F: drivers/pinctrl/pinctrl-eyeq5.c F: drivers/reset/reset-eyeq5.c F: include/dt-bindings/clock/mobileye,eyeq5-clk.h F: include/dt-bindings/soc/mobileye,eyeq5.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 8163a5983166..abe94de85b3d 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -195,6 +195,21 @@ config PINCTRL_EQUILIBRIUM desired pin functions, configure GPIO attributes for LGM SoC pins. Pin muxing and pin config settings are retrieved from device tree. +config PINCTRL_EYEQ5 + bool "Mobileye EyeQ5 pinctrl driver" + depends on OF + depends on MACH_EYEQ5 || COMPILE_TEST + select PINMUX + select GENERIC_PINCONF + select MFD_SYSCON + default MACH_EYEQ5 + help + Pin controller driver for the Mobileye EyeQ5 platform. It does both + pin config & pin muxing. It does not handle GPIO. + + Pin muxing supports two functions for each pin: first is GPIO, second + is pin-dependent. Pin config is about bias & drive strength. + config PINCTRL_GEMINI bool depends on ARCH_GEMINI diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index 1071f301cc70..0033940914d9 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -22,6 +22,7 @@ obj-$(CONFIG_PINCTRL_DA850_PUPD) += pinctrl-da850-pupd.o obj-$(CONFIG_PINCTRL_DA9062) += pinctrl-da9062.o obj-$(CONFIG_PINCTRL_DIGICOLOR) += pinctrl-digicolor.o obj-$(CONFIG_PINCTRL_EQUILIBRIUM) += pinctrl-equilibrium.o +obj-$(CONFIG_PINCTRL_EYEQ5) += pinctrl-eyeq5.o obj-$(CONFIG_PINCTRL_GEMINI) += pinctrl-gemini.o obj-$(CONFIG_PINCTRL_INGENIC) += pinctrl-ingenic.o obj-$(CONFIG_PINCTRL_K210) += pinctrl-k210.o diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c new file mode 100644 index 000000000000..a5ade3a253b5 --- /dev/null +++ b/drivers/pinctrl/pinctrl-eyeq5.c @@ -0,0 +1,567 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Pinctrl driver for the Mobileye EyeQ5 platform. + * + * The registers are located in a syscon region called OLB. There are two pin + * banks, each being controlled by 5 registers (see enum eq5p_regs) for + * pull-down, pull-up, drive strength and muxing. + * + * For each pin, muxing is between two functions: (0) GPIO or (1) another one + * that is pin-dependent. Functions are declared statically in this driver. + * + * We create pinctrl groups that are 1:1 equivalent to pins: each group has a + * single pin, and its index/selector is the pin number/offset. + * + * We use eq5p_ as prefix, as-in "EyeQ5 Pinctrl", but way shorter. + * + * Copyright (C) 2024 Mobileye Vision Technologies Ltd. + */ +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "core.h" +#include "pinctrl-utils.h" + +struct eq5p_pinctrl { + struct pinctrl_desc desc; + void __iomem *base; +}; + +struct eq5p_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +enum eq5p_bank { + EQ5P_BANK_A, + EQ5P_BANK_B, + + EQ5P_BANK_COUNT, +}; + +enum eq5p_regs { + EQ5P_PD, + EQ5P_PU, + EQ5P_DS_LOW, + EQ5P_DS_HIGH, + EQ5P_IOCR, + + EQ5P_REG_COUNT, +}; + +static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = { + [EQ5P_BANK_A] = {0x010, 0x014, 0x020, 0x024, 0x000}, + [EQ5P_BANK_B] = {0x018, 0x01C, 0x028, 0x02C, 0x004}, +}; + +/* + * Comments to the right of each pin are the "signal name" in the datasheet. + */ +static const struct pinctrl_pin_desc eq5p_pins[] = { + /* Bank A */ + PINCTRL_PIN(0, "PA0"), /* A0_TIMER0_CK */ + PINCTRL_PIN(1, "PA1"), /* A1_TIMER0_EOC */ + PINCTRL_PIN(2, "PA2"), /* A2_TIMER1_CK */ + PINCTRL_PIN(3, "PA3"), /* A3_TIMER1_EOC */ + PINCTRL_PIN(4, "PA4"), /* A4_TIMER2_CK */ + PINCTRL_PIN(5, "PA5"), /* A5_TIMER2_EOC */ + PINCTRL_PIN(6, "PA6"), /* A6_TIMER5_EXT_INCAP1 */ + PINCTRL_PIN(7, "PA7"), /* A7_TIMER5_EXT_INCAP2 */ + PINCTRL_PIN(8, "PA8"), /* A8_TIMER5_EXT_OUTCMP1 */ + PINCTRL_PIN(9, "PA9"), /* A9_TIMER5_EXT_OUTCMP2 */ + PINCTRL_PIN(10, "PA10"), /* A10_UART_0_TX */ + PINCTRL_PIN(11, "PA11"), /* A11_UART_0_RX */ + PINCTRL_PIN(12, "PA12"), /* A12_UART_1_TX */ + PINCTRL_PIN(13, "PA13"), /* A13_UART_1_RX */ + PINCTRL_PIN(14, "PA14"), /* A14_CAN_0_TX */ + PINCTRL_PIN(15, "PA15"), /* A15_CAN_0_RX */ + PINCTRL_PIN(16, "PA16"), /* A16_CAN_1_TX */ + PINCTRL_PIN(17, "PA17"), /* A17_CAN_1_RX */ + PINCTRL_PIN(18, "PA18"), /* A18_SPI_0_DO */ + PINCTRL_PIN(19, "PA19"), /* A19_SPI_0_DI */ + PINCTRL_PIN(20, "PA20"), /* A20_SPI_0_CK */ + PINCTRL_PIN(21, "PA21"), /* A21_SPI_0_CS0 */ + PINCTRL_PIN(22, "PA22"), /* A22_SPI_0_CS1 */ + PINCTRL_PIN(23, "PA23"), /* A23_SPI_1_DO */ + PINCTRL_PIN(24, "PA24"), /* A24_SPI_1_DI */ + PINCTRL_PIN(25, "PA25"), /* A25_SPI_1_CK */ + PINCTRL_PIN(26, "PA26"), /* A26_SPI_1_CS0 */ + PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */ + PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */ + +#define EQ5P_PIN_OFFSET_BANK_B 29 + + /* Bank B */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0, "PB0"), /* B0_TIMER3_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1, "PB1"), /* B1_TIMER3_EOC */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2, "PB2"), /* B2_TIMER4_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3, "PB3"), /* B3_TIMER4_EOC */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4, "PB4"), /* B4_TIMER6_EXT_INCAP1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5, "PB5"), /* B5_TIMER6_EXT_INCAP2 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6, "PB6"), /* B6_TIMER6_EXT_OUTCMP1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7, "PB7"), /* B7_TIMER6_EXT_OUTCMP2 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8, "PB8"), /* B8_UART_2_TX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9, "PB9"), /* B9_UART_2_RX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */ + PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */ +}; + +static const char * const gpio_groups[] = { + /* Bank A */ + "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6", "PA7", "PA8", "PA9", + "PA10", "PA11", "PA12", "PA13", "PA14", "PA15", "PA16", "PA17", "PA18", + "PA19", "PA20", "PA21", "PA22", "PA23", "PA24", "PA25", "PA26", "PA27", + "PA28", + + /* Bank B */ + "PB0", "PB1", "PB2", "PB3", "PB4", "PB5", "PB6", "PB7", "PB8", "PB9", + "PB10", "PB11", "PB12", "PB13", "PB14", "PB15", "PB16", "PB17", "PB18", + "PB19", "PB20", "PB21", "PB22", +}; + +/* Groups of functions on bank A */ +static const char * const timer0_groups[] = { "PA0", "PA1" }; +static const char * const timer1_groups[] = { "PA2", "PA3" }; +static const char * const timer2_groups[] = { "PA4", "PA5" }; +static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" }; +static const char * const uart0_groups[] = { "PA10", "PA11" }; +static const char * const uart1_groups[] = { "PA12", "PA13" }; +static const char * const can0_groups[] = { "PA14", "PA15" }; +static const char * const can1_groups[] = { "PA16", "PA17" }; +static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" }; +static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" }; +static const char * const refclk0_groups[] = { "PA28" }; + +/* Groups of functions on bank B */ +static const char * const timer3_groups[] = { "PB0", "PB1" }; +static const char * const timer4_groups[] = { "PB2", "PB3" }; +static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" }; +static const char * const uart2_groups[] = { "PB8", "PB9" }; +static const char * const can2_groups[] = { "PB10", "PB11" }; +static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" }; +static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" }; +static const char * const mclk0_groups[] = { "PB22" }; + +#define FUNCTION(a, b) { .name = a, .groups = b, .ngroups = ARRAY_SIZE(b) } + +static const struct eq5p_function eq5p_functions[] = { + /* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */ + FUNCTION("gpio", gpio_groups), +#define GPIO_FUNC_SELECTOR 0 + + /* Bank A functions */ + FUNCTION("timer0", timer0_groups), + FUNCTION("timer1", timer1_groups), + FUNCTION("timer2", timer2_groups), + FUNCTION("timer5", timer5_groups), + FUNCTION("uart0", uart0_groups), + FUNCTION("uart1", uart1_groups), + FUNCTION("can0", can0_groups), + FUNCTION("can1", can1_groups), + FUNCTION("spi0", spi0_groups), + FUNCTION("spi1", spi1_groups), + FUNCTION("refclk0", refclk0_groups), + + /* Bank B functions */ + FUNCTION("timer3", timer3_groups), + FUNCTION("timer4", timer4_groups), + FUNCTION("timer6", timer6_groups), + FUNCTION("uart2", uart2_groups), + FUNCTION("can2", can2_groups), + FUNCTION("spi2", spi2_groups), + FUNCTION("spi3", spi3_groups), + FUNCTION("mclk0", mclk0_groups), +}; + +static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl, + enum eq5p_bank bank, enum eq5p_regs reg, + u32 mask, u32 val) +{ + void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg]; + + writel((readl(ptr) & ~mask) | (val & mask), ptr); +} + +static bool eq5p_readl_bit(const struct eq5p_pinctrl *pctrl, + enum eq5p_bank bank, enum eq5p_regs reg, int bit) +{ + u32 val = readl(pctrl->base + eq5p_regs[bank][reg]); + + return (val & BIT(bit)) != 0; +} + +static enum eq5p_bank eq5p_pin_offset_to_bank(const struct eq5p_pinctrl *pctrl, + unsigned int offset) +{ + if (offset < EQ5P_PIN_OFFSET_BANK_B) + return EQ5P_BANK_A; + else + return EQ5P_BANK_B; +} + +static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(eq5p_pins); +} + +static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return pctldev->desc->pins[selector].name; +} + +static int eq5p_pinctrl_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int selector, + const unsigned int **pins, + unsigned int *num_pins) +{ + *pins = &pctldev->desc->pins[selector].number; + *num_pins = 1; + return 0; +} + +static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offset, + unsigned long *config); + +static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev, + struct seq_file *s, + unsigned int offset) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum eq5p_bank bank = eq5p_pin_offset_to_bank(pctrl, offset); + const char *pin_name = pctrl->desc.pins[offset].name; + const char *func_name, *bias; + unsigned long ds_config; + u32 drive_strength; + bool pd, pu; + int i, j; + + /* + * First, let's get the function name. All pins have only two functions: + * GPIO (IOCR == 0) and something else (IOCR == 1). + */ + if (!eq5p_readl_bit(pctrl, bank, EQ5P_IOCR, offset)) { + func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name; + } else { + func_name = NULL; + for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) { + if (i == GPIO_FUNC_SELECTOR) + continue; + + for (j = 0; j < eq5p_functions[i].ngroups; j++) { + /* Groups and pins are the same thing for us. */ + const char *x = eq5p_functions[i].groups[j]; + + if (strcmp(x, pin_name) == 0) { + func_name = eq5p_functions[i].name; + break; + } + } + + if (func_name) + break; + } + + /* + * We have not found the function attached to this pin, this + * should never occur as all pins have exactly two functions. + */ + if (!func_name) + func_name = "unknown"; + } + + /* Second, we retrieve the bias. */ + pd = eq5p_readl_bit(pctrl, bank, EQ5P_PD, offset); + pu = eq5p_readl_bit(pctrl, bank, EQ5P_PU, offset); + if (pd && pu) + bias = "both"; + else if (pd && !pu) + bias = "pulldown"; + else if (!pd && pu) + bias = "pullup"; + else + bias = "none"; + + /* Third, we get the drive strength. */ + ds_config = pinconf_to_config_packed(PIN_CONFIG_DRIVE_STRENGTH, 0); + eq5p_pinconf_get(pctldev, offset, &ds_config); + drive_strength = pinconf_to_config_argument(ds_config); + + seq_printf(s, "function=%s bias=%s drive_strength=%d", + func_name, bias, drive_strength); +} + +static const struct pinctrl_ops eq5p_pinctrl_ops = { + .get_groups_count = eq5p_pinctrl_get_groups_count, + .get_group_name = eq5p_pinctrl_get_group_name, + .get_group_pins = eq5p_pinctrl_get_group_pins, + .pin_dbg_show = eq5p_pinctrl_pin_dbg_show, + .dt_node_to_map = pinconf_generic_dt_node_to_map_pin, + .dt_free_map = pinctrl_utils_free_map, +}; + +static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev) +{ + return ARRAY_SIZE(eq5p_functions); +} + +static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev, + unsigned int selector) +{ + return eq5p_functions[selector].name; +} + +static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev, + unsigned int selector, + const char * const **groups, + unsigned int *num_groups) +{ + *groups = eq5p_functions[selector].groups; + *num_groups = eq5p_functions[selector].ngroups; + return 0; +} + +static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev, + unsigned int func_selector, unsigned int offset) +{ + const char *group_name = pctldev->desc->pins[offset].name; + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum eq5p_bank bank = eq5p_pin_offset_to_bank(pctrl, offset); + const char *func_name = eq5p_functions[func_selector].name; + bool is_gpio = func_selector == GPIO_FUNC_SELECTOR; + u32 mask, val; + + dev_dbg(pctldev->dev, "%s: func=%s group=%s\n", __func__, func_name, + group_name); + + mask = BIT(offset); + val = is_gpio ? 0 : U32_MAX; + eq5p_update_bits(pctrl, bank, EQ5P_IOCR, mask, val); + return 0; +} + +static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev, + struct pinctrl_gpio_range *range, + unsigned int offset) +{ + /* Pin offsets and group selectors are the same thing in our case. */ + return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, offset); +} + +static const struct pinmux_ops eq5p_pinmux_ops = { + .get_functions_count = eq5p_pinmux_get_functions_count, + .get_function_name = eq5p_pinmux_get_function_name, + .get_function_groups = eq5p_pinmux_get_function_groups, + .set_mux = eq5p_pinmux_set_mux, + .gpio_request_enable = eq5p_pinmux_gpio_request_enable, + .strict = true, +}; + +static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int offset, + unsigned long *config) +{ + enum pin_config_param param = pinconf_to_config_param(*config); + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum eq5p_bank bank = eq5p_pin_offset_to_bank(pctrl, offset); + u32 val_ds, arg = 0; + bool pd, pu; + + pd = eq5p_readl_bit(pctrl, bank, EQ5P_PD, offset); + pu = eq5p_readl_bit(pctrl, bank, EQ5P_PU, offset); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + arg = !(pd || pu); + break; + case PIN_CONFIG_BIAS_PULL_DOWN: + arg = pd; + break; + case PIN_CONFIG_BIAS_PULL_UP: + arg = pu; + break; + case PIN_CONFIG_DRIVE_STRENGTH: + offset *= 2; /* two bits per pin */ + if (offset >= 32) { + val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]); + offset -= 32; + } else { + val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]); + } + arg = (val_ds >> offset) & 0b11; + break; + default: + return -ENOTSUPP; + } + + *config = pinconf_to_config_packed(param, arg); + return 0; +} + +static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev, + unsigned int offset, u32 arg) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum eq5p_bank bank = eq5p_pin_offset_to_bank(pctrl, offset); + unsigned int reg; + u32 mask, val; + + if (arg > 3) { + dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg); + return -EINVAL; + } + + offset *= 2; /* two bits per pin */ + + if (offset >= 32) { + reg = EQ5P_DS_HIGH; + offset -= 32; + } else { + reg = EQ5P_DS_LOW; + } + + mask = 0b11 << offset; + val = arg << offset; + eq5p_update_bits(pctrl, bank, reg, mask, val); + return 0; +} + +static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int offset, + unsigned long *configs, unsigned int num_configs) +{ + struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev); + enum eq5p_bank bank = eq5p_pin_offset_to_bank(pctrl, offset); + const char *pin_name = pctldev->desc->pins[offset].name; + struct device *dev = pctldev->dev; + u32 val = BIT(offset); + unsigned int i; + + for (i = 0; i < num_configs; i++) { + enum pin_config_param param = pinconf_to_config_param(configs[i]); + u32 arg = pinconf_to_config_argument(configs[i]); + + switch (param) { + case PIN_CONFIG_BIAS_DISABLE: + dev_dbg(dev, "pin=%s bias_disable\n", pin_name); + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); + break; + + case PIN_CONFIG_BIAS_PULL_DOWN: + dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n", + pin_name, arg); + + if (arg == 0) /* cannot connect to GND */ + return -ENOTSUPP; + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0); + break; + + case PIN_CONFIG_BIAS_PULL_UP: + dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n", + pin_name, arg); + + if (arg == 0) /* cannot connect to VDD */ + return -ENOTSUPP; + + eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0); + eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val); + break; + + case PIN_CONFIG_DRIVE_STRENGTH: + dev_dbg(dev, "pin=%s drive_strength arg=%u\n", + pin_name, arg); + + eq5p_pinconf_set_drive_strength(pctldev, offset, arg); + break; + + default: + dev_err(dev, "Unsupported pinconf %u\n", param); + return -ENOTSUPP; + } + } + + return 0; +} + +static const struct pinconf_ops eq5p_pinconf_ops = { + .is_generic = true, + .pin_config_get = eq5p_pinconf_get, + .pin_config_set = eq5p_pinconf_set, + /* Pins and groups are equivalent in this driver. */ + .pin_config_group_get = eq5p_pinconf_get, + .pin_config_group_set = eq5p_pinconf_set, +}; + +static int eq5p_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct pinctrl_dev *pctldev; + struct eq5p_pinctrl *pctrl; + int ret; + + pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pctrl->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(pctrl->base)) + return PTR_ERR(pctrl->base); + + pctrl->desc.name = dev_name(dev); + pctrl->desc.pins = eq5p_pins; + pctrl->desc.npins = ARRAY_SIZE(eq5p_pins); + pctrl->desc.pctlops = &eq5p_pinctrl_ops; + pctrl->desc.pmxops = &eq5p_pinmux_ops; + pctrl->desc.confops = &eq5p_pinconf_ops; + pctrl->desc.owner = THIS_MODULE; + + ret = devm_pinctrl_register_and_init(dev, &pctrl->desc, pctrl, &pctldev); + if (ret) { + dev_err(dev, "Failed registering pinctrl device: %d\n", ret); + return ret; + } + + ret = pinctrl_enable(pctldev); + if (ret) { + dev_err(dev, "Failed enabling pinctrl device: %d\n", ret); + return ret; + } + + return 0; +} + +static const struct of_device_id eq5p_match[] = { + { .compatible = "mobileye,eyeq5-pinctrl" }, + {}, +}; + +static struct platform_driver eq5p_driver = { + .driver = { + .name = "eyeq5-pinctrl", + .of_match_table = eq5p_match, + }, + .probe = eq5p_probe, +}; + +builtin_platform_driver(eq5p_driver); From patchwork Wed Jan 31 16:26:24 2024 Content-Type: text/plain; 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OLB, meaning "Other Logic Block", is a name specific to this platform. Change the node name to the generic and often-used "system-controller". See §2.2.2. "Generic Names Recommendation" in the devicetree specification. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index fd34c49af510..81497febcdee 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -100,7 +100,7 @@ uart2: serial@a00000 { clock-names = "uartclk", "apb_pclk"; }; - olb: olb@e00000 { + olb: system-controller@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; reg-io-width = <4>; From patchwork Wed Jan 31 16:26:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194848 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2007833dyb; Wed, 31 Jan 2024 08:31:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IFIo+1uIGZmPhJu+NuVCj/to1klQ97PfImJCeknoNvVuJdmqwAyCIm/W1fF27oD4g21yLey X-Received: by 2002:a17:903:1112:b0:1d7:91:4f9e with SMTP id n18-20020a170903111200b001d700914f9emr1478650plh.96.1706718689701; Wed, 31 Jan 2024 08:31:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718689; cv=pass; d=google.com; s=arc-20160816; b=qY+QSVz1Epnif+y5GDkpCHUvfdPYvHfT78/m7HOWNmklRdU25wia6CAVm2jqfNCk6F 2ILx9XL6KRrHt/7nKiWshfTyBLChPkx3ynYI6uZ+HvrMJiHl0KTGuojZKYy8cS9r2vmP ltAM8r4pMoaZIlEpyDj+yi8aIEUtbJbLGIO1LgwTMCFpxtu3qkE3sGpM2ob2vgkdtNb/ geQP47VLPDgIpwYhwF3FH6GUjz1h7zdRHeXIAnl23TeckMjX9OOZ8zxO3D4lvD4BvMXP an+CwnvyJwk6DBT59/m96UXiOAGVSABkpT2x958w12hLuBqaBgrus2qOp8D6fm/Vc/rN BXzA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=uvFAvzfq7+hFGweJFxbN+uqUZSVxDpI6pzlv2xpGDIc=; fh=Wd0UIQ2dnyGHNjMHohKoKErBdrEFho8YKM/SSw08wgg=; b=YfATMubooQ4bDeKtcjY70lS+7J4qSvMtzub9pjOu9LLQAPkyqwBEN7bk988OHU2XXK eurL1I4HSXwaLlDkCCl91OSnvgOE15V6zPmd2CvtKWrUveUhJBrngvR4urJoX+W/oNhN 7NZqzMB8p4WPEZmqVRc2X1yBDReT50xHgVPLWpgF9gJIqG3YC/f7Yq8gV0Brcq/IOWce 9CfmwfDVRJ/ltw80Jkm+Lw1/KWK6Bqj795groX/3txvJxrtn5pzygl72j51VcQk+37Bw 9fg60JkQaUXPuco9rPatReht5N7aC6Lwp60iH43WjG3k014iODinH2px81o7BiYnqSvZ luuw==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Q3c22cB0; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46798-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46798-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCU89eh5bPs8UgERvxV6rxu89O7fcfKbNnfecbd9RcKuXSVanbXQk58qCNxa5cZ/3XzmGb6lZ8Qbx+Z+x+MNh7cTci0LtA== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718440; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uvFAvzfq7+hFGweJFxbN+uqUZSVxDpI6pzlv2xpGDIc=; b=Q3c22cB00X22uU0+unIxoZ+GCChLde2WYBhFhq49tKHhG5Sr3j/22PVstaFnvqgWehQbbi scYh4QMKo5sT5dVw4ugJYgBBBgT23bytEV0WqaPpZf4C5qF5x8nM+FkIaeZu0+rHiXdGsC TBVqhjj9MPsOSagfRh8Nl1Z2UBRqdMUuwD64Ol4oB50pIo3V5Y33vkMguMXlQQQvh7LuHP iBSrQ+vMyGisJhHzYvnRfoj5eodYsmCMRLK0LrjYR2KEd2pwX8kwvrfsGSGRQsau4rr0NK abFfKtSmPrWSL0gQo2G/Y9nVtmmULsYcquLdWCvQ1DRuPwtd5kVZelnFR2Pfnw== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:25 +0100 Subject: [PATCH v4 12/18] MIPS: mobileye: eyeq5: remove reg-io-width property from OLB syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-12-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624256635347695 X-GMAIL-MSGID: 1789624256635347695 Remove the `reg-io-width` property from the system-controller@e00000 syscon. The default memory access width is what we desire: no need to make it explicit. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 81497febcdee..03e7e942ee22 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -103,7 +103,6 @@ uart2: serial@a00000 { olb: system-controller@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; - reg-io-width = <4>; }; gic: interrupt-controller@140000 { From patchwork Wed Jan 31 16:26:26 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194850 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2008111dyb; Wed, 31 Jan 2024 08:31:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IH9vS6Yt4rTm8zzbzAC3jCmmVK5pq/0XeLJETpI8qaJlzIh/FNUM1Kg/Wm24LgsoC3IVxUW X-Received: by 2002:aa7:8553:0:b0:6dd:c1f2:8ae4 with SMTP id y19-20020aa78553000000b006ddc1f28ae4mr1997084pfn.14.1706718712447; Wed, 31 Jan 2024 08:31:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718712; cv=pass; d=google.com; s=arc-20160816; b=RbvtKkbBJCg/R50n2EUjCyUKu6uMkayn5I/3OsW1kztyE4Qc3VCoEBEqRbbW8JE2xd KE+wCqXWk7vF0UEM1HrcBFWi/JYsRsDZfpx4ofCmbrn+Y113/aP348NJy/aOqo05v04E I1rmhd0fSIPneD8/qGlRORkHmSHq7iXIqnUrpipUnZBTSHBc7WWNvhJpR618JG1BYilH 95RFe26h5dPKTcSIohF9A/rrE4hLH9rwt7pqQueuuvdruFXtHxFgT5j507NitrrrgGhg CZ3ia7GODhnp+7AiMr6zkOUlBWfH/TN7KcrreAH3GDhd0Mme2LaUWE1oqxhtlsfhfcIb pLEw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=fORjDlsDhrIYNSllDnl+lAljmgE3xSz15qek+qYmWrk=; fh=m0AACwtgDkpcDaxauPTlGe7PGbD+mJqbNBmf95r4Vyk=; b=W8x5TRXL0P0vg7HOLPjym3pHsdGLlo3gHo12tMz0Veut16UAzYdTY4gStmFcjKei41 AWe6/bvbVc/c6xWm9RoOCyPrfH2htRwZWLliq06Mhd0GekBdD2/5BmiflF3/khIpEE/O Z4eNPsPUGn5jbDESRnALYTrmVe8DAb5IVx91EeAAySguv8D6Fl3fhyeHdcB48hz+tbvh HlF2Q+68zwWJHX0WZehfVJxuEyQ95Mm84otThTRIpOnq1vYXkMxnWPJA3OAEwmk7jeDU BbE0FZ5+o7BzGl4pDspvceW49Sy0S/7hfGDwahVhou+f7UrCkNn6waogc/YI6OEHASmo bnoA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=eidMrhta; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46799-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46799-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWMyxreQkQ1ymKYZ1gkbFZ4Uj76FATK5fVeGvIv//IPi5lMxW43Z9FZrfMa+euQLPKHRKFs3ngwaqscYjNb1R8k3A93nQ== Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718440; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=fORjDlsDhrIYNSllDnl+lAljmgE3xSz15qek+qYmWrk=; b=eidMrhtaP0pvp7ETrGL/Tbun1n7+k2Qi3uKYyTp9hXDNMSDQCS21cCug4228h26Rk4kNRS 5fB20NqUhwpG4r1YC1Mq2s0cPgj3pTSUQ3eeHQ29SC15KsXMFe6AbdDHf6zsMgfMiesUt8 Ds1FLsp0EbTGs7TY3Fr835D6tdJ9MCRkNAXkTjSeO29bsRpsBRoR1fxIbw2Z7lymwzL4Bt lJI7z4aBPXPccSYYXeeYdXq1iNkG5SOZE4sfJIuCaOMgIpYChcA9XQHuGZkYMK3gsh5b0z s6RKqhksoD5ISG6R+jH/6RcKk5INjyjPnCRGFAcuid4fT/ngxvT8sO4iwNM0Og== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:26 +0100 Subject: [PATCH v4 13/18] MIPS: mobileye: eyeq5: add memory translation inside OLB syscon Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-13-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624280601144403 X-GMAIL-MSGID: 1789624280601144403 The OLB syscon block is host to a few peripherals (clock, reset, pinctrl). Simplify declarations by mapping memory to have relative addresses. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 03e7e942ee22..732e21be65b4 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -103,6 +103,9 @@ uart2: serial@a00000 { olb: system-controller@e00000 { compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd"; reg = <0 0xe00000 0x0 0x400>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0xe00000 0x400>; }; gic: interrupt-controller@140000 { From patchwork Wed Jan 31 16:26:27 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194851 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2008258dyb; Wed, 31 Jan 2024 08:32:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IEhYUSYinC2Q0sVA/xZrv0rqTkv1Ekps/HoVQmi759j4cvmz7ZvOHyi+yAvn/SBOQSAThvF X-Received: by 2002:ac8:5a0f:0:b0:42b:ee14:1525 with SMTP id n15-20020ac85a0f000000b0042bee141525mr775683qta.110.1706718723683; Wed, 31 Jan 2024 08:32:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718723; cv=pass; d=google.com; s=arc-20160816; b=I2jpvgG+YmJ1xRdFRdQC9BD55JOqLYhV9SoRjtH272ZhLb12/4V6HcVsRs6Fx5YZvB p2a3I59wdWziulx5+CIb6sIwLYvjh815xpg5i3/pgDXTOQrjEAa873pi7Ny3xqPlWPyY ECBm/jGMw2JFGIuFHXEFxe7ME9uDkQJi7IU/HejURqhMvj2Zf/JBUTkmlZKQCEJUKmSG BWKqknAxJrxEZlKiyJZC4ldvROIV7rkKXsY762FUCKLR5Lk8QEVKBImy4MFIe0LXzX/p HwHvzblJFNPL/L/5cPsHZ0i7lud7K8HHzlm5+aGa8p66aiuZifmUTX592WDxtSOs762T 4ozQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=qtI2Bmw/Qd3wn7V+IjY8a46w4YqNdEQ9NakuEGrL+ss=; fh=aIXeB1laBJudViPXmepxtrgbEkdBeQzbvwqvN1gcorE=; b=FlDcFvYbsZImo9AzxiRtFXnrrVWtEGC2puIHjPDJEVodCljqZntuiT8bFvnxmgljtN P+fZCeTZQgmYvKHUKUvM3BcJWWF0zpP2HMp6GmIyhX5H+hqvpPyaNO/Fqg3Ih1ss5Vt4 c08RB4okc5mF8NX+Vzy3Ep9GBZWlfJLUc4VBwdP6kItSGTxWqdZ1A2rOyAoJ58CZ4s4n XbbchIv/a9UpBJzPwzIL9xOcNrK3YCzum6D2qTKl4eUtTwgJfCMhXU2NFJVYKc+BMlNG EyZrn/EE2x3exDhbfTR8YOgz0z6VKjOU2ek5tmo9qrIDk6d5hZ9D+RLi2caovDFfFNDW DMWg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=otpDdrei; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46800-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46800-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCWN3UkKr1PF/l8vHrNgim6LT2BFwPBwtMDenxMYgBKjHCCF1cwhZzdTCTxhRLvWsMIwGKHMeYsVlqUcew/mCd5GP/KIhQ== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718441; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qtI2Bmw/Qd3wn7V+IjY8a46w4YqNdEQ9NakuEGrL+ss=; b=otpDdreijvL3Fd9lveSsEBh1aJ2/UNXAwd05NKaDK4vI5dfl2DPO08wF/q+M8M/x/IS9zh Gk1dD2OqWvBlxlEsbmMxFa/vK7G6BCyaAn5Y5luCxPHbILWbvqDZuQl9siJI8IqEspPIUB 3KvlqyZZedn3gscwmneRQPVcYVy9haTDlG4CpKgg/u+XIz4IkUbzfLN5uK95xMwlhpdfhl UDzFEHr3y+u9gLUO/IzKoCo5gXDtTEW4P4a7zi7gfIkkG2LTHGzdlIlKXGRO/uFxhI7zwW mD+hQEy9zKBAgV1aIGVxwXXwrypCgJbK6w/g9Jjc93Mp8LR/HFT4r2CGgqyWUg== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:27 +0100 Subject: [PATCH v4 14/18] MIPS: mobileye: eyeq5: use OLB clocks controller Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-14-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624292510217827 X-GMAIL-MSGID: 1789624292510217827 We add the clock controller inside the OLB syscon region and removed previous fixed devicetree nodes representing PLLs exposed by the clock controller. Signed-off-by: Théo Lebrun --- .../{eyeq5-fixed-clocks.dtsi => eyeq5-clocks.dtsi} | 54 +++++++--------------- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 11 ++++- 2 files changed, 26 insertions(+), 39 deletions(-) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi similarity index 88% rename from arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi rename to arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi index 78f5533a95c6..aa6db704a786 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5-fixed-clocks.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi @@ -3,42 +3,20 @@ * Copyright 2023 Mobileye Vision Technologies Ltd. */ +#include + / { /* Fixed clock */ - pll_cpu: pll-cpu { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1500000000>; - }; - - pll_vdi: pll-vdi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1280000000>; - }; - - pll_per: pll-per { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <2000000000>; - }; - - pll_ddr0: pll-ddr0 { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <1857210000>; - }; - - pll_ddr1: pll-ddr1 { + xtal: xtal { compatible = "fixed-clock"; #clock-cells = <0>; - clock-frequency = <1857210000>; + clock-frequency = <30000000>; }; /* PLL_CPU derivatives */ occ_cpu: occ-cpu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <1>; clock-mult = <1>; @@ -101,7 +79,7 @@ mem_clk: mem-clk { }; occ_isram: occ-isram { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -115,7 +93,7 @@ isram_clk: isram-clk { /* gate ClkRstGen_isram */ }; occ_dbu: occ-dbu { compatible = "fixed-factor-clock"; - clocks = <&pll_cpu>; + clocks = <&clocks EQ5C_PLL_CPU>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -130,7 +108,7 @@ si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */ /* PLL_VDI derivatives */ occ_vdi: occ-vdi { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -144,7 +122,7 @@ vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */ }; occ_can_ser: occ-can-ser { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -158,7 +136,7 @@ can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */ }; i2c_ser_clk: i2c-ser-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_vdi>; + clocks = <&clocks EQ5C_PLL_VDI>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -166,7 +144,7 @@ i2c_ser_clk: i2c-ser-clk { /* PLL_PER derivatives */ occ_periph: occ-periph { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <16>; clock-mult = <1>; @@ -225,7 +203,7 @@ gpio_clk: gpio-clk { }; emmc_sys_clk: emmc-sys-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <10>; clock-mult = <1>; @@ -233,7 +211,7 @@ emmc_sys_clk: emmc-sys-clk { }; ccf_ctrl_clk: ccf-ctrl-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <4>; clock-mult = <1>; @@ -241,7 +219,7 @@ ccf_ctrl_clk: ccf-ctrl-clk { }; occ_mjpeg_core: occ-mjpeg-core { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <2>; clock-mult = <1>; @@ -265,7 +243,7 @@ mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */ }; fcmu_a_clk: fcmu-a-clk { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <20>; clock-mult = <1>; @@ -273,7 +251,7 @@ fcmu_a_clk: fcmu-a-clk { }; occ_pci_sys: occ-pci-sys { compatible = "fixed-factor-clock"; - clocks = <&pll_per>; + clocks = <&clocks EQ5C_PLL_PER>; #clock-cells = <0>; clock-div = <8>; clock-mult = <1>; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 732e21be65b4..69f89793fed7 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -5,7 +5,7 @@ #include -#include "eyeq5-fixed-clocks.dtsi" +#include "eyeq5-clocks.dtsi" / { #address-cells = <2>; @@ -106,6 +106,15 @@ olb: system-controller@e00000 { #address-cells = <1>; #size-cells = <1>; ranges = <0 0 0xe00000 0x400>; + + clocks: clock-controller@e0002c { + compatible = "mobileye,eyeq5-clk"; + reg = <0x02c 0x50>, <0x11c 0x04>; + reg-names = "plls", "ospi"; + #clock-cells = <1>; + clocks = <&xtal>; + clock-names = "ref"; + }; }; gic: interrupt-controller@140000 { From patchwork Wed Jan 31 16:26:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194853 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2008416dyb; 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718442; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=0ldyJrn/6hMrKL66J7c4uEBP6rhcVzqhrRn+hm5cRxo=; b=j40VU6kDHEncJGPWRFDSRmW7RIiUn0th58GxZZ14+rQVV3xrvlhQPgkjqPwIv51V8iYh0m muo1WWcMx60qdnBH2FFgQc50sMfbWTxjWGzcorvrWHcGZ0T5qK+9qp8WQ64dNWFmmiwyxt trdpmjViM2u4TL4JGaggEF+d9DJkig/JYGUu/djfo3AgPKyJbOBh8VZEQzeQQTH6QyigKH HJICZUzKeZaegJhiAFWwPa0Zd0GfOInGVaB3JQv5NHo/I4re/a4uOH9E/y45DrDusClq41 3iOEep0Jn3+KkYPXMRwhAOHU80NAtdvjhJ6E2+aUerazwyAMc85rp1vimSDcew== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:28 +0100 Subject: [PATCH v4 15/18] MIPS: mobileye: eyeq5: add OLB reset controller node Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-15-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624308870034951 X-GMAIL-MSGID: 1789624308870034951 Add the devicetree node for the reset controller on the Mobileye EyeQ5 platform. It appears as a subnode to the OLB syscon as its registers are located in this shared register region. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 69f89793fed7..06e941b0ce10 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -115,6 +115,13 @@ clocks: clock-controller@e0002c { clocks = <&xtal>; clock-names = "ref"; }; + + reset: reset-controller@e00000 { + compatible = "mobileye,eyeq5-reset"; + reg = <0x000 0x0c>, <0x200 0x34>, <0x120 0x04>; + reg-names = "d0", "d1", "d2"; + #reset-cells = <2>; + }; }; gic: interrupt-controller@140000 { From patchwork Wed Jan 31 16:26:29 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194852 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2008322dyb; Wed, 31 Jan 2024 08:32:09 -0800 (PST) X-Google-Smtp-Source: AGHT+IHP6OLMYYb3CwRwSi5l8AxZaEZfSvrpll2nIayBxAZehIGTVr98rRtXbua2kDzewam443zo X-Received: by 2002:a05:622a:1007:b0:42a:a930:ab4d with SMTP id d7-20020a05622a100700b0042aa930ab4dmr2443519qte.35.1706718728812; Wed, 31 Jan 2024 08:32:08 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718728; cv=pass; d=google.com; s=arc-20160816; b=PR/tK6q8YH2TlXi3iQi96wsygUMc0sV3t+IviUp6+5YMuCQIpzGj0MU69APVcFycYr B+YgX1j/Tsjxqp985blyV3KnS22NPtE+FXTwQNVvotwlI94AxqcnJruYR31HUrsRmWdd upyLt/etTQJFr5gQHqcXhOYMQzMVUHPAi39kc8amxj+Zo7+S8aiWQ2QJLg+BHSDXDE7P G0cItQ0fKi48rOuLPdxPGH4b2aLTLZPVsVUaXWoxJ2QdUGaEI5rAID1z1m0XovhTuZZr PecNITwa1RlWtr+L07VuuuwJlAgi5z7P3gR0Uqu16cW6udUWgJpQjapfPdUFHWAX6fqH aOeA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=JJeokSopmVKcL3uXVtWha5+P5NH0m5rgY0PH8CJYzgU=; fh=W7chTc71HS21hiGNMegBkwUoj0v7V5dS8lNoq2sevDA=; b=nN2I81hS+tOgH+I10CufkJr8RLzYUAHJi+IVTVr58ghM3+ATI8vc7gACZSaH1A1D8V tzekxIRS9PyMAUoHHDxcSicya8RAR1UG29wBJjTucSmhaS0g5GuEljBe+3GiFv/2NObp OJkMT/7Z3oj5k2VqMZetH6z9uQkFiZtGHZQBxlS9y+jePXhLwXZeQtRk8a5fTQSb4G5G 3a59zMusmUBeEMe8NrLn8iwkdmhbKy7HpF7o+znI/vgPbV4pphIFNwiPGQorZtsUAXzM 5X0sUBHFyGDcAJo8zaHLBSHBQBbFD6hI7o3dDX8+FvBxZK0tRipKWK7Mqwet1F0mfxh2 255A==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=Es78e1Ie; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46802-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46802-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCXceReLGeddKK21I9A16GMybe9/GUYDSB0GVQ8cnNpKgiYfS2JHSekN5tRclPtEn8SEFQWiEhormRs2F04FLAvZ1J2w1g== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718443; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=JJeokSopmVKcL3uXVtWha5+P5NH0m5rgY0PH8CJYzgU=; b=Es78e1IesRvttlYt6VTqSYHuXGdy6TdFkNT3WJvGaOrJvm9Q8VM9leRnIXHHRovC1rNo3V 0y6Ua0Tbl6gywXHUYmw/jgeY9WqhI0JnKvuYm5ItsMuQgOJBGx2A7uIn7566z4lXiG+PwK JIht0t8kcUOrWWdcTXsXkmnFCwfKa/+KBQ9sxO5S1RM7wAnFCzCYhEBkWbCqOimECKWLlg BivgPg7TbzZVI/XZFFNiSmdKIMKvq5eHTUt4AXe4Y0n38bwMMrcQ0VI8U9gdPzFnyvBhwZ B+phJc1ZiAl/IjXy9dey/O5fUYOLNTY1VKcKgQx+XMWI8j6j9ZsQ8R1x98RPuA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:29 +0100 Subject: [PATCH v4 16/18] MIPS: mobileye: eyeq5: add reset properties to UARTs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-16-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624297778373695 X-GMAIL-MSGID: 1789624297778373695 UART nodes have been added to the devicetree by the initial platform support patch series. Add reset properties now that the reset node is declared. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index 06e941b0ce10..ece71cafb6ee 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -78,6 +78,7 @@ uart0: serial@800000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 10>; }; uart1: serial@900000 { @@ -88,6 +89,7 @@ uart1: serial@900000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 11>; }; uart2: serial@a00000 { @@ -98,6 +100,7 @@ uart2: serial@a00000 { interrupts = ; clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; + resets = <&reset 0 12>; }; olb: system-controller@e00000 { From patchwork Wed Jan 31 16:26:30 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Th=C3=A9o_Lebrun?= X-Patchwork-Id: 194854 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp2008455dyb; Wed, 31 Jan 2024 08:32:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IFjbB6Ee4ng7ZJj/uxJ2lsJkcAy0JP2q5MKdf19JObfRc0gnL4iw/zmgu3uNFOph8saJqbB X-Received: by 2002:a05:6214:2aa6:b0:68c:6e9a:d925 with SMTP id js6-20020a0562142aa600b0068c6e9ad925mr1930310qvb.3.1706718743068; Wed, 31 Jan 2024 08:32:23 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706718743; cv=pass; d=google.com; s=arc-20160816; b=ArBkiF3VsffbKL5WTfiMvDovN1uEXvln4gh4iNeWK2nsSWt3nhpaJS11CFTjg40Sjd fP0A9da1PqR/O3A0FuZiRZlECKqBl7Vahtny31B2piMXM1iyt720Jh38e+RAXYL7wAy1 W71RI7ADGPUeer0SThfY9CTIXo+eTFIE4Ubh7WEM33p4W6yJRs2oscGyswd/s4XkhRlQ zrVDO+odrU73ZZSm9AewRnIW1Xrj4GyNYMFX61s/ZOlAXjYZRsE+Yl9AtODDL8rSftKd 7kwl+Jlo9IJl+o7TdHrf5V33nzPqRSRgdPghlk38h3QNc/ZeYZjJGVzuIFTNf5yTTvM8 Nl5Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=VNC27OFOihTp3bOx750xw7viXyvhaOjsFxRElEISsgo=; fh=faEtENBRj+7gGbRWy0J8nGra9XLrB8s8e8PL+5bOE/M=; b=ZEIROXuM9fNZRxWFja63ZW/OKD1MnXQMkZ8d2ynUkqhNGinGfS8M/xOtbQSZqFhkPb LDuDA/ItaSVq+ZZSk7qXd3eNKDlWMje/bkrATZC3wDbetf0G1y24lGSMj2MazsoW/UFd ebk5DdyIJoxQZEoFb/WNizMeaOBVKhwe7V+gK4NpLEeIRkHV8sQfmCspEdExm2kQ9u/B qGWhk+KqsXUNjwXq2dOClUI81vyZDCWnTPVc+iBI1v5uwuYvM98F9u9Kc7UXvTeo2tPf vWdLcvfwbCxIT5taTVLWtL08K+UFVcoFduucqLXYwsAQMi1N7kNGhjru8BY1h7BoE8fO jKVA==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="KiZoFa/w"; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46803-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46803-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com X-Forwarded-Encrypted: i=1; AJvYcCXfUDa9lrXoSQ3f8JdIZCA9ajQONU6gJiUTOpPL2Z80rqe0qqthnGRrLvdVGAIDTgXjsYbIlhQCHtqDW2QmQ9vxg2e0cg== Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718444; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=VNC27OFOihTp3bOx750xw7viXyvhaOjsFxRElEISsgo=; b=KiZoFa/w/D04u82HpGkBb8RZEodV4mEX2Bt/5L2iETcdN0b2eD0W0ZYV9w/+CpLJMt5J7V Gxsnz9cHRFtCXbpip4I+jGyX9W49D4XVycDezDxQZfJj/m5KWkq2j5G9oUT0LCo/hgDJyM 0aldxCBB1oDKKw8ybtsxWaioz9SCTMaM2stUXvJ5ih9Z9daiSEPO2IHj/nu/c/mgEUKak0 jHJ6K9MxJHu/ztTHi81xKn3VlRXMtagrdXRc6q6+G72eFNqJHtQdXRJTl1AwSlnmVLpPk5 UhBr0KoHqoaZITBbxE/ql+U52Ya5MSEWX0iUry/MXWOEBGicznaQ7sKMgLwY7w== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:30 +0100 Subject: [PATCH v4 17/18] MIPS: mobileye: eyeq5: add pinctrl nodes & pinmux function nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-17-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624312962462349 X-GMAIL-MSGID: 1789624312962462349 Pins on this platform have two functions: GPIO or something-else. We create function nodes for each something-else based on functions. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi | 125 ++++++++++++++++++++++++++++ arch/mips/boot/dts/mobileye/eyeq5.dtsi | 6 ++ 2 files changed, 131 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi new file mode 100644 index 000000000000..42acda13e57a --- /dev/null +++ b/arch/mips/boot/dts/mobileye/eyeq5-pins.dtsi @@ -0,0 +1,125 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +/* + * Default pin configuration for Mobileye EyeQ5 boards. We mostly create one + * pin configuration node per function. + */ + +&pinctrl { + timer0_pins: timer0-pins { + function = "timer0"; + pins = "PA0", "PA1"; + }; + timer1_pins: timer1-pins { + function = "timer1"; + pins = "PA2", "PA3"; + }; + timer2_pins: timer2-pins { + function = "timer2"; + pins = "PA4", "PA5"; + }; + pps0_pins: pps0-pin { + function = "timer2"; + pins = "PA4"; + }; + pps1_pins: pps1-pin { + function = "timer2"; + pins = "PA5"; + }; + timer5_ext_pins: timer5-ext-pins { + function = "timer5"; + pins = "PA6", "PA7", "PA8", "PA9"; + }; + timer5_ext_input_pins: timer5-ext-input-pins { + function = "timer5"; + pins = "PA6", "PA7"; + }; + timer5_ext_incap_a_pins: timer5-ext-incap-a-pin { + function = "timer5"; + pins = "PA6"; + }; + timer5_ext_incap_b_pins: timer5-ext-incap-b-pin { + function = "timer5"; + pins = "PA7"; + }; + can0_pins: can0-pins { + function = "can0"; + pins = "PA14", "PA15"; + }; + can1_pins: can1-pins { + function = "can1"; + pins = "PA16", "PA17"; + }; + uart0_pins: uart0-pins { + function = "uart0"; + pins = "PA10", "PA11"; + }; + uart1_pins: uart1-pins { + function = "uart1"; + pins = "PA12", "PA13"; + }; + spi0_pins: spi0-pins { + function = "spi0"; + pins = "PA18", "PA19", "PA20", "PA21", "PA22"; + }; + spi1_pins: spi1-pins { + function = "spi1"; + pins = "PA23", "PA24", "PA25", "PA26", "PA27"; + }; + spi1_slave_pins: spi1-slave-pins { + function = "spi1"; + pins = "PA24", "PA25", "PA26"; + }; + refclk0_pins: refclk0-pin { + function = "refclk0"; + pins = "PA28"; + }; + timer3_pins: timer3-pins { + function = "timer3"; + pins = "PB0", "PB1"; + }; + timer4_pins: timer4-pins { + function = "timer4"; + pins = "PB2", "PB3"; + }; + timer6_ext_pins: timer6-ext-pins { + function = "timer6"; + pins = "PB4", "PB5", "PB6", "PB7"; + }; + timer6_ext_input_pins: timer6-ext-input-pins { + function = "timer6"; + pins = "PB4", "PB5"; + }; + timer6_ext_incap_a_pins: timer6-ext-incap-a-pin { + function = "timer6"; + pins = "PB4"; + }; + timer6_ext_incap_b_pins: timer6-ext-incap-b-pin { + function = "timer6"; + pins = "PB5"; + }; + can2_pins: can2-pins { + function = "can2"; + pins = "PB10", "PB11"; + }; + uart2_pins: uart2-pins { + function = "uart2"; + pins = "PB8", "PB9"; + }; + spi2_pins: spi2-pins { + function = "spi2"; + pins = "PB12", "PB13", "PB14", "PB15", "PB16"; + }; + spi3_pins: spi3-pins { + function = "spi3"; + pins = "PB17", "PB18", "PB19", "PB20", "PB21"; + }; + spi3_slave_pins: spi3-slave-pins { + function = "spi3"; + pins = "PB18", "PB19", "PB20"; + }; + mclk0_pins: mclk0-pin { + function = "mclk0"; + pins = "PB22"; + }; +}; diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index ece71cafb6ee..ae13e8299994 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -125,6 +125,11 @@ reset: reset-controller@e00000 { reg-names = "d0", "d1", "d2"; #reset-cells = <2>; }; + + pinctrl: pinctrl@e000b0 { + compatible = "mobileye,eyeq5-pinctrl"; + reg = <0x0b0 0x30>; + }; }; gic: interrupt-controller@140000 { @@ -150,3 +155,4 @@ timer { }; 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[139.178.88.99]) by mx.google.com with ESMTPS id n36-20020a635c64000000b005d4af343858si9717691pgm.361.2024.01.31.08.34.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 08:34:48 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-46804-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=F2vykkux; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-46804-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46804-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 2149B2838BA for ; Wed, 31 Jan 2024 16:32:23 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 96DE913F003; Wed, 31 Jan 2024 16:27:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="F2vykkux" Received: from relay2-d.mail.gandi.net (relay2-d.mail.gandi.net [217.70.183.194]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C29A013BE80; Wed, 31 Jan 2024 16:27:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.194 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718449; cv=none; b=elPAkh0tfj5JgEQ4wVgMLYuD/KwIIjyVmK3Sn20mTrOVx7DxlBva1J8MVCtvZVRl+GQIYQUkis3CBCACfHSx4pppRbIPZVde4x9RctSIYjd9NfwuEWbGBIOCCMtN/pBpP2H15eZlh3REJxUCvu+AEtin0rwuIiwRRfHNzpyKWb4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706718449; c=relaxed/simple; bh=XnW4AYy3Nc97tfx3b9rBN9XG71YZGgJFnnvWMkeQV3U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Brt13EpCq7UrRCf/Sx/As7Wf6gk/p3q8CAokzmBzA5OOdypUWgWW70Sy4uKRM8NW2px7cwYmq7BGu0/5bkXBhf4Q2WElkr0yvI890PzImb/oHlbsNbpxUTNBXlxUKighkcu9mvQ/r1xArYt3lkI78ZoLsbG2zkWAt8hLdS4v0mc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=F2vykkux; arc=none smtp.client-ip=217.70.183.194 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPSA id 4DFBF4000C; Wed, 31 Jan 2024 16:27:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706718444; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E0E4D1zz8fIXJ+KURAPowU82qI2dGBP74YLhcrLKxeE=; b=F2vykkuxPmOPCEqFpG66Hjw4H+nvbRvwiORFpqCghiwDy6wgvYnqTB7tCu1698xlP+9yi3 mK8Fa1OnckzQr5yn5ufgb67Nl48UPBwBL7ChdGEgPFq3Z6lk6PKnCIlblQbQZmXDL1RllZ BYBN3lu8uy7uPLnHkOYsDCD5IlU2H82f4RMMI30fG0OH60gkF8+lJ8YS2EQubUuckh1cYr IMKfY2kyS+lDfN5yiUsN7E8vmah2Y9BZCHbV86go1Y6R2kiwczY+XBOnCs1XU1XL+DBcJ8 /sfVlQ9ZNkdbnWV/BfmNnuk+BuiflxfwggsiLuu5JucQDIO7aa/+OSynLpafMA== From: =?utf-8?q?Th=C3=A9o_Lebrun?= Date: Wed, 31 Jan 2024 17:26:31 +0100 Subject: [PATCH v4 18/18] MIPS: mobileye: eyeq5: add pinctrl properties to UART nodes Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240131-mbly-clk-v4-18-bcd00510d6a0@bootlin.com> References: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> In-Reply-To: <20240131-mbly-clk-v4-0-bcd00510d6a0@bootlin.com> To: Gregory CLEMENT , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Linus Walleij , =?utf-8?b?UmFmYcWCIE1pxYJlY2tp?= , Philipp Zabel Cc: Vladimir Kondratiev , linux-mips@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Tawfik Bayouk , linux-gpio@vger.kernel.org, =?utf-8?q?Th=C3=A9o_Lebrun?= X-Mailer: b4 0.12.4 X-GND-Sasl: theo.lebrun@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789624464878888953 X-GMAIL-MSGID: 1789624464878888953 UART nodes are present in the platform devicetree. Add pinctrl to them now that the pin controller is supported. Signed-off-by: Théo Lebrun --- arch/mips/boot/dts/mobileye/eyeq5.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi index ae13e8299994..643bbc55e2b5 100644 --- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi +++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi @@ -79,6 +79,8 @@ uart0: serial@800000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 10>; + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; }; uart1: serial@900000 { @@ -90,6 +92,8 @@ uart1: serial@900000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 11>; + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; }; uart2: serial@a00000 { @@ -101,6 +105,8 @@ uart2: serial@a00000 { clocks = <&uart_clk>, <&occ_periph>; clock-names = "uartclk", "apb_pclk"; resets = <&reset 0 12>; + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; }; olb: system-controller@e00000 {