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[2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id o3-20020a170902d4c300b001d90dcdc6fesi2993514plg.488.2024.01.31.03.09.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 31 Jan 2024 03:09:05 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-46211-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; arc=pass (i=1 spf=pass spfdomain=jmu.edu.cn dmarc=pass fromdomain=jmu.edu.cn); spf=pass (google.com: domain of linux-kernel+bounces-46211-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46211-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=jmu.edu.cn Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 13A41B2B30A for ; Wed, 31 Jan 2024 10:23:35 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C9CA97BAF3; Wed, 31 Jan 2024 10:20:47 +0000 (UTC) Received: from mail-m155101.qiye.163.com (mail-m155101.qiye.163.com [101.71.155.101]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D4E4F762DC; Wed, 31 Jan 2024 10:20:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=101.71.155.101 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696444; cv=none; b=iZ8s1PXPREu+N47QzUhNmd5UIpXUbfkhI4hqJ2uFOwQghGZYmDFrBC6JoNl9FYCq/PZAJd2gHzzDVDSuEbBYs4gvRrR3pq8KCciRMtBjfVe2qZFuD8oZ3dAJnzSvRpjAQL8ZTtzteyG02l7sGQnIdwSwvrzQrkN/CjHIVw5/MTQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706696444; c=relaxed/simple; bh=ncR9ZVIZnZgWBEFvpVMj29/3lFamrXl8RVdJlKMnu6U=; h=From:To:Cc:Subject:Date:Message-Id:MIME-Version; b=u2/IMq7VMxtlEk07+oNCNPGoiwZnSNPAcW/8Hl0Zy1ADVwjd2pACFeGZgQjbE0fb2fVpo9bIkUTLCXv0E7QQpk+4Pyf6Y6wVLFOcATSSrlnBxcP4m4+kIsAbrMokxQ9z5RBvZ3avAdOWdILmv6vrQmE8lKywKf6lgiQW/GKd14o= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn; spf=pass smtp.mailfrom=jmu.edu.cn; arc=none smtp.client-ip=101.71.155.101 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=jmu.edu.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=jmu.edu.cn Received: from amadeus-Vostro-3710.lan (unknown [116.25.94.16]) by smtp.qiye.163.com (Hmail) with ESMTPA id C9EF57E010C; Wed, 31 Jan 2024 18:20:14 +0800 (CST) From: Chukun Pan To: Bjorn Andersson Cc: Konrad Dybcio , Krzysztof Kozlowski , Conor Dooley , Rob Herring , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Chukun Pan Subject: [PATCH 1/3] arm64: dts: qcom: ipq6018: separate CPU OPP tables Date: Wed, 31 Jan 2024 18:20:01 +0800 Message-Id: <20240131102003.2061203-1-amadeus@jmu.edu.cn> X-Mailer: git-send-email 2.25.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-HM-Spam-Status: e1kfGhgUHx5ZQUpXWQgPGg8OCBgUHx5ZQUlOS1dZFg8aDwILHllBWSg2Ly tZV1koWUFITzdXWS1ZQUlXWQ8JGhUIEh9ZQVlCHk0fVhpPHhoZHk8ZGUxDSlUTARMWGhIXJBQOD1 lXWRgSC1lBWUpKTVVJTlVCT1VKTVlXWRYaDxIVHRRZQVlPS0hVSkhKQkhLVUpLS1VLWQY+ X-HM-Tid: 0a8d5f08985f03a2kunmc9ef57e010c X-HM-MType: 10 X-HM-Sender-Digest: e1kMHhlZQR0aFwgeV1kSHx4VD1lBWUc6Mhw6NRw5AjMJTU9CC04eAUgI HwgwFDlVSlVKTEtNTUJNT0pNS09JVTMWGhIXVRoWGh8eDgg7ERYOVR4fDlUYFUVZV1kSC1lBWUpK TVVJTlVCT1VKTVlXWQgBWUFNTk5LNwY+ X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789603973224935059 X-GMAIL-MSGID: 1789603973224935059 Some IPQ6000 SoCs do not come with PMIC (MP5496) chip, which causes cpufreq to be unavailable due to lack of cpu-supply. Separate CPU OPP tables from soc.dtsi to support versions with and without PMIC chip. Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts | 1 + arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi | 74 ++++++++++++++++++++ arch/arm64/boot/dts/qcom/ipq6018.dtsi | 56 --------------- 3 files changed, 75 insertions(+), 56 deletions(-) create mode 100644 arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts index f5f4827c0e17..06dfc2cb6b7f 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts +++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts @@ -8,6 +8,7 @@ /dts-v1/; #include "ipq6018.dtsi" +#include "ipq6018-opp.dtsi" / { model = "Qualcomm Technologies, Inc. IPQ6018/AP-CP01-C1"; diff --git a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi new file mode 100644 index 000000000000..9c0bed2d8bf5 --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * IPQ60xx with PMIC (MP5496) CPU OPP tables + */ + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpu_speed_bin>; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1320000000 { + opp-hz = /bits/ 64 <1320000000>; + opp-microvolt = <862500>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1440000000 { + opp-hz = /bits/ 64 <1440000000>; + opp-microvolt = <925000>; + opp-supported-hw = <0x3>; + clock-latency-ns = <200000>; + }; + + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <987500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <1062500>; + opp-supported-hw = <0x1>; + clock-latency-ns = <200000>; + }; + }; +}; + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; + cpu-supply = <&ipq6018_s2>; +}; diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi index 5e1277fea725..ea72fd5739ac 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi @@ -41,8 +41,6 @@ CPU0: cpu@0 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU1: cpu@1 { @@ -53,8 +51,6 @@ CPU1: cpu@1 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU2: cpu@2 { @@ -65,8 +61,6 @@ CPU2: cpu@2 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; CPU3: cpu@3 { @@ -77,8 +71,6 @@ CPU3: cpu@3 { next-level-cache = <&L2_0>; clocks = <&apcs_glb APCS_ALIAS0_CORE_CLK>; clock-names = "cpu"; - operating-points-v2 = <&cpu_opp_table>; - cpu-supply = <&ipq6018_s2>; }; L2_0: l2-cache { @@ -95,54 +87,6 @@ scm { }; }; - cpu_opp_table: opp-table-cpu { - compatible = "operating-points-v2-kryo-cpu"; - nvmem-cells = <&cpu_speed_bin>; - opp-shared; - - opp-864000000 { - opp-hz = /bits/ 64 <864000000>; - opp-microvolt = <725000>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1056000000 { - opp-hz = /bits/ 64 <1056000000>; - opp-microvolt = <787500>; - opp-supported-hw = <0xf>; - clock-latency-ns = <200000>; - }; - - opp-1320000000 { - opp-hz = /bits/ 64 <1320000000>; - opp-microvolt = <862500>; - opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1440000000 { - opp-hz = /bits/ 64 <1440000000>; - opp-microvolt = <925000>; - opp-supported-hw = <0x3>; - clock-latency-ns = <200000>; - }; - - opp-1608000000 { - opp-hz = /bits/ 64 <1608000000>; - opp-microvolt = <987500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - - opp-1800000000 { - opp-hz = /bits/ 64 <1800000000>; - opp-microvolt = <1062500>; - opp-supported-hw = <0x1>; - clock-latency-ns = <200000>; - }; - }; - pmuv8: pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; From patchwork Wed Jan 31 10:20:02 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 194651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1794140dyb; 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Add a separate CPU OPP tables for these SoCs. Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi | 49 +++++++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi diff --git a/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi new file mode 100644 index 000000000000..acb4774da33e --- /dev/null +++ b/arch/arm64/boot/dts/qcom/ipq6000-opp.dtsi @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * IPQ6000 without PMIC (MP5496) CPU OPP tables + */ + +/ { + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-kryo-cpu"; + nvmem-cells = <&cpu_speed_bin>; + opp-shared; + + opp-864000000 { + opp-hz = /bits/ 64 <864000000>; + opp-microvolt = <725000>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + opp-microvolt = <787500>; + opp-supported-hw = <0xf>; + clock-latency-ns = <200000>; + }; + + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <850000>; + opp-supported-hw = <0x4>; + clock-latency-ns = <200000>; + }; + }; +}; + +&CPU0 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU1 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU2 { + operating-points-v2 = <&cpu_opp_table>; +}; + +&CPU3 { + operating-points-v2 = <&cpu_opp_table>; +}; From patchwork Wed Jan 31 10:20:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chukun Pan X-Patchwork-Id: 194650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1791854dyb; Wed, 31 Jan 2024 02:23:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IHH0+oxVekopfAMz0KMCNuCaysqnNLorsLrb9J/Lwyg34GT4Q5YMcV1tdKw/ulohxtBS6pe X-Received: by 2002:a19:f506:0:b0:50e:7225:38fd with SMTP id j6-20020a19f506000000b0050e722538fdmr849759lfb.35.1706696618022; Wed, 31 Jan 2024 02:23:38 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706696617; cv=pass; d=google.com; s=arc-20160816; b=x1EdSzmsMkqUp20k9m0aouamYQAuFHtH6NCcEiu3hSQM/P4KneYKn/bOXqEE1FR6sq mf4PrUfSWECnpKJxX/9bu+DzoFrqVSri0f9HdSQL+laLem9HOLfidV4vjRksuhJ0ksAJ zieUCn3uEmQ3LimzX+H1pGGzeF0q6XiVDvGjDhdUUTyVGR4yhDIPAfpzBjD+l31osEfp Z0qdltr2gj1dtT+bD9F3f2KGcSkKEoFXkwe8lxlsyzWC/vpxCEUYK8md5sahjcgdBb7D DJU+v5TyK11vig5fijucLTD4E9JKJaASDJO1+cbM2VoKd2NgeZ27cftNXV3joPD/BR1V qgSg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from; bh=9eNF55yRZZvrz2FYpGZTksFEER9NdLKJ3BNer5RiN/0=; fh=Hz0aRbOV3q2/iIbE6Wn6q3iNaGNc2q16rwZWW6ZNCaY=; b=pzlzmkHCG1JVXmj0GO2qPJEnsSpLTAtsLq6AioUUcvAMAaQM9G+RNEEcGFQDcVOtXS WdR75kqiRIN9hUZ7Fa9Yf/WyJnTBhY2iwKz7WRWfbeFbaW3qHmuQX+vsz6wvHgFWfrsc agiWlr/lttw3iVeyYJiECAUkIqRM5IF8FvR8WHM8v6BBLS72kTo9RHm8+f1AEiyCTKJ0 MJuEryVw1cCMhOB15dH4pAz741SbSYn8uTGARxt/eoRHFH8O1Bv72PpDfUYyLyN7Ggz7 LDfwUzEQ7q+Pd4GAvkSsOAZ6DeFoYRRDzkiTEZiwIyC4NkBYyThLu8/rMO8jVJED+uz3 RhZg==; dara=google.com ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1 spf=pass spfdomain=jmu.edu.cn dmarc=pass fromdomain=jmu.edu.cn); spf=pass (google.com: domain of linux-kernel+bounces-46212-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-46212-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=jmu.edu.cn X-Forwarded-Encrypted: i=1; AJvYcCXD0vHeoCmk8XzUlfJMFdiGx8VMsY8KJXfpegLQ97D/H2JAoBaCgieY9hvcAMZLPCiHYrkaCDStgmEUDA3VN140y5ys/g== Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Signed-off-by: Chukun Pan --- arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi index 9c0bed2d8bf5..a0d53588f298 100644 --- a/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq6018-opp.dtsi @@ -37,6 +37,13 @@ opp-1440000000 { clock-latency-ns = <200000>; }; + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-microvolt = <937500>; + opp-supported-hw = <0x2>; + clock-latency-ns = <200000>; + }; + opp-1608000000 { opp-hz = /bits/ 64 <1608000000>; opp-microvolt = <987500>;