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Tue, 30 Jan 2024 23:26:19 +0000 Received: from LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9]) by LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9%3]) with mapi id 15.20.7228.029; Tue, 30 Jan 2024 23:26:19 +0000 From: "Corona, Ernesto" To: "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" CC: "Corona, Ernesto" , "'oleksandrs@mellanox.com'" , "'jiri@nvidia.com'" , "Castro, Omar Eduardo" , "'omar.eduardo.castro@linux.intel.com'" , "'pombredanne@nexb.com'" , "'gregkh@linuxfoundation.org'" , "'arnd@arndb.de'" , "'bbrezillon@kernel.org'" , "'rdunlap@infradead.org'" , "'johan@kernel.org'" , "'axboe@kernel.dk'" , "'joel@jms.id.au'" , "'palmer@sifive.com'" , "'keescook@chromium.org'" , "'vilhelm.gray@gmail.com'" , "'federico.vaga@cern.ch'" , "'Jonathan.Cameron@huawei.com'" , "Luck, Tony" , "'christian.gromm@microchip.com'" , "'linus.walleij@linaro.org'" , "'zzyiwei@google.com'" , "'rubini@gnudd.com'" , "'viresh.kumar@linaro.org'" , "'mika.westerberg@linux.intel.com'" , "Filary, Steven A" , "'vadimp@mellanox.com'" , "'amithash@fb.com'" , "'patrickw3@fb.com'" , "Chen, Luke" , "'billy_tsai@aspeedtech.com'" , "'rgrs@protonmail.com'" Subject: [PATCH 30 1/7] Add JTAG core driver Thread-Topic: [PATCH 30 1/7] Add JTAG core driver Thread-Index: AdpTwn19iWWLMIbtQG6Zmu4WwU9j2Q== Date: Tue, 30 Jan 2024 23:26:19 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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It provide user layer API interface for flashing and debugging external devices which equipped with JTAG interface using standard transactions. Driver exposes set of IOCTL to user space for: - XFER: SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan); SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan); - GIOCSTATUS read the current TAPC state of the JTAG controller - SIOCSTATE Forces the JTAG TAPC to go into a particular state. - SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency. - IOCBITBANG for low level control of JTAG signals. Driver core provides set of internal APIs for allocation and registration: - jtag_register; - jtag_unregister; - jtag_alloc; - jtag_free; Platform driver on registration with jtag-core creates the next entry in dev folder: /dev/jtagX Signed-off-by: Oleksandr Shamray Signed-off-by: Jiri Pirko Signed-off-by: Ernesto Corona Signed-off-by: Omar Castro Acked-by: Philippe Ombredanne Cc: Greg Kroah-Hartman Cc: Arnd Bergmann Cc: Boris Brezillon Cc: Randy Dunlap Cc: Johan Hovold Cc: Jens Axboe Cc: Joel Stanley Cc: Palmer Dabbelt Cc: Kees Cook Cc: William Breathitt Gray Cc: Federico Vaga Cc: Jonathan Cameron Cc: Tony Luck Cc: Christian Gromm Cc: Linus Walleij Cc: Yiwei Zhang Cc: Alessandro Rubini Cc: Viresh Kumar Cc: Mika Westerberg Cc: Steven Filary Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Luke Chen Cc: Billy Tsai Cc: Rgrs --- v29->v30 Comments pointed by Steven Filary - Add pre and post padding support for JTAG transfers. - Add padding bit configuration definition. - Use C99 flexible arrays. - Add debug messages for JTAG core driver IOCTL operations. - Add support for JTAG_SIOCTRST(Set TRST pin for JTAG). - Update Ioctl number to 0xB9 due conflicts. v28->v29 Comments pointed by Steven Filary - Expand bitbang function to accept multiples bitbang operations within a single JTAG_IOCBITBANG call. It will receive a buffer with TDI and TMS values and it is expected that driver fills TDO fields with its corresponding output value for every transaction. - Always setup JTAG controller to master mode but disable JTAG output when the driver is not in use to allow other HW to own the JTAG bus. Remove SCU register accesses. This register controls the JTAG controller mode (main/subordinate). - Fix static analysis issues - Add support for multichain. Set tap state and xfer operations now include two tap state arguments: current state and end state. v27->v28 Comments pointed by Steven Filary - Replace JTAG_IOCRUNTEST with JTAG_SIOCSTATE adding support for all TAPC end states in SW mode using a lookup table to navigate across states. - Add support for simultaneous READ/WRITE transfers (JTAG_READ_WRITE_XFER). - Support for switching JTAG controller mode between slave and master mode. - Setup JTAG controller mode to master only when the driver is opened, letting other HW to own the JTAG bus when it isn't in use. - Include JTAG bit bang IOCTL for low level JTAG control usage (JTAG_IOCBITBANG). v24->v25 Comments pointed by Greg KH - set values to enums in jtag.h v23->v24 Notifications from kbuild test robot - Add include types.h header to jtag.h - remove unecessary jtag_release v22->v23 Comments pointed by Greg KH - remove restriction of allocated JTAG devs- - add validation fo idle values - remove unnecessary blank line - change retcode for xfer - remove unecessary jtag_release callback - remove unecessary defined fron jtag.h - align in one line define JTAG_IOCRUNTEST v21->v22 Comments pointed by Andy Shevchenko - Fix 0x0f -> 0x0F in ioctl-number.txt - Add description to #define MAX_JTAG_NAME_LEN - Remove unnecessary entry *dev from struct jtag - Remove redundant parens - Described mandatory callbacks and removed unnecessary - Set JTAG_MAX_XFER_DATA_LEN to power of 2 - rework driver alloc/register to devm_ variant - increasing line length up to 84 in order to improve readability. Comments pointed by Randy Dunlap - fix spell in ABI doccumentation v20->v21 Comments pointed by Randy Dunlap - Fix JTAG dirver help in Kconfig v19->v20 Comments pointed by Randy Dunlap - Fix JTAG dirver help in Kconfig Notifications from kbuild test robot - fix incompatible type casts v18->v19 Comments pointed by Julia Cartwright - Fix memory leak on jtag_alloc exit v17->v18 Comments pointed by Julia Cartwright - Change to return -EOPNOTSUPP in case of error in JTAG_GIOCFREQ - Add ops callbacks check to jtag_alloc - Add err check for copy_to_user - Move the kfree() above the if (err) in JTAG_IOCXFER - remove unnecessary check for error after put_user - add padding to struct jtag_xfer v16->v17 Comments pointed by Julia Cartwright - Fix memory allocation on jtag alloc - Move out unnecessary form lock on jtag open - Rework jtag register behavior v15->v16 Comments pointed by Florian Fainelli - move check jtag->ops->* in ioctl before get_user() - change error type -EINVAL --> -EBUSY on open already opened jtag - remove unnecessary ARCH_DMA_MINALIGN flag from kzalloc - remove define ARCH_DMA_MINALIGN v14->v15 v13->v14 Comments pointed by Philippe Ombredanne - Change style of head block comment from /**/ to // v12->v13 Comments pointed by Philippe Ombredanne - Change jtag.c licence type to SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note and reorder line with license in description v11->v12 Comments pointed by Greg KH - Change jtag.h licence type to SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note and reorder line with license in description Comments pointed by Chip Bilbrey - Remove Apeed reference from uapi jtag.h header - Remove access mode from xfer and idle transactions - Add new ioctl JTAG_SIOCMODE for set hw mode - Add single open per device blocking v10->v11 Notifications from kbuild test robot - Add include types.h header to jtag.h - fix incompatible type of xfer callback - remove rdundant class defination - Fix return order in case of xfer error V9->v10 Comments pointed by Greg KH - remove unnecessary alignment for pirv data - move jtag_copy_to_user and jtag_copy_from_user code just to ioctl - move int jtag_run_test_idle_op and jtag_xfer_op code just to ioctl - change return error codes to more applicable - add missing error checks - fix error check order in ioctl - remove unnecessary blank lines - add param validation to ioctl - remove compat_ioctl - remove only one open per JTAG port blocking. User will care about this. - Fix idr memory leak on jtag_exit - change cdev device type to misc V8->v9 Comments pointed by Arnd Bergmann - use get_user() instead of __get_user(). - change jtag->open type from int to atomic_t - remove spinlock on jtg_open - remove mutex on jtag_register - add unregister_chrdev_region on jtag_init err - add unregister_chrdev_region on jtag_exit - remove unnecessary pointer casts - add *data parameter to xfer function prototype v7->v8 Comments pointed by Moritz Fischer - Fix misspelling s/friver/driver v6->v7 Notifications from kbuild test robot - Remove include asm/types.h from jtag.h - Add include to jtag.c v5->v6 v4->v5 v3->v4 Comments pointed by Arnd Bergmann - change transaction pointer tdio type to __u64 - change internal status type from enum to __u32 - reorder jtag_xfer members to avoid the implied padding - add __packed attribute to jtag_xfer and jtag_run_test_idle v2->v3 Notifications from kbuild test robot - Change include path to in jtag.h v1->v2 Comments pointed by Greg KH - Change license type from GPLv2/BSD to GPLv2 - Change type of variables which crossed user/kernel to __type - Remove "default n" from Kconfig Comments pointed by Andrew Lunn - Change list_add_tail in jtag_unregister to list_del Comments pointed by Neil Armstrong - Add SPDX-License-Identifier instead of license text Comments pointed by Arnd Bergmann - Change __copy_to_user to memdup_user - Change __put_user to put_user - Change type of variables to __type for compatible 32 and 64-bit systems - Add check for maximum xfer data size - Change lookup data mechanism to get jtag data from inode - Add .compat_ioctl to file ops - Add mem alignment for jtag priv data Comments pointed by Tobias Klauser - Change function names to avoid match with variable types - Fix description for jtag_ru_test_idle in uapi jtag.h - Fix misprints IDEL/IDLE, trough/through --- drivers/Kconfig | 2 + drivers/Makefile | 1 + drivers/jtag/Kconfig | 17 ++ drivers/jtag/Makefile | 1 + drivers/jtag/jtag.c | 387 ++++++++++++++++++++++++++++++++++++++ include/linux/jtag.h | 49 +++++ include/uapi/linux/jtag.h | 378 +++++++++++++++++++++++++++++++++++++ 7 files changed, 835 insertions(+) create mode 100644 drivers/jtag/Kconfig create mode 100644 drivers/jtag/Makefile create mode 100644 drivers/jtag/jtag.c create mode 100644 include/linux/jtag.h create mode 100644 include/uapi/linux/jtag.h diff --git a/drivers/Kconfig b/drivers/Kconfig index 7bdad836fc62..c13e0a575a69 100644 --- a/drivers/Kconfig +++ b/drivers/Kconfig @@ -245,4 +245,6 @@ source "drivers/cdx/Kconfig" source "drivers/dpll/Kconfig" +source "drivers/jtag/Kconfig" + endmenu diff --git a/drivers/Makefile b/drivers/Makefile index 37fd6ce3bd7f..cb0e4a719cef 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -198,3 +198,4 @@ obj-$(CONFIG_CDX_BUS) += cdx/ obj-$(CONFIG_DPLL) += dpll/ obj-$(CONFIG_S390) += s390/ +obj-$(CONFIG_JTAG_ASPEED) += jtag/ diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig new file mode 100644 index 000000000000..47771fcd3c5b --- /dev/null +++ b/drivers/jtag/Kconfig @@ -0,0 +1,17 @@ +menuconfig JTAG + tristate "JTAG support" + help + This provides basic core functionality support for JTAG class devices. + Hardware that is equipped with a JTAG microcontroller can be + supported by using this driver's interfaces. + This driver exposes a set of IOCTLs to the user space for + the following commands: + SDR: Performs an IEEE 1149.1 Data Register scan + SIR: Performs an IEEE 1149.1 Instruction Register scan. + RUNTEST: Forces the IEEE 1149.1 bus to a run state for a specified + number of clocks or a specified time period. + + If you want this support, you should say Y here. + + To compile this driver as a module, choose M here: the module will + be called jtag. diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile new file mode 100644 index 000000000000..af374939a9e6 --- /dev/null +++ b/drivers/jtag/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_JTAG) += jtag.o diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c new file mode 100644 index 000000000000..070ca77ca8a6 --- /dev/null +++ b/drivers/jtag/jtag.c @@ -0,0 +1,387 @@ +// SPDX-License-Identifier: GPL-2.0-only +// Copyright (c) 2018 Mellanox Technologies. All rights reserved. +// Copyright (c) 2018 Oleksandr Shamray +// Copyright (c) 2019 Intel Corporation + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static char *end_status_str[] = { "tlr", "idle", "selDR", "capDR", "sDR", + "ex1DR", "pDR", "ex2DR", "updDR", "selIR", + "capIR", "sIR", "ex1IR", "pIR", "ex2IR", + "updIR", "current" }; + +struct jtag { + struct miscdevice miscdev; + const struct jtag_ops *ops; + int id; + unsigned long *priv; +}; + +static DEFINE_IDA(jtag_ida); + +void *jtag_priv(struct jtag *jtag) +{ + return jtag->priv; +} +EXPORT_SYMBOL_GPL(jtag_priv); + +static long jtag_ioctl(struct file *file, unsigned int cmd, unsigned long arg) +{ + struct jtag *jtag = file->private_data; + struct jtag_tap_state tapstate; + struct jtag_xfer xfer; + struct bitbang_packet bitbang; + struct tck_bitbang *bitbang_data; + struct jtag_mode mode; + u8 *xfer_data; + u32 data_size; + u32 value; + u32 active; + int err; + + if (!arg) + return -EINVAL; + + switch (cmd) { + case JTAG_GIOCFREQ: + if (!jtag->ops->freq_get) + return -EOPNOTSUPP; + + err = jtag->ops->freq_get(jtag, &value); + if (err) + break; + dev_dbg(jtag->miscdev.parent, "JTAG_GIOCFREQ: freq get = %d", + value); + + if (put_user(value, (__u32 __user *)arg)) + err = -EFAULT; + break; + + case JTAG_SIOCFREQ: + if (!jtag->ops->freq_set) + return -EOPNOTSUPP; + + if (get_user(value, (__u32 __user *)arg)) + return -EFAULT; + if (value == 0) + return -EINVAL; + + err = jtag->ops->freq_set(jtag, value); + dev_dbg(jtag->miscdev.parent, "JTAG_SIOCFREQ: freq set = %d", + value); + break; + + case JTAG_SIOCSTATE: + if (copy_from_user(&tapstate, (const void __user *)arg, + sizeof(struct jtag_tap_state))) + return -EFAULT; + + if (tapstate.from > JTAG_STATE_CURRENT) + return -EINVAL; + + if (tapstate.endstate > JTAG_STATE_CURRENT) + return -EINVAL; + + if (tapstate.reset > JTAG_FORCE_RESET) + return -EINVAL; + + dev_dbg(jtag->miscdev.parent, + "JTAG_SIOCSTATE: status set from %s to %s reset %d tck %d", + end_status_str[tapstate.from], + end_status_str[tapstate.endstate], tapstate.reset, + tapstate.tck); + + err = jtag->ops->status_set(jtag, &tapstate); + break; + + case JTAG_IOCXFER: + { + u8 ubit_mask = GENMASK(7, 0); + u8 remaining_bits = 0x0; + union pad_config padding; + + if (copy_from_user(&xfer, (const void __user *)arg, + sizeof(struct jtag_xfer))) + return -EFAULT; + + if (xfer.length >= JTAG_MAX_XFER_DATA_LEN) + return -EINVAL; + + if (xfer.type > JTAG_SDR_XFER) + return -EINVAL; + + if (xfer.direction > JTAG_READ_WRITE_XFER) + return -EINVAL; + + if (xfer.from > JTAG_STATE_CURRENT) + return -EINVAL; + + if (xfer.endstate > JTAG_STATE_CURRENT) + return -EINVAL; + + data_size = DIV_ROUND_UP(xfer.length, BITS_PER_BYTE); + xfer_data = memdup_user(u64_to_user_ptr(xfer.tdio), data_size); + + /* Save unused remaining bits in this transfer */ + if ((xfer.length % BITS_PER_BYTE)) { + ubit_mask = GENMASK((xfer.length % BITS_PER_BYTE) - 1, + 0); + remaining_bits = xfer_data[data_size - 1] & ~ubit_mask; + } + + if (IS_ERR(xfer_data)) + return -EFAULT; + padding.int_value = xfer.padding; + dev_dbg(jtag->miscdev.parent, + "JTAG_IOCXFER: type: %s direction: %d, END : %s, padding: (value: %d) pre_pad: %d post_pad: %d, len: %d\n", + xfer.type ? "DR" : "IR", xfer.direction, + end_status_str[xfer.endstate], padding.pad_data, + padding.pre_pad_number, padding.post_pad_number, + xfer.length); + + print_hex_dump_debug("I:", DUMP_PREFIX_NONE, 16, 1, xfer_data, + data_size, false); + + err = jtag->ops->xfer(jtag, &xfer, xfer_data); + if (err) { + kfree(xfer_data); + return err; + } + + print_hex_dump_debug("O:", DUMP_PREFIX_NONE, 16, 1, xfer_data, + data_size, false); + + /* Restore unused remaining bits in this transfer */ + xfer_data[data_size - 1] = (xfer_data[data_size - 1] + & ubit_mask) | remaining_bits; + + err = copy_to_user(u64_to_user_ptr(xfer.tdio), + (void *)xfer_data, data_size); + kfree(xfer_data); + if (err) + return -EFAULT; + + if (copy_to_user((void __user *)arg, (void *)&xfer, + sizeof(struct jtag_xfer))) + return -EFAULT; + break; + } + + case JTAG_GIOCSTATUS: + err = jtag->ops->status_get(jtag, &value); + if (err) + break; + dev_dbg(jtag->miscdev.parent, "JTAG_GIOCSTATUS: status get %s", + end_status_str[value]); + + err = put_user(value, (__u32 __user *)arg); + break; + case JTAG_IOCBITBANG: + if (copy_from_user(&bitbang, (const void __user *)arg, + sizeof(struct bitbang_packet))) + return -EFAULT; + + if (bitbang.length >= JTAG_MAX_XFER_DATA_LEN) + return -EINVAL; + + data_size = bitbang.length * sizeof(struct tck_bitbang); + bitbang_data = memdup_user((void __user *)bitbang.data, + data_size); + if (IS_ERR(bitbang_data)) + return -EFAULT; + + err = jtag->ops->bitbang(jtag, &bitbang, bitbang_data); + if (err) { + kfree(bitbang_data); + return err; + } + err = copy_to_user((void __user *)bitbang.data, + (void *)bitbang_data, data_size); + kfree(bitbang_data); + if (err) + return -EFAULT; + break; + case JTAG_SIOCMODE: + if (!jtag->ops->mode_set) + return -EOPNOTSUPP; + + if (copy_from_user(&mode, (const void __user *)arg, + sizeof(struct jtag_mode))) + return -EFAULT; + + dev_dbg(jtag->miscdev.parent, + "JTAG_SIOCMODE: mode set feature %d mode %d", + mode.feature, mode.mode); + err = jtag->ops->mode_set(jtag, &mode); + break; + case JTAG_SIOCTRST: + if (!jtag->ops->trst_set) + return -EOPNOTSUPP; + + if (get_user(active, (__u32 __user *)arg)) + return -EFAULT; + + dev_dbg(jtag->miscdev.parent, + "JTAG_SIOCTRST: active %d", active); + + err = jtag->ops->trst_set(jtag, active); + break; + + default: + return -EINVAL; + } + return err; +} + +static int jtag_open(struct inode *inode, struct file *file) +{ + struct jtag *jtag = container_of(file->private_data, + struct jtag, + miscdev); + + file->private_data = jtag; + if (jtag->ops->enable(jtag)) + return -EBUSY; + return nonseekable_open(inode, file); +} + +static int jtag_release(struct inode *inode, struct file *file) +{ + struct jtag *jtag = file->private_data; + + if (jtag->ops->disable(jtag)) + return -EBUSY; + return 0; +} + +static const struct file_operations jtag_fops = { + .owner = THIS_MODULE, + .open = jtag_open, + .llseek = noop_llseek, + .unlocked_ioctl = jtag_ioctl, + .release = jtag_release, +}; + +struct jtag *jtag_alloc(struct device *host, size_t priv_size, + const struct jtag_ops *ops) +{ + struct jtag *jtag; + + if (!host) + return NULL; + + if (!ops) + return NULL; + + if (!ops->status_set || !ops->status_get || !ops->xfer) + return NULL; + + jtag = kzalloc(sizeof(*jtag), GFP_KERNEL); + if (!jtag) + return NULL; + jtag->priv = kzalloc(priv_size, GFP_KERNEL); + if (!jtag->priv) + return NULL; + + jtag->ops = ops; + jtag->miscdev.parent = host; + + return jtag; +} +EXPORT_SYMBOL_GPL(jtag_alloc); + +void jtag_free(struct jtag *jtag) +{ + kfree(jtag); +} +EXPORT_SYMBOL_GPL(jtag_free); + +static int jtag_register(struct jtag *jtag) +{ + struct device *dev = jtag->miscdev.parent; + int err; + int id; + + if (!dev) + return -ENODEV; + + id = ida_simple_get(&jtag_ida, 0, 0, GFP_KERNEL); + if (id < 0) + return id; + + jtag->id = id; + + jtag->miscdev.fops = &jtag_fops; + jtag->miscdev.minor = MISC_DYNAMIC_MINOR; + jtag->miscdev.name = kasprintf(GFP_KERNEL, "jtag%d", id); + if (!jtag->miscdev.name) { + err = -ENOMEM; + goto err_jtag_alloc; + } + + err = misc_register(&jtag->miscdev); + if (err) { + dev_err(jtag->miscdev.parent, "Unable to register device\n"); + goto err_jtag_name; + } + return 0; + +err_jtag_name: + kfree(jtag->miscdev.name); +err_jtag_alloc: + ida_simple_remove(&jtag_ida, id); + return err; +} + +static void jtag_unregister(struct jtag *jtag) +{ + misc_deregister(&jtag->miscdev); + kfree(jtag->miscdev.name); + ida_simple_remove(&jtag_ida, jtag->id); +} + +static void devm_jtag_unregister(struct device *dev, void *res) +{ + jtag_unregister(*(struct jtag **)res); +} + +int devm_jtag_register(struct device *dev, struct jtag *jtag) +{ + struct jtag **ptr; + int ret; + + ptr = devres_alloc(devm_jtag_unregister, sizeof(struct jtag *), + GFP_KERNEL); + if (!ptr) + return -ENOMEM; + + ret = jtag_register(jtag); + if (!ret) { + *ptr = jtag; + devres_add(dev, ptr); + } else { + devres_free(ptr); + } + return ret; +} +EXPORT_SYMBOL_GPL(devm_jtag_register); + +static void __exit jtag_exit(void) +{ + ida_destroy(&jtag_ida); +} + +module_exit(jtag_exit); + +MODULE_AUTHOR("Oleksandr Shamray "); +MODULE_DESCRIPTION("Generic jtag support"); +MODULE_LICENSE("GPL v2"); diff --git a/include/linux/jtag.h b/include/linux/jtag.h new file mode 100644 index 000000000000..87396ee21df9 --- /dev/null +++ b/include/linux/jtag.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Mellanox Technologies. All rights reserved. */ +/* Copyright (c) 2018 Oleksandr Shamray */ +/* Copyright (c) 2019 Intel Corporation */ + +#ifndef __LINUX_JTAG_H +#define __LINUX_JTAG_H + +#include +#include + +#define JTAG_MAX_XFER_DATA_LEN (0xFFFFFFFF) + +struct jtag; +/** + * struct jtag_ops - callbacks for JTAG control functions: + * + * @freq_get: get frequency function. Filled by dev driver + * @freq_set: set frequency function. Filled by dev driver + * @status_get: get JTAG TAPC state function. Mandatory, Filled by dev driver + * @status_set: set JTAG TAPC state function. Mandatory, Filled by dev driver + * @xfer: send JTAG xfer function. Mandatory func. Filled by dev driver + * @mode_set: set specific work mode for JTAG. Filled by dev driver + * @trst_set: set TRST pin active(pull low) for JTAG. Filled by dev driver + * @bitbang: set low level bitbang operations. Filled by dev driver + * @enable: enables JTAG interface in controller mode. Filled by dev driver + * @disable: disables JTAG interface controller mode. Filled by dev driver + */ +struct jtag_ops { + int (*freq_get)(struct jtag *jtag, u32 *freq); + int (*freq_set)(struct jtag *jtag, u32 freq); + int (*status_get)(struct jtag *jtag, u32 *state); + int (*status_set)(struct jtag *jtag, struct jtag_tap_state *endst); + int (*xfer)(struct jtag *jtag, struct jtag_xfer *xfer, u8 *xfer_data); + int (*mode_set)(struct jtag *jtag, struct jtag_mode *jtag_mode); + int (*trst_set)(struct jtag *jtag, u32 active); + int (*bitbang)(struct jtag *jtag, struct bitbang_packet *bitbang, + struct tck_bitbang *bitbang_data); + int (*enable)(struct jtag *jtag); + int (*disable)(struct jtag *jtag); +}; + +void *jtag_priv(struct jtag *jtag); +int devm_jtag_register(struct device *dev, struct jtag *jtag); +struct jtag *jtag_alloc(struct device *host, size_t priv_size, + const struct jtag_ops *ops); +void jtag_free(struct jtag *jtag); + +#endif /* __LINUX_JTAG_H */ diff --git a/include/uapi/linux/jtag.h b/include/uapi/linux/jtag.h new file mode 100644 index 000000000000..3dd0c51284f1 --- /dev/null +++ b/include/uapi/linux/jtag.h @@ -0,0 +1,378 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* Copyright (c) 2018 Mellanox Technologies. All rights reserved. */ +/* Copyright (c) 2018 Oleksandr Shamray */ +/* Copyright (c) 2019 Intel Corporation */ + +#ifndef __UAPI_LINUX_JTAG_H +#define __UAPI_LINUX_JTAG_H + +#include +#include + +/* + * JTAG_XFER_MODE: JTAG transfer mode. Used to set JTAG controller transfer mode + * This is bitmask for feature param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_MODE 0 +/* + * JTAG_CONTROL_MODE: JTAG controller mode. Used to set JTAG controller mode + * This is bitmask for feature param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_CONTROL_MODE 1 +/* + * JTAG_TCK_CYCLE_DELAY_COUNT: JTAG delay counter for aspeed_jtag_tck_cycle. Used + * set the number of jtag_tck_cycle delays repetitions. + * This is bitmask for feature param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_TCK_CYCLE_DELAY_COUNT 2 +/* + * JTAG_CONTROLLER_OUTPUT_DISABLE: JTAG controller mode output disable, it is + * used to enable other devices to own the JTAG bus. + * This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_CONTROLLER_OUTPUT_DISABLE 0 +/* + * JTAG_CONTROLLER_MODE: JTAG controller mode. Used to set JTAG controller in + * host mode. + * This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_CONTROLLER_MODE 1 +/* + * JTAG_XFER_HW_MODE: JTAG hardware mode. Used to set HW drived or bitbang + * mode. This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_HW_MODE 1 +/* + * JTAG_XFER_SW_MODE: JTAG software mode. Used to set SW drived or bitbang + * mode. This is bitmask for mode param in jtag_mode for ioctl JTAG_SIOCMODE + */ +#define JTAG_XFER_SW_MODE 0 + +/** + * enum jtag_tapstate: + * + * @JTAG_STATE_TLRESET: JTAG state machine Test Logic Reset state + * @JTAG_STATE_IDLE: JTAG state machine IDLE state + * @JTAG_STATE_SELECTDR: JTAG state machine SELECT_DR state + * @JTAG_STATE_CAPTUREDR: JTAG state machine CAPTURE_DR state + * @JTAG_STATE_SHIFTDR: JTAG state machine SHIFT_DR state + * @JTAG_STATE_EXIT1DR: JTAG state machine EXIT-1 DR state + * @JTAG_STATE_PAUSEDR: JTAG state machine PAUSE_DR state + * @JTAG_STATE_EXIT2DR: JTAG state machine EXIT-2 DR state + * @JTAG_STATE_UPDATEDR: JTAG state machine UPDATE DR state + * @JTAG_STATE_SELECTIR: JTAG state machine SELECT_IR state + * @JTAG_STATE_CAPTUREIR: JTAG state machine CAPTURE_IR state + * @JTAG_STATE_SHIFTIR: JTAG state machine SHIFT_IR state + * @JTAG_STATE_EXIT1IR: JTAG state machine EXIT-1 IR state + * @JTAG_STATE_PAUSEIR: JTAG state machine PAUSE_IR state + * @JTAG_STATE_EXIT2IR: JTAG state machine EXIT-2 IR state + * @JTAG_STATE_UPDATEIR: JTAG state machine UPDATE IR state + * @JTAG_STATE_CURRENT: JTAG current state, saved by driver + */ +enum jtag_tapstate { + JTAG_STATE_TLRESET, + JTAG_STATE_IDLE, + JTAG_STATE_SELECTDR, + JTAG_STATE_CAPTUREDR, + JTAG_STATE_SHIFTDR, + JTAG_STATE_EXIT1DR, + JTAG_STATE_PAUSEDR, + JTAG_STATE_EXIT2DR, + JTAG_STATE_UPDATEDR, + JTAG_STATE_SELECTIR, + JTAG_STATE_CAPTUREIR, + JTAG_STATE_SHIFTIR, + JTAG_STATE_EXIT1IR, + JTAG_STATE_PAUSEIR, + JTAG_STATE_EXIT2IR, + JTAG_STATE_UPDATEIR, + JTAG_STATE_CURRENT +}; + +/** + * enum jtag_reset: + * + * @JTAG_NO_RESET: JTAG run TAP from current state + * @JTAG_FORCE_RESET: JTAG force TAP to reset state + */ +enum jtag_reset { + JTAG_NO_RESET = 0, + JTAG_FORCE_RESET = 1, +}; + +/** + * enum jtag_xfer_type: + * + * @JTAG_SIR_XFER: SIR transfer + * @JTAG_SDR_XFER: SDR transfer + */ +enum jtag_xfer_type { + JTAG_SIR_XFER = 0, + JTAG_SDR_XFER = 1, +}; + +/** + * enum jtag_xfer_direction: + * + * @JTAG_READ_XFER: read transfer + * @JTAG_WRITE_XFER: write transfer + * @JTAG_READ_WRITE_XFER: read & write transfer + */ +enum jtag_xfer_direction { + JTAG_READ_XFER = 1, + JTAG_WRITE_XFER = 2, + JTAG_READ_WRITE_XFER = 3, +}; + +/** + * struct jtag_tap_state - forces JTAG state machine to go into a TAPC + * state + * + * @reset: 0 - run IDLE/PAUSE from current state + * 1 - go through TEST_LOGIC/RESET state before IDLE/PAUSE + * @from: initital jtag state + * @endstate: jtag end state + * @tck: clock counter + * + * Structure provide interface to JTAG device for JTAG set state execution. + */ +struct jtag_tap_state { + __u8 reset; + __u8 from; + __u8 endstate; + __u32 tck; +}; + +/** + * union pad_config - Padding Configuration: + * + * @type: transfer type + * @pre_pad_number: Number of prepadding bits bit[11:0] + * @post_pad_number: Number of prepadding bits bit[23:12] + * @pad_data : Bit value to be used by pre and post padding bit[24] + * @int_value: unsigned int packed padding configuration value bit[32:0] + * + * Structure provide pre and post padding configuration in a single __u32 + */ +union pad_config { + struct { + __u32 pre_pad_number : 12; + __u32 post_pad_number : 12; + __u32 pad_data : 1; + __u32 rsvd : 7; + }; + __u32 int_value; +}; + +/** + * struct jtag_xfer - jtag xfer: + * + * @type: transfer type + * @direction: xfer direction + * @from: xfer current state + * @endstate: xfer end state + * @padding: xfer padding + * @length: xfer bits length + * @tdio : xfer data array + * + * Structure provide interface to JTAG device for JTAG SDR/SIR xfer execution. + */ +struct jtag_xfer { + __u8 type; + __u8 direction; + __u8 from; + __u8 endstate; + __u32 padding; + __u32 length; + __u64 tdio; +}; + +/** + * struct bitbang_packet - jtag bitbang array packet: + * + * @data: JTAG Bitbang struct array pointer(input/output) + * @length: array size (input) + * + * Structure provide interface to JTAG device for JTAG bitbang bundle execution + */ +struct bitbang_packet { + struct tck_bitbang *data; + __u32 length; +} __attribute__((__packed__)); + +/** + * struct jtag_bitbang - jtag bitbang: + * + * @tms: JTAG TMS + * @tdi: JTAG TDI (input) + * @tdo: JTAG TDO (output) + * + * Structure provide interface to JTAG device for JTAG bitbang execution. + */ +struct tck_bitbang { + __u8 tms; + __u8 tdi; + __u8 tdo; +} __attribute__((__packed__)); + +/** + * struct jtag_mode - jtag mode: + * + * @feature: 0 - JTAG feature setting selector for JTAG controller HW/SW + * 1 - JTAG feature setting selector for controller bus mode + * output (enable / disable). + * @mode: (0 - SW / 1 - HW) for JTAG_XFER_MODE feature(0) + * (0 - output disable / 1 - output enable) for JTAG_CONTROL_MODE + * feature(1) + * + * Structure provide configuration modes to JTAG device. + */ +struct jtag_mode { + __u32 feature; + __u32 mode; +}; + +/* ioctl interface */ +#define __JTAG_IOCTL_MAGIC 0xb9 + +#define JTAG_SIOCSTATE _IOW(__JTAG_IOCTL_MAGIC, 0, struct jtag_tap_state) +#define JTAG_SIOCFREQ _IOW(__JTAG_IOCTL_MAGIC, 1, unsigned int) +#define JTAG_GIOCFREQ _IOR(__JTAG_IOCTL_MAGIC, 2, unsigned int) +#define JTAG_IOCXFER _IOWR(__JTAG_IOCTL_MAGIC, 3, struct jtag_xfer) +#define JTAG_GIOCSTATUS _IOWR(__JTAG_IOCTL_MAGIC, 4, enum jtag_tapstate) +#define JTAG_SIOCMODE _IOW(__JTAG_IOCTL_MAGIC, 5, unsigned int) +#define JTAG_IOCBITBANG _IOW(__JTAG_IOCTL_MAGIC, 6, unsigned int) +#define JTAG_SIOCTRST _IOW(__JTAG_IOCTL_MAGIC, 7, unsigned int) + +/** + * struct tms_cycle - This structure represents a tms cycle state. + * + * @tmsbits: is the bitwise representation of the needed tms transitions to + * move from one state to another. + * @count: number of jumps needed to move to the needed state. + * + */ +struct tms_cycle { + unsigned char tmsbits; + unsigned char count; +}; + +/* + * This is the complete set TMS cycles for going from any TAP state to any + * other TAP state, following a "shortest path" rule. + */ +static const struct tms_cycle _tms_cycle_lookup[][16] = { +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* TLR */{{0x00, 0}, {0x00, 1}, {0x02, 2}, {0x02, 3}, {0x02, 4}, {0x0a, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0a, 5}, {0x2a, 6}, {0x1a, 5}, {0x06, 3}, {0x06, 4}, {0x06, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x16, 5}, {0x16, 6}, {0x56, 7}, {0x36, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* RTI */{{0x07, 3}, {0x00, 0}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x0d, 4}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x1b, 5} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SelDR*/{{0x03, 2}, {0x03, 3}, {0x00, 0}, {0x00, 1}, {0x00, 2}, {0x02, 2}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x02, 3}, {0x0a, 4}, {0x06, 3}, {0x01, 1}, {0x01, 2}, {0x01, 3}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x05, 3}, {0x05, 4}, {0x15, 5}, {0x0d, 4} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* CapDR*/{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x00, 0}, {0x00, 1}, {0x01, 1}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x01, 2}, {0x05, 3}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SDR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x00, 0}, {0x01, 1}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x01, 2}, {0x05, 3}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex1DR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x02, 3}, {0x00, 0}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x00, 1}, {0x02, 2}, {0x01, 1}, {0x07, 3}, {0x07, 4}, {0x07, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x17, 5}, {0x17, 6}, {0x57, 7}, {0x37, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* PDR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x01, 2}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x00, 0}, {0x01, 1}, {0x03, 2}, {0x0f, 4}, {0x0f, 5}, {0x0f, 6}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x2f, 6}, {0x2f, 7}, {0xaf, 8}, {0x6f, 7} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex2DR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x00, 1}, {0x02, 2}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x02, 3}, {0x00, 0}, {0x01, 1}, {0x07, 3}, {0x07, 4}, {0x07, 5}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x17, 5}, {0x17, 6}, {0x57, 7}, {0x37, 6} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* UpdDR*/{{0x07, 3}, {0x00, 1}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x00, 0}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x1b, 5} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SelIR*/{{0x01, 1}, {0x01, 2}, {0x05, 3}, {0x05, 4}, {0x05, 5}, {0x15, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x15, 6}, {0x55, 7}, {0x35, 6}, {0x00, 0}, {0x00, 1}, {0x00, 2}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x02, 2}, {0x02, 3}, {0x0a, 4}, {0x06, 3} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* CapIR*/{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x00, 0}, {0x00, 1}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x01, 1}, {0x01, 2}, {0x05, 3}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* SIR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x0f, 5}, {0x00, 0}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x01, 1}, {0x01, 2}, {0x05, 3}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex1IR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x03, 4}, {0x0b, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0b, 5}, {0x2b, 6}, {0x1b, 5}, {0x07, 3}, {0x07, 4}, {0x02, 3}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x00, 0}, {0x00, 1}, {0x02, 2}, {0x01, 1} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* PIR */{{0x1f, 5}, {0x03, 3}, {0x07, 3}, {0x07, 4}, {0x07, 5}, {0x17, 5}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x17, 6}, {0x57, 7}, {0x37, 6}, {0x0f, 4}, {0x0f, 5}, {0x01, 2}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x05, 3}, {0x00, 0}, {0x01, 1}, {0x03, 2} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* Ex2IR*/{{0x0f, 4}, {0x01, 2}, {0x03, 2}, {0x03, 3}, {0x03, 4}, {0x0b, 4}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x0b, 5}, {0x2b, 6}, {0x1b, 5}, {0x07, 3}, {0x07, 4}, {0x00, 1}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x02, 2}, {0x02, 3}, {0x00, 0}, {0x01, 1} }, + +/* TLR RTI SelDR CapDR SDR Ex1DR*/ +/* UpdIR*/{{0x07, 3}, {0x00, 1}, {0x01, 1}, {0x01, 2}, {0x01, 3}, {0x05, 3}, +/* PDR Ex2DR UpdDR SelIR CapIR SIR*/ + {0x05, 4}, {0x15, 5}, {0x0d, 4}, {0x03, 2}, {0x03, 3}, {0x03, 4}, +/* Ex1IR PIR Ex2IR UpdIR*/ + {0x0b, 4}, {0x0b, 5}, {0x2b, 6}, {0x00, 0} }, +}; + +#endif /* __UAPI_LINUX_JTAG_H */ From patchwork Tue Jan 30 23:30:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: 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Signed-off-by: Oleksandr Shamray Signed-off-by: Jiri Pirko Signed-off-by: Ernesto Corona Signed-off-by: Omar Castro Acked-by: Rob Herring Cc: Jonathan Corbet Cc: Mauro Carvalho Chehab Cc: Alexandre Belloni Cc: "Theodore Ts'o" Cc: Arnd Bergmann Cc: Eric Biggers Cc: Mark Rutland Cc: Joel Stanley Cc: Andrew Jeffery Cc: Steven Filary Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Luke Chen Cc: Billy Tsai Cc: Rgrs --- v29->v30 Comments pointed by Steven Filary - Add Suport for 26xx series v28->v29 Comments pointed by Ernesto Corona - Change documentation to the new dt-bindings yaml format. v27->v28 v26->v27 v25->v26 v24->v25 v23->v24 v22->v23 v21->v22 v20->v21 v19->v20 v18->v19 v17->v18 v16->v17 v15->v16 Comments pointed by Joel Stanley - change clocks = <&clk_apb> to proper clocks = <&syscon ASPEED_CLK_APB> - add reset descriptions in bindings file v14->v15 v13->v14 v12->v13 v11->v12 v10->v11 v9->v10 v8->v9 v7->v8 Comments pointed by pointed by Joel Stanley - Change compatible string to ast2400 and ast2000 V6->v7 Comments pointed by Tobias Klauser - Fix spell "Doccumentation" -> "Documentation" v5->v6 Comments pointed by Tobias Klauser - Small nit: s/documentation/Documentation/ v4->v5 V3->v4 Comments pointed by Rob Herring - delete unnecessary "status" and "reg-shift" descriptions in bindings file v2->v3 Comments pointed by Rob Herring - split Aspeed jtag driver and binding to separate patches - delete unnecessary "status" and "reg-shift" descriptions in bindings file --- .../devicetree/bindings/jtag/aspeed-jtag.yaml | 85 +++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml diff --git a/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml b/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml new file mode 100644 index 000000000000..1a412e83b81b --- /dev/null +++ b/Documentation/devicetree/bindings/jtag/aspeed-jtag.yaml @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/jtag/aspeed-jtag.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed JTAG driver for ast2400, ast2500 and ast2600 SoC + +description: + Driver adds support of Aspeed 24/25/2600 series SOC JTAG controller. + Driver implements the following jtag ops + freq_get + freq_set + status_get + status_set + xfer + mode_set + bitbang + enable + disable + + It has been tested on Mellanox system with BMC equipped with + Aspeed 2520 SoC for programming CPLD devices. + + It has also been tested on Intel system using Aspeed 25xx SoC + for JTAG communication. + + Tested on Intel system using Aspeed 26xx SoC for JTAG communication. + +maintainers: + - Oleksandr Shamray + - Jiri Pirko + - Ernesto Corona + +properties: + compatible: + oneOf: + - items: + - enum: + - aspeed,ast2400-jtag + - aspeed,ast2500-jtag + - aspeed,ast2600-jtag + + + reg: + items: + - description: JTAG Master controller register range + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +examples: + - | + #include + #include + + jtag: jtag@1e6e4000 { + compatible = "aspeed,ast2500-jtag"; + reg = <0x1e6e4000 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER>; + interrupts = <43>; + }; + - | + #include + #include + + jtag1: jtag@1e6e4100 { + compatible = "aspeed,ast2600-jtag"; + reg = <0x1e6e4100 0x40>; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER2>; + interrupts = ; + }; + +... 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Driver implements the following jtag ops: - freq_get; - freq_set; - status_get; - status_set - xfer; - mode_set; - bitbang; - enable; - disable; It has been tested on Mellanox system with BMC equipped with Aspeed 2520 SoC for programming CPLD devices. It has also been tested on Intel system using Aspeed 25xx SoC for JTAG communication. Tested on Intel system using Aspeed 26xx SoC for JTAG communication. Signed-off-by: Oleksandr Shamray Signed-off-by: Jiri Pirko Signed-off-by: Ernesto Corona Signed-off-by: Omar Castro Acked-by: Arnd Bergmann Acked-by: Philippe Ombredanne Acked-by: Joel Stanley Cc: Joel Stanley Cc: Andrew Jeffery Cc: Philipp Zabel Cc: Steven Filary Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Luke Chen Cc: Billy Tsai Cc: Rgrs --- v29->v30 Comments pointed by Steven Filary - Add Suport for 26xx series Software mode Hardware mode 1 (disabled by default) Hardware mode 2 (enabled by default) up to 512 bit lenght transfers - clang jtag-aspeed.c - Add pre and post padding support for JTAG transfers. - For 26xx series add TRST_N pin transition from low to high during TLR jtag state transition in HW and SW modes. Comments pointed by Moritz Fischer - Moved tms_cycle_loopup to jtag.hardware Comments pointed by Paul Fertser - Removed scu_base from aspeed_jtag structure. - Fixed Frequency calculation based on Aspeed 2600,2500 specs. - Removed tck as it is ignored. v28->v29 Comments pointed by Steven Filary - Expand bitbang function to accept multiples bitbang operations within a single JTAG_IOCBITBANG call. It will receive a buffer with TDI and TMS values and it is expected that driver fills TDO fields with its corresponding output value for every transaction. - Always setup JTAG controller to host mode but disable JTAG output when the driver is not in use to allow other HW to own the JTAG bus. Remove SCU register accesses. This register controls the JTAG controller mode (host controller/target). - Encansulate dev_dgb message into DEBUG_JTAG macros to improve driver's JTAG performace. - Add support for multichain. Set tap state and xfer operations now include two tap state arguments: current state and end state. v27->v28 Comments pointed by Steven Filary - Replace JTAG_IOCRUNTEST with JTAG_SIOCSTATE adding support for all TAPC end states in SW mode using a lookup table to navigate across states. - Add support for simultaneous READ/WRITE transfers (JTAG_READ_WRITE_XFER). - Support for switching JTAG controller mode between target and controller mode. - Setup JTAG controller mode to host only when the driver is opened, letting other HW to own the JTAG bus when it isn't in use. - Include JTAG bit bang IOCTL for low level JTAG control usage (JTAG_IOCBITBANG). - Add debug traces. - Add support for register polling (default) due it is 3 times faster than interrupt mode. Define USE_INTERRUPTS macro to enable interrupt usage. - Remove unnecessary delays for aspeed_jtag_status_set function. It makes SW mode 4 times faster. - Clean data buffer on aspeed_jtag_xfer_sw before tdo writes to avoid data output corruption for read operations in SW mode. - Correct register settings for HW mode transfer operations. - Propagate ret codes all the way from low level functions up to JTAG_IOCXFER call. - Support for partitioned transfers. Single JTAG transfer through multiples JTAG_IOCXFER calls. Now end transmission(scan_end) also evaluates transfer end state. v26->v27 Changes made by Oleksandr Shamray - change aspeed_jtag_sw_delay to udelay function in bit-bang operation v25->v26 v24->v25 Comments pointed by Greg KH - reduced debug printouts v23->v24 v22->v23 v21->v22 Comments pointed by Andy Shevchenko - rearrange ASPEED register defines - simplified JTAG divider calculation formula - change delay function in bit-bang operation - add helper functions for TAP states switching - remove unnecessary comments - remove redundant debug messages - make dines for repetative register bit sets - fixed indentation - change checks from negative to positive - add error check for clk_prepare_enable - rework driver alloc/register to devm_ variant - Increasing line length up to 85 in order to improve readability v20->v21 v19->v20 Notifications from kbuild test robot - add static declaration to 'aspeed_jtag_init' and 'aspeed_jtag_deinit' functions v18->v19 v17->v18 v16->v17 v15->v16 Comments pointed by Joel Stanley - Add reset_control on Jtag init/deinit v14->v15 Comments pointed by Joel Stanley - Add ARCH_ASPEED || COMPILE_TEST to Kconfig - remove unused offset variable - remove "aspeed_jtag" from dev_err and dev_dbg messages - change clk_prepare_enable initialisation order v13->v14 Comments pointed by Philippe Ombredanne - Change style of head block comment from /**/ to // v12->v13 Comments pointed by Philippe Ombredanne - Change jtag-aspeed.c licence type to SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note and reorder line with license- add reset descriptions in bndings file in description Comments pointed by Kun Yi - Changed capability check for aspeed,ast2400-jtag/ast200-jtag v11->v12 Comments pointed by Chip Bilbrey - Remove access mode from xfer and idle transactions - Add new ioctl JTAG_SIOCMODE for set hw mode v10->v11 v9->v10 V8->v9 Comments pointed by Arnd Bergmann - add *data parameter to xfer function prototype v7->v8 Comments pointed by Joel Stanley - aspeed_jtag_init replace goto to return; - change input variables type from __u32 to u32 in functios freq_get, freq_set, status_get - change sm_ variables type from char to u8 - in jatg_init add disable clocks on error case - remove release_mem_region on error case - remove devm_free_irq on jtag_deinit - Fix misspelling Disabe/Disable - Change compatible string to ast2400 and ast2000 v6->v7 Notifications from kbuild test robot - Add include to jtag-asapeed.c v5->v6 v4->v5 Comments pointed by Arnd Bergmann - Added HAS_IOMEM dependence in Kconfig to avoid "undefined reference to `devm_ioremap_resource'" error, because in some arch this not supported v3->v4 Comments pointed by Arnd Bergmann - change transaction pointer tdio type to __u64 - change internal status type from enum to __u32 v2->v3 v1->v2 Comments pointed by Greg KH - change license type from GPLv2/BSD to GPLv2 Comments pointed by Neil Armstrong - Add clk_prepare_enable/clk_disable_unprepare in clock init/deinit - Change .compatible to soc-specific compatible names aspeed,aspeed4000-jtag/aspeed5000-jtag - Added dt-bindings Comments pointed by Arnd Bergmann - Reorder functions and removed the forward declarations - Add static const qualifier to state machine states transitions - Change .compatible to soc-specific compatible names aspeed,aspeed4000-jtag/aspeed5000-jtag - Add dt-bindings Comments pointed by Randy Dunlap - Change module name jtag-aspeed in description in Kconfig Comments pointed by kbuild test robot - Remove invalid include - add resource_size instead of calculation --- drivers/jtag/Kconfig | 29 + drivers/jtag/Makefile | 1 + drivers/jtag/jtag-aspeed.c | 1666 ++++++++++++++++++++++++++++++++++++ 3 files changed, 1696 insertions(+) create mode 100644 drivers/jtag/jtag-aspeed.c diff --git a/drivers/jtag/Kconfig b/drivers/jtag/Kconfig index 47771fcd3c5b..d66b60448da0 100644 --- a/drivers/jtag/Kconfig +++ b/drivers/jtag/Kconfig @@ -15,3 +15,32 @@ menuconfig JTAG To compile this driver as a module, choose M here: the module will be called jtag. + +menuconfig JTAG_ASPEED + tristate "Aspeed SoC JTAG controller support" + depends on JTAG && HAS_IOMEM + depends on ARCH_ASPEED || COMPILE_TEST + help + This provides support for Aspeed JTAG devices equipped on Aspeed + SoC 24xx, 25xx and 26xx families. Driver allows programming of + hardware devices, connected to SoC through the JTAG interface. + + If you want this support, you should say Y here. + + To compile this driver as a module, choose M here: the module will + be called jtag-aspeed. + +config USE_INTERRUPTS + bool "Use interrupts as event wait mechanism" + depends on JTAG_ASPEED + default n + help + Aspeed SoC 24xx, 25xx and 26xx driver monitors the JTAG shift + operation completion by either polling or waiting for an interrupt. + + This flag is used by Aspeed driver to select from either interrupt or + polling as wait mechanism for JTAG controller completion events. + + If you want interrupt support, you should say Y here. + + If you want polling support, you should say N here. diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile index af374939a9e6..04a855e2df28 100644 --- a/drivers/jtag/Makefile +++ b/drivers/jtag/Makefile @@ -1 +1,2 @@ obj-$(CONFIG_JTAG) += jtag.o +obj-$(CONFIG_JTAG_ASPEED) += jtag-aspeed.o diff --git a/drivers/jtag/jtag-aspeed.c b/drivers/jtag/jtag-aspeed.c new file mode 100644 index 000000000000..f2e8c20beab4 --- /dev/null +++ b/drivers/jtag/jtag-aspeed.c @@ -0,0 +1,1666 @@ +// SPDX-License-Identifier: GPL-2.0 +// Copyright (c) 2018 Mellanox Technologies. All rights reserved. +// Copyright (c) 2018 Oleksandr Shamray +// Copyright (c) 2019 Intel Corporation + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define ASPEED_JTAG_DATA 0x00 +#define ASPEED_JTAG_INST 0x04 +#define ASPEED_JTAG_CTRL 0x08 +#define ASPEED_JTAG_ISR 0x0C +#define ASPEED_JTAG_SW 0x10 +#define ASPEED_JTAG_TCK 0x14 +#define ASPEED_JTAG_EC 0x18 + +#define ASPEED_JTAG_DATA_MSB 0x01 +#define ASPEED_JTAG_DATA_CHUNK_SIZE 0x20 +#define ASPEED_JTAG_HW2_DATA_CHUNK_SIZE 512 + +/* ASPEED_JTAG_CTRL: Engine Control 24xx and 25xx series*/ +#define ASPEED_JTAG_CTL_ENG_EN BIT(31) +#define ASPEED_JTAG_CTL_ENG_OUT_EN BIT(30) +#define ASPEED_JTAG_CTL_FORCE_TMS BIT(29) +#define ASPEED_JTAG_CTL_IR_UPDATE BIT(26) +#define ASPEED_JTAG_CTL_INST_LEN(x) ((x) << 20) +#define ASPEED_JTAG_CTL_LASPEED_INST BIT(17) +#define ASPEED_JTAG_CTL_INST_EN BIT(16) +#define ASPEED_JTAG_CTL_DR_UPDATE BIT(10) +#define ASPEED_JTAG_CTL_DATA_LEN(x) ((x) << 4) +#define ASPEED_JTAG_CTL_LASPEED_DATA BIT(1) +#define ASPEED_JTAG_CTL_DATA_EN BIT(0) + +/* ASPEED_JTAG_CTRL: Engine Control 26xx series*/ +#define ASPEED_JTAG_CTL_26XX_RESET_FIFO BIT(21) +#define ASPEED_JTAG_CTL_26XX_FIFO_MODE_CTRL BIT(20) +#define ASPEED_JTAG_CTL_26XX_TRANS_LEN(x) ((x) << 8) +#define ASPEED_JTAG_CTL_26XX_TRANS_MASK GENMASK(17, 8) +#define ASPEED_JTAG_CTL_26XX_MSB_FIRST BIT(6) +#define ASPEED_JTAG_CTL_26XX_TERM_TRANS BIT(5) +#define ASPEED_JTAG_CTL_26XX_LASPEED_TRANS BIT(4) +#define ASPEED_JTAG_CTL_26XX_INST_EN BIT(1) + +/* ASPEED_JTAG_ISR : Interrupt status and enable */ +#define ASPEED_JTAG_ISR_INST_PAUSE BIT(19) +#define ASPEED_JTAG_ISR_INST_COMPLETE BIT(18) +#define ASPEED_JTAG_ISR_DATA_PAUSE BIT(17) +#define ASPEED_JTAG_ISR_DATA_COMPLETE BIT(16) +#define ASPEED_JTAG_ISR_INST_PAUSE_EN BIT(3) +#define ASPEED_JTAG_ISR_INST_COMPLETE_EN BIT(2) +#define ASPEED_JTAG_ISR_DATA_PAUSE_EN BIT(1) +#define ASPEED_JTAG_ISR_DATA_COMPLETE_EN BIT(0) +#define ASPEED_JTAG_ISR_INT_EN_MASK GENMASK(3, 0) +#define ASPEED_JTAG_ISR_INT_MASK GENMASK(19, 16) + +/* ASPEED_JTAG_SW : Software Mode and Status */ +#define ASPEED_JTAG_SW_MODE_EN BIT(19) +#define ASPEED_JTAG_SW_MODE_TCK BIT(18) +#define ASPEED_JTAG_SW_MODE_TMS BIT(17) +#define ASPEED_JTAG_SW_MODE_TDIO BIT(16) + +/* ASPEED_JTAG_TCK : TCK Control */ +#define ASPEED_JTAG_TCK_DIVISOR_MASK GENMASK(10, 0) +#define ASPEED_JTAG_TCK_GET_DIV(x) ((x) & ASPEED_JTAG_TCK_DIVISOR_MASK) + +/* ASPEED_JTAG_EC : Controller set for go to IDLE */ +#define ASPEED_JTAG_EC_TRST BIT(31) +#define ASPEED_JTAG_EC_GO_IDLE BIT(0) + +#define ASPEED_JTAG_IOUT_LEN(len) \ + (ASPEED_JTAG_CTL_ENG_EN | \ + ASPEED_JTAG_CTL_ENG_OUT_EN | \ + ASPEED_JTAG_CTL_INST_LEN(len)) + +#define ASPEED_JTAG_DOUT_LEN(len) \ + (ASPEED_JTAG_CTL_ENG_EN | \ + ASPEED_JTAG_CTL_ENG_OUT_EN | \ + ASPEED_JTAG_CTL_DATA_LEN(len)) + +#define ASPEED_JTAG_TRANS_LEN(len) \ + (ASPEED_JTAG_CTL_ENG_EN | \ + ASPEED_JTAG_CTL_ENG_OUT_EN | \ + ASPEED_JTAG_CTL_26XX_TRANS_LEN(len)) + +#define ASPEED_JTAG_SW_TDIO (ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TDIO) + +#define ASPEED_JTAG_GET_TDI(direction, byte) \ + (((direction) & JTAG_WRITE_XFER) ? byte : UINT_MAX) + +#define ASPEED_JTAG_TCK_WAIT 10 +#define ASPEED_JTAG_RESET_CNTR 10 +#define WAIT_ITERATIONS 300 + +/* Use this macro to switch between HW mode 1(comment out) and 2(defined) */ +#define ASPEED_JTAG_HW_MODE_2_ENABLE 1 + +/* ASPEED JTAG HW MODE 2 (Only supported in AST26xx series) */ +#define ASPEED_JTAG_SHDATA 0x20 +#define ASPEED_JTAG_SHINST 0x24 +#define ASPEED_JTAG_PADCTRL0 0x28 +#define ASPEED_JTAG_PADCTRL1 0x2C +#define ASPEED_JTAG_SHCTRL 0x30 +#define ASPEED_JTAG_GBLCTRL 0x34 +#define ASPEED_JTAG_INTCTRL 0x38 +#define ASPEED_JTAG_STAT 0x3C + +/* ASPEED_JTAG_PADCTRLx : Padding control 0 and 1 */ +#define ASPEED_JTAG_PADCTRL_PAD_DATA BIT(24) +#define ASPEED_JTAG_PADCTRL_POSTPAD(x) (((x) & GENMASK(8, 0)) << 12) +#define ASPEED_JTAG_PADCTRL_PREPAD(x) (((x) & GENMASK(8, 0)) << 0) + +/* ASPEED_JTAG_SHCTRL: Shift Control */ +#define ASPEED_JTAG_SHCTRL_FRUN_TCK_EN BIT(31) +#define ASPEED_JTAG_SHCTRL_STSHIFT_EN BIT(30) +#define ASPEED_JTAG_SHCTRL_TMS(x) (((x) & GENMASK(13, 0)) << 16) +#define ASPEED_JTAG_SHCTRL_POST_TMS(x) (((x) & GENMASK(2, 0)) << 13) +#define ASPEED_JTAG_SHCTRL_PRE_TMS(x) (((x) & GENMASK(2, 0)) << 10) +#define ASPEED_JTAG_SHCTRL_PAD_SEL0 (0) +#define ASPEED_JTAG_SHCTRL_PAD_SEL1 BIT(9) +#define ASPEED_JTAG_SHCTRL_END_SHIFT BIT(8) +#define ASPEED_JTAG_SHCTRL_START_SHIFT BIT(7) +#define ASPEED_JTAG_SHCTRL_LWRDT_SHIFT(x) ((x) & GENMASK(6, 0)) + +#define ASPEED_JTAG_END_SHIFT_DISABLED 0 + +/* ASPEED_JTAG_GBLCTRL : Global Control */ +#define ASPEED_JTAG_GBLCTRL_ENG_MODE_EN BIT(31) +#define ASPEED_JTAG_GBLCTRL_ENG_OUT_EN BIT(30) +#define ASPEED_JTAG_GBLCTRL_FORCE_TMS BIT(29) +#define ASPEED_JTAG_GBLCTRL_SHIFT_COMPLETE BIT(28) +#define ASPEED_JTAG_GBLCTRL_RESET_FIFO BIT(25) +#define ASPEED_JTAG_GBLCTRL_FIFO_CTRL_MODE BIT(24) +#define ASPEED_JTAG_GBLCTRL_UPDT_SHIFT(x) (((x) & GENMASK(9, 7)) << 13) +#define ASPEED_JTAG_GBLCTRL_STSHIFT(x) (((x) & GENMASK(0, 0)) << 16) +#define ASPEED_JTAG_GBLCTRL_TRST BIT(15) +#define ASPEED_JTAG_CLK_DIVISOR_MASK GENMASK(11, 0) +#define ASPEED_JTAG_CLK_GET_DIV(x) ((x) & ASPEED_JTAG_CLK_DIVISOR_MASK) + +/* ASPEED_JTAG_INTCTRL: Interrupt Control */ +#define ASPEED_JTAG_INTCTRL_SHCPL_IRQ_EN BIT(16) +#define ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT BIT(0) + +/* ASPEED_JTAG_STAT: JTAG HW mode 2 status */ +#define ASPEED_JTAG_STAT_ENG_IDLE BIT(0) + +#define ASPEED_JTAG_MAX_PAD_SIZE 512 + +/* Use this macro to set us delay to WA the intensive R/W FIFO usage issue */ +#define AST26XX_FIFO_UDELAY 2 + +/* Use this macro to set us delay for JTAG Controller to be programmed */ +#define AST26XX_JTAG_CTRL_UDELAY 2 + +/*#define CONFIG_USE_INTERRUPTS*/ +#define DEBUG_JTAG + +static const char * const regnames[] = { + [ASPEED_JTAG_DATA] = "ASPEED_JTAG_DATA", + [ASPEED_JTAG_INST] = "ASPEED_JTAG_INST", + [ASPEED_JTAG_CTRL] = "ASPEED_JTAG_CTRL", + [ASPEED_JTAG_ISR] = "ASPEED_JTAG_ISR", + [ASPEED_JTAG_SW] = "ASPEED_JTAG_SW", + [ASPEED_JTAG_TCK] = "ASPEED_JTAG_TCK", + [ASPEED_JTAG_EC] = "ASPEED_JTAG_EC", + [ASPEED_JTAG_SHDATA] = "ASPEED_JTAG_SHDATA", + [ASPEED_JTAG_SHINST] = "ASPEED_JTAG_SHINST", + [ASPEED_JTAG_PADCTRL0] = "ASPEED_JTAG_PADCTRL0", + [ASPEED_JTAG_PADCTRL1] = "ASPEED_JTAG_PADCTRL1", + [ASPEED_JTAG_SHCTRL] = "ASPEED_JTAG_SHCTRL", + [ASPEED_JTAG_GBLCTRL] = "ASPEED_JTAG_GBLCTRL", + [ASPEED_JTAG_INTCTRL] = "ASPEED_JTAG_INTCTRL", + [ASPEED_JTAG_STAT] = "ASPEED_JTAG_STAT", +}; + +#define ASPEED_JTAG_NAME "jtag-aspeed" + +struct aspeed_jtag { + void __iomem *reg_base; + struct device *dev; + struct clk *pclk; + enum jtag_tapstate status; + int irq; + struct reset_control *rst; + u32 flag; + wait_queue_head_t jtag_wq; + u32 mode; + enum jtag_tapstate current_state; + u32 tck_period; + u32 tck_cycle_delay_count; + const struct jtag_low_level_functions *llops; + u32 pad_data_one[ASPEED_JTAG_MAX_PAD_SIZE / 32]; + u32 pad_data_zero[ASPEED_JTAG_MAX_PAD_SIZE / 32]; +}; + +/* + * Multi generation support is enabled by fops and low level assped function + * mapping using asped_jtag_functions struct as config mechanism. + */ + +struct jtag_low_level_functions { + void (*output_disable)(struct aspeed_jtag *aspeed_jtag); + void (*controller_enable)(struct aspeed_jtag *aspeed_jtag); + int (*xfer_push_data)(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, u32 bits_len); + int (*xfer_push_data_last)(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, u32 bits_len); + void (*xfer_sw)(struct aspeed_jtag *aspeed_jtag, struct jtag_xfer *xfer, + u32 *data); + int (*xfer_hw)(struct aspeed_jtag *aspeed_jtag, struct jtag_xfer *xfer, + u32 *data); + void (*xfer_hw_fifo_delay)(void); + void (*xfer_sw_delay)(struct aspeed_jtag *aspeed_jtag); + void (*xfer_tck_cycle_delay)(struct aspeed_jtag *aspeed_jtag); + irqreturn_t (*jtag_interrupt)(s32 this_irq, void *dev_id); +}; + +struct aspeed_jtag_functions { + const struct jtag_ops *aspeed_jtag_ops; + const struct jtag_low_level_functions *aspeed_jtag_llops; +}; + +#ifdef DEBUG_JTAG +static char *end_status_str[] = { "tlr", "idle", "selDR", "capDR", + "sDR", "ex1DR", "pDR", "ex2DR", + "updDR", "selIR", "capIR", "sIR", + "ex1IR", "pIR", "ex2IR", "updIR", + "current"}; +#endif + +static u32 aspeed_jtag_read(struct aspeed_jtag *aspeed_jtag, u32 reg) +{ + u32 val = readl(aspeed_jtag->reg_base + reg); + +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "read:%s val = 0x%08x\n", regnames[reg], val); +#endif + return val; +} + +static void aspeed_jtag_write(struct aspeed_jtag *aspeed_jtag, u32 val, u32 reg) +{ +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "write:%s val = 0x%08x\n", regnames[reg], + val); +#endif + writel(val, aspeed_jtag->reg_base + reg); +} + +static int aspeed_jtag_freq_set(struct jtag *jtag, u32 freq) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + unsigned long apb_frq; + u32 tck_val; + u16 div; + + if (!freq) + return -EINVAL; + + apb_frq = clk_get_rate(aspeed_jtag->pclk); + if (!apb_frq) + return -EOPNOTSUPP; + + div = (apb_frq - 1) / freq; + tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK); + aspeed_jtag_write(aspeed_jtag, + (tck_val & ~ASPEED_JTAG_TCK_DIVISOR_MASK) | div, + ASPEED_JTAG_TCK); + aspeed_jtag->tck_period = + DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * (div + 1), apb_frq); + return 0; +} + +static int aspeed_jtag_freq_set_26xx(struct jtag *jtag, u32 freq) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + unsigned long apb_frq; + u32 tck_val; + u16 div; + + if (!freq) + return -EINVAL; + + apb_frq = clk_get_rate(aspeed_jtag->pclk); + if (!apb_frq) + return -EOPNOTSUPP; + + div = (apb_frq - 1) / freq; + tck_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + aspeed_jtag_write(aspeed_jtag, + (tck_val & ~ASPEED_JTAG_CLK_DIVISOR_MASK) | div, + ASPEED_JTAG_GBLCTRL); + return 0; +} + +static int aspeed_jtag_freq_get(struct jtag *jtag, u32 *frq) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + u32 pclk; + u32 tck; + + pclk = clk_get_rate(aspeed_jtag->pclk); + tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_TCK); + *frq = pclk / (ASPEED_JTAG_TCK_GET_DIV(tck) + 1); + + return 0; +} + +static int aspeed_jtag_freq_get_26xx(struct jtag *jtag, u32 *frq) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + u32 pclk; + u32 tck; + + pclk = clk_get_rate(aspeed_jtag->pclk); + tck = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + *frq = pclk / (ASPEED_JTAG_CLK_GET_DIV(tck) + 1); + + return 0; +} + +static inline void aspeed_jtag_output_disable(struct aspeed_jtag *aspeed_jtag) +{ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL); +} + +static inline void +aspeed_jtag_output_disable_26xx(struct aspeed_jtag *aspeed_jtag) +{ + u32 reg_val; + + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL) & + ASPEED_JTAG_CLK_DIVISOR_MASK; + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, reg_val, ASPEED_JTAG_GBLCTRL); +} + +static inline void aspeed_jtag_controller(struct aspeed_jtag *aspeed_jtag) +{ + aspeed_jtag_write(aspeed_jtag, + (ASPEED_JTAG_CTL_ENG_EN | ASPEED_JTAG_CTL_ENG_OUT_EN), + ASPEED_JTAG_CTRL); + + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TDIO, + ASPEED_JTAG_SW); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_ISR_INST_PAUSE | + ASPEED_JTAG_ISR_INST_COMPLETE | + ASPEED_JTAG_ISR_DATA_PAUSE | + ASPEED_JTAG_ISR_DATA_COMPLETE | + ASPEED_JTAG_ISR_INST_PAUSE_EN | + ASPEED_JTAG_ISR_INST_COMPLETE_EN | + ASPEED_JTAG_ISR_DATA_PAUSE_EN | + ASPEED_JTAG_ISR_DATA_COMPLETE_EN, + ASPEED_JTAG_ISR); /* Enable Interrupt */ +} + +static inline void aspeed_jtag_controller_26xx(struct aspeed_jtag *aspeed_jtag) +{ + u32 reg_val; + + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL) & + ASPEED_JTAG_CLK_DIVISOR_MASK; + if (aspeed_jtag->mode & JTAG_XFER_HW_MODE) { + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW); + } else { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_SW_MODE_EN | + ASPEED_JTAG_SW_MODE_TDIO, + ASPEED_JTAG_SW); + } + /* + * For the software mode, it's still necessary to enable out_en and + * select the out_en in the hw2 register to maintain control of the + * TRST bit same as hw2. + */ + aspeed_jtag_write(aspeed_jtag, + reg_val | ASPEED_JTAG_GBLCTRL_ENG_MODE_EN | + ASPEED_JTAG_GBLCTRL_ENG_OUT_EN | + ASPEED_JTAG_GBLCTRL_TRST, + ASPEED_JTAG_GBLCTRL); + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + dev_dbg(aspeed_jtag->dev, "ASPEED_JTAG_GBLCTRL:val = 0x%08x\n", reg_val); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_INTCTRL_SHCPL_IRQ_EN | + ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT, + ASPEED_JTAG_INTCTRL); /* Enable HW2 IRQ */ + + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_ISR_INST_PAUSE | + ASPEED_JTAG_ISR_INST_COMPLETE | + ASPEED_JTAG_ISR_DATA_PAUSE | + ASPEED_JTAG_ISR_DATA_COMPLETE | + ASPEED_JTAG_ISR_INST_PAUSE_EN | + ASPEED_JTAG_ISR_INST_COMPLETE_EN | + ASPEED_JTAG_ISR_DATA_PAUSE_EN | + ASPEED_JTAG_ISR_DATA_COMPLETE_EN, + ASPEED_JTAG_ISR); /* Enable HW1 Interrupts */ +} + +static void aspeed_jtag_tck_cycle_delay(struct aspeed_jtag *aspeed_jtag) +{ + int i = 0; + + for (i = 0; i < aspeed_jtag->tck_cycle_delay_count; i++) + ndelay(aspeed_jtag->tck_period >> 1); +} + +static int aspeed_jtag_mode_set(struct jtag *jtag, struct jtag_mode *jtag_mode) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + switch (jtag_mode->feature) { + case JTAG_XFER_MODE: + aspeed_jtag->mode = jtag_mode->mode; + aspeed_jtag->llops->controller_enable(aspeed_jtag); + break; + case JTAG_CONTROL_MODE: + if (jtag_mode->mode == JTAG_CONTROLLER_OUTPUT_DISABLE) + aspeed_jtag->llops->output_disable(aspeed_jtag); + else if (jtag_mode->mode == JTAG_CONTROLLER_MODE) + aspeed_jtag->llops->controller_enable(aspeed_jtag); + break; + case JTAG_TCK_CYCLE_DELAY_COUNT: + aspeed_jtag->tck_cycle_delay_count = jtag_mode->mode; + break; + default: + return -EINVAL; + } + return 0; +} + +/* + * We read and write from an unused JTAG controller register in SW mode to + * create a delay in xfers. + * We found this mechanism better than any udelay or usleep option. + */ +static inline void aspeed_jtag_sw_delay_26xx(struct aspeed_jtag *aspeed_jtag) +{ + u32 read_reg = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_PADCTRL1); + + aspeed_jtag_write(aspeed_jtag, read_reg, ASPEED_JTAG_PADCTRL1); +} + +static char aspeed_jtag_tck_cycle(struct aspeed_jtag *aspeed_jtag, u8 tms, + u8 tdi) +{ + char tdo = 0; + + /* TCK = 0 */ + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_SW_MODE_EN | + (tms * ASPEED_JTAG_SW_MODE_TMS) | + (tdi * ASPEED_JTAG_SW_MODE_TDIO), + ASPEED_JTAG_SW); + + /* Wait until JTAG controller finishes the operation */ + if (aspeed_jtag->llops->xfer_sw_delay) + aspeed_jtag->llops->xfer_sw_delay(aspeed_jtag); + else + aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW); + + if (aspeed_jtag->llops->xfer_tck_cycle_delay && + aspeed_jtag->tck_cycle_delay_count) + aspeed_jtag->llops->xfer_tck_cycle_delay(aspeed_jtag); + + /* TCK = 1 */ + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_SW_MODE_EN | ASPEED_JTAG_SW_MODE_TCK | + (tms * ASPEED_JTAG_SW_MODE_TMS) | + (tdi * ASPEED_JTAG_SW_MODE_TDIO), + ASPEED_JTAG_SW); + + /* Wait until JTAG controller finishes the operation */ + if (aspeed_jtag->llops->xfer_sw_delay) + aspeed_jtag->llops->xfer_sw_delay(aspeed_jtag); + + if (aspeed_jtag->llops->xfer_tck_cycle_delay && + aspeed_jtag->tck_cycle_delay_count) + aspeed_jtag->llops->xfer_tck_cycle_delay(aspeed_jtag); + + if (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_SW) & + ASPEED_JTAG_SW_MODE_TDIO) + tdo = 1; + + return tdo; +} + +static int aspeed_jtag_bitbang(struct jtag *jtag, + struct bitbang_packet *bitbang, + struct tck_bitbang *bitbang_data) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + int i = 0; + + for (i = 0; i < bitbang->length; i++) { + bitbang_data[i].tdo = + aspeed_jtag_tck_cycle(aspeed_jtag, bitbang_data[i].tms, + bitbang_data[i].tdi); + } + return 0; +} + +static inline void aspeed_jtag_xfer_hw_fifo_delay_26xx(void) +{ + udelay(AST26XX_FIFO_UDELAY); +} + +static int aspeed_jtag_isr_wait(struct aspeed_jtag *aspeed_jtag, u32 bit) +{ + int res = 0; +#ifdef CONFIG_USE_INTERRUPTS + res = wait_event_interruptible(aspeed_jtag->jtag_wq, + aspeed_jtag->flag & bit); + aspeed_jtag->flag &= ~bit; +#else + u32 status = 0; + u32 iterations = 0; + + while ((status & bit) == 0) { + status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR); +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "%s = 0x%08x\n", __func__, status); +#endif + iterations++; + if (iterations > WAIT_ITERATIONS) { + dev_err(aspeed_jtag->dev, "%s %d in ASPEED_JTAG_ISR\n", + "aspeed_jtag driver timed out waiting for bit", + bit); + res = -EFAULT; + break; + } + if ((status & ASPEED_JTAG_ISR_DATA_COMPLETE) == 0) { + if (iterations % 25 == 0) + usleep_range(1, 5); + else + udelay(1); + } + } + aspeed_jtag_write(aspeed_jtag, bit | (status & 0xf), ASPEED_JTAG_ISR); +#endif + return res; +} + +static int aspeed_jtag_wait_shift_complete(struct aspeed_jtag *aspeed_jtag) +{ + int res = 0; +#ifdef CONFIG_USE_INTERRUPTS + res = wait_event_interruptible(aspeed_jtag->jtag_wq, + aspeed_jtag->flag & + ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT); + aspeed_jtag->flag &= ~ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT; +#else + u32 status = 0; + u32 iterations = 0; + + while ((status & ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT) == 0) { + status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_INTCTRL); +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "%s = 0x%08x\n", __func__, status); +#endif + iterations++; + if (iterations > WAIT_ITERATIONS) { + dev_err(aspeed_jtag->dev, + "aspeed_jtag driver timed out waiting for shift completed\n"); + res = -EFAULT; + break; + } + if (iterations % 25 == 0) + usleep_range(1, 5); + else + udelay(1); + } + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT | + ASPEED_JTAG_INTCTRL_SHCPL_IRQ_EN, + ASPEED_JTAG_INTCTRL); +#endif + return res; +} + +static void aspeed_jtag_set_tap_state(struct aspeed_jtag *aspeed_jtag, + enum jtag_tapstate from_state, + enum jtag_tapstate end_state) +{ + int i = 0; + enum jtag_tapstate from, to; + + from = from_state; + to = end_state; + + if (from == JTAG_STATE_CURRENT) + from = aspeed_jtag->current_state; + + for (i = 0; i < _tms_cycle_lookup[from][to].count; i++) + aspeed_jtag_tck_cycle(aspeed_jtag, + ((_tms_cycle_lookup[from][to].tmsbits + >> i) & 0x1), 0); + aspeed_jtag->current_state = end_state; +} + +static void aspeed_jtag_set_tap_state_sw(struct aspeed_jtag *aspeed_jtag, + struct jtag_tap_state *tapstate) +{ + int i; + + /* SW mode from curent tap state -> to end_state */ + if (tapstate->reset || tapstate->endstate == JTAG_STATE_TLRESET) { + for (i = 0; i < ASPEED_JTAG_RESET_CNTR; i++) + aspeed_jtag_tck_cycle(aspeed_jtag, 1, 0); + aspeed_jtag->current_state = JTAG_STATE_TLRESET; + } + + aspeed_jtag_set_tap_state(aspeed_jtag, tapstate->from, + tapstate->endstate); + if (tapstate->endstate == JTAG_STATE_TLRESET || + tapstate->endstate == JTAG_STATE_IDLE || + tapstate->endstate == JTAG_STATE_PAUSEDR || + tapstate->endstate == JTAG_STATE_PAUSEIR) + for (i = 0; i < tapstate->tck; i++) + aspeed_jtag_tck_cycle(aspeed_jtag, 0, 0); +} + +static int aspeed_jtag_status_set(struct jtag *jtag, + struct jtag_tap_state *tapstate) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + int i; + +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "Set TAP state: %s\n", + end_status_str[tapstate->endstate]); +#endif + + if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) { + aspeed_jtag_set_tap_state_sw(aspeed_jtag, tapstate); + return 0; + } + + /* x TMS high + 1 TMS low */ + if (tapstate->reset) { + /* Disable sw mode */ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW); + mdelay(1); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_CTL_ENG_EN | + ASPEED_JTAG_CTL_ENG_OUT_EN | + ASPEED_JTAG_CTL_FORCE_TMS, + ASPEED_JTAG_CTRL); + mdelay(1); + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, + ASPEED_JTAG_SW); + aspeed_jtag->current_state = JTAG_STATE_TLRESET; + } + for (i = 0; i < tapstate->tck; i++) + ndelay(aspeed_jtag->tck_period); + + return 0; +} + +static int aspeed_jtag_shctrl_tms_mask(enum jtag_tapstate from, + enum jtag_tapstate to, + enum jtag_tapstate there, + enum jtag_tapstate endstate, + u32 start_shift, u32 end_shift, + u32 *tms_mask) +{ + u32 pre_tms = start_shift ? _tms_cycle_lookup[from][to].count : 0; + u32 post_tms = end_shift ? _tms_cycle_lookup[there][endstate].count : 0; + u32 tms_value = start_shift ? _tms_cycle_lookup[from][to].tmsbits : 0; + + tms_value |= end_shift ? _tms_cycle_lookup[there][endstate].tmsbits + << pre_tms : + 0; + if (pre_tms > GENMASK(2, 0) || post_tms > GENMASK(2, 0)) { + pr_err("pre/port tms count is greater than hw limit"); + return -EINVAL; + } + *tms_mask = start_shift | ASPEED_JTAG_SHCTRL_PRE_TMS(pre_tms) | + end_shift | ASPEED_JTAG_SHCTRL_POST_TMS(post_tms) | + ASPEED_JTAG_SHCTRL_TMS(tms_value); + return 0; +} + +static void aspeed_jtag_set_tap_state_hw2(struct aspeed_jtag *aspeed_jtag, + struct jtag_tap_state *tapstate) +{ + u32 reg_val; + + /* x TMS high + 1 TMS low */ + if (tapstate->reset || tapstate->endstate == JTAG_STATE_TLRESET) { + /* Disable sw mode */ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW); + udelay(AST26XX_JTAG_CTRL_UDELAY); + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + aspeed_jtag_write(aspeed_jtag, + reg_val | ASPEED_JTAG_GBLCTRL_ENG_MODE_EN | + ASPEED_JTAG_GBLCTRL_ENG_OUT_EN | + ASPEED_JTAG_GBLCTRL_RESET_FIFO | + ASPEED_JTAG_GBLCTRL_FORCE_TMS, + ASPEED_JTAG_GBLCTRL); + udelay(AST26XX_JTAG_CTRL_UDELAY); + while (aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL) & + ASPEED_JTAG_GBLCTRL_FORCE_TMS) + ; + aspeed_jtag->current_state = JTAG_STATE_TLRESET; + } else if (tapstate->endstate == JTAG_STATE_IDLE && + aspeed_jtag->current_state != JTAG_STATE_IDLE) { + /* Always go to RTI, do not wait for shift operation */ + aspeed_jtag_set_tap_state(aspeed_jtag, + aspeed_jtag->current_state, + JTAG_STATE_IDLE); + aspeed_jtag->current_state = JTAG_STATE_IDLE; + } + /* Run TCK */ + if (tapstate->tck) { + /* Disable sw mode */ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW); + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_PADCTRL0); + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + reg_val = reg_val & ~(GENMASK(22, 20)); + aspeed_jtag_write(aspeed_jtag, + reg_val | ASPEED_JTAG_GBLCTRL_FIFO_CTRL_MODE | + ASPEED_JTAG_GBLCTRL_STSHIFT(0) | + ASPEED_JTAG_GBLCTRL_UPDT_SHIFT(tapstate->tck), + ASPEED_JTAG_GBLCTRL); + + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_SHCTRL_STSHIFT_EN | + ASPEED_JTAG_SHCTRL_LWRDT_SHIFT(tapstate->tck), + ASPEED_JTAG_SHCTRL); + aspeed_jtag_wait_shift_complete(aspeed_jtag); + } +} + +static int aspeed_jtag_status_set_26xx(struct jtag *jtag, + struct jtag_tap_state *tapstate) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "Set TAP state: status %s from %s to %s\n", + end_status_str[aspeed_jtag->current_state], + end_status_str[tapstate->from], + end_status_str[tapstate->endstate]); +#endif + + if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) { + aspeed_jtag_set_tap_state_sw(aspeed_jtag, tapstate); + return 0; + } + + aspeed_jtag_set_tap_state_hw2(aspeed_jtag, tapstate); + return 0; +} + +static void aspeed_jtag_xfer_sw(struct aspeed_jtag *aspeed_jtag, + struct jtag_xfer *xfer, u32 *data) +{ + unsigned long remain_xfer = xfer->length; + unsigned long shift_bits = 0; + unsigned long index = 0; + unsigned long tdi; + char tdo; + +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "SW JTAG SHIFT %s, length = %d\n", + (xfer->type == JTAG_SIR_XFER) ? "IR" : "DR", xfer->length); +#endif + + if (xfer->type == JTAG_SIR_XFER) + aspeed_jtag_set_tap_state(aspeed_jtag, xfer->from, + JTAG_STATE_SHIFTIR); + else + aspeed_jtag_set_tap_state(aspeed_jtag, xfer->from, + JTAG_STATE_SHIFTDR); + + tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]); + data[index] = 0; + while (remain_xfer > 1) { + tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0, + tdi & ASPEED_JTAG_DATA_MSB); + data[index] |= tdo + << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE); + tdi >>= 1; + shift_bits++; + remain_xfer--; + + if (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE == 0) { + tdo = 0; + index++; + tdi = ASPEED_JTAG_GET_TDI(xfer->direction, data[index]); + data[index] = 0; + } + } + + if ((xfer->endstate == (xfer->type == JTAG_SIR_XFER ? + JTAG_STATE_SHIFTIR : + JTAG_STATE_SHIFTDR))) { + /* Stay in Shift IR/DR*/ + tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 0, + tdi & ASPEED_JTAG_DATA_MSB); + data[index] |= tdo + << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE); + } else { + /* Goto end state */ + tdo = aspeed_jtag_tck_cycle(aspeed_jtag, 1, + tdi & ASPEED_JTAG_DATA_MSB); + data[index] |= tdo + << (shift_bits % ASPEED_JTAG_DATA_CHUNK_SIZE); + aspeed_jtag->status = (xfer->type == JTAG_SIR_XFER) ? + JTAG_STATE_EXIT1IR : + JTAG_STATE_EXIT1DR; + aspeed_jtag_set_tap_state(aspeed_jtag, aspeed_jtag->status, + xfer->endstate); + } +} + +static int aspeed_jtag_xfer_push_data_26xx(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, + u32 bits_len) +{ + int res = 0; + + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_TRANS_LEN(bits_len), + ASPEED_JTAG_CTRL); + if (type == JTAG_SIR_XFER) { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_TRANS_LEN(bits_len) | + ASPEED_JTAG_CTL_26XX_INST_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_INST_PAUSE); + } else { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_TRANS_LEN(bits_len) | + ASPEED_JTAG_CTL_DATA_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_DATA_PAUSE); + } + return res; +} + +static int aspeed_jtag_xfer_push_data(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, u32 bits_len) +{ + int res = 0; + + if (type == JTAG_SIR_XFER) { + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_IOUT_LEN(bits_len), + ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_IOUT_LEN(bits_len) | + ASPEED_JTAG_CTL_INST_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_INST_PAUSE); + } else { + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_DOUT_LEN(bits_len), + ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_DOUT_LEN(bits_len) | + ASPEED_JTAG_CTL_DATA_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_DATA_PAUSE); + } + return res; +} + +static int aspeed_jtag_xfer_push_data_last_26xx(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, + u32 shift_bits) +{ + int res = 0; + + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_TRANS_LEN(shift_bits) | + ASPEED_JTAG_CTL_26XX_LASPEED_TRANS, + ASPEED_JTAG_CTRL); + if (type == JTAG_SIR_XFER) { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_TRANS_LEN(shift_bits) | + ASPEED_JTAG_CTL_26XX_LASPEED_TRANS | + ASPEED_JTAG_CTL_26XX_INST_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_INST_COMPLETE); + } else { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_TRANS_LEN(shift_bits) | + ASPEED_JTAG_CTL_26XX_LASPEED_TRANS | + ASPEED_JTAG_CTL_DATA_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_DATA_COMPLETE); + } + return res; +} + +static int aspeed_jtag_xfer_push_data_last(struct aspeed_jtag *aspeed_jtag, + enum jtag_xfer_type type, + u32 shift_bits) +{ + int res = 0; + + if (type == JTAG_SIR_XFER) { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_IOUT_LEN(shift_bits) | + ASPEED_JTAG_CTL_LASPEED_INST, + ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_IOUT_LEN(shift_bits) | + ASPEED_JTAG_CTL_LASPEED_INST | + ASPEED_JTAG_CTL_INST_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_INST_COMPLETE); + } else { + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_DOUT_LEN(shift_bits) | + ASPEED_JTAG_CTL_LASPEED_DATA, + ASPEED_JTAG_CTRL); + aspeed_jtag_write(aspeed_jtag, + ASPEED_JTAG_DOUT_LEN(shift_bits) | + ASPEED_JTAG_CTL_LASPEED_DATA | + ASPEED_JTAG_CTL_DATA_EN, + ASPEED_JTAG_CTRL); + res = aspeed_jtag_isr_wait(aspeed_jtag, + ASPEED_JTAG_ISR_DATA_COMPLETE); + } + return res; +} + +static int aspeed_jtag_xfer_hw(struct aspeed_jtag *aspeed_jtag, + struct jtag_xfer *xfer, u32 *data) +{ + unsigned long remain_xfer = xfer->length; + unsigned long index = 0; + char shift_bits; + u32 data_reg; + u32 scan_end; + union pad_config padding; + int retval = 0; + + padding.int_value = xfer->padding; + +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, "HW JTAG SHIFT %s, length = %d pad = 0x%x\n", + (xfer->type == JTAG_SIR_XFER) ? "IR" : "DR", xfer->length, + xfer->padding); +#endif + data_reg = xfer->type == JTAG_SIR_XFER ? ASPEED_JTAG_INST : + ASPEED_JTAG_DATA; + if (xfer->endstate == JTAG_STATE_SHIFTIR || + xfer->endstate == JTAG_STATE_SHIFTDR || + xfer->endstate == JTAG_STATE_PAUSEIR || + xfer->endstate == JTAG_STATE_PAUSEDR) { + scan_end = 0; + } else { + if (padding.post_pad_number) + scan_end = 0; + else + scan_end = 1; + } + + /* Perform pre padding */ + if (padding.pre_pad_number) { + struct jtag_xfer pre_xfer = { + .type = xfer->type, + .direction = JTAG_WRITE_XFER, + .from = xfer->from, + .endstate = xfer->type == JTAG_SIR_XFER ? + JTAG_STATE_SHIFTIR : JTAG_STATE_SHIFTDR, + .padding = 0, + .length = padding.pre_pad_number, + }; + if (padding.pre_pad_number > ASPEED_JTAG_MAX_PAD_SIZE) + return -EINVAL; + retval = aspeed_jtag_xfer_hw(aspeed_jtag, &pre_xfer, + padding.pad_data ? + aspeed_jtag->pad_data_one : + aspeed_jtag->pad_data_zero); + if (retval) + return retval; + } + + while (remain_xfer) { + if (xfer->direction & JTAG_WRITE_XFER) + aspeed_jtag_write(aspeed_jtag, data[index], data_reg); + else + aspeed_jtag_write(aspeed_jtag, 0, data_reg); + if (aspeed_jtag->llops->xfer_hw_fifo_delay) + aspeed_jtag->llops->xfer_hw_fifo_delay(); + + if (remain_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) { +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, + "Chunk len=%d chunk_size=%d remain_xfer=%lu\n", + xfer->length, ASPEED_JTAG_DATA_CHUNK_SIZE, + remain_xfer); +#endif + shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE; + + /* + * Transmit bytes that were not equals to column length + * and after the transfer go to Pause IR/DR. + */ + if (aspeed_jtag->llops->xfer_push_data(aspeed_jtag, + xfer->type, + shift_bits) + != 0) { + return -EFAULT; + } + } else { + /* + * Read bytes equals to column length + */ + shift_bits = remain_xfer; + if (scan_end) { + /* + * If this data is the end of the transmission + * send remaining bits and go to endstate + */ +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, + "Last len=%d chunk_size=%d remain_xfer=%lu\n", + xfer->length, + ASPEED_JTAG_DATA_CHUNK_SIZE, + remain_xfer); +#endif + if (aspeed_jtag->llops->xfer_push_data_last( + aspeed_jtag, xfer->type, + shift_bits) != 0) { + return -EFAULT; + } + } else { + /* + * If transmission is waiting for additional + * data send remaining bits and then go to + * Pause IR/DR. + */ +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, + "Tail len=%d chunk_size=%d remain_xfer=%lu\n", + xfer->length, + ASPEED_JTAG_DATA_CHUNK_SIZE, + remain_xfer); +#endif + if (aspeed_jtag->llops->xfer_push_data( + aspeed_jtag, xfer->type, + shift_bits) != 0) { + return -EFAULT; + } + } + } + + if (xfer->direction & JTAG_READ_XFER) { + if (shift_bits < ASPEED_JTAG_DATA_CHUNK_SIZE) { + data[index] = + aspeed_jtag_read(aspeed_jtag, data_reg); + + data[index] >>= ASPEED_JTAG_DATA_CHUNK_SIZE - + shift_bits; + } else { + data[index] = + aspeed_jtag_read(aspeed_jtag, data_reg); + } + if (aspeed_jtag->llops->xfer_hw_fifo_delay) + aspeed_jtag->llops->xfer_hw_fifo_delay(); + } + + remain_xfer = remain_xfer - shift_bits; + index++; + } + + /* Perform post padding */ + if (padding.post_pad_number) { + struct jtag_xfer post_xfer = { + .type = xfer->type, + .direction = JTAG_WRITE_XFER, + .from = xfer->from, + .endstate = xfer->endstate, + .padding = 0, + .length = padding.post_pad_number, + }; + if (padding.post_pad_number > ASPEED_JTAG_MAX_PAD_SIZE) + return -EINVAL; + retval = aspeed_jtag_xfer_hw(aspeed_jtag, &post_xfer, + padding.pad_data ? + aspeed_jtag->pad_data_one : + aspeed_jtag->pad_data_zero); + if (retval) + return retval; + } + return 0; +} + +static int aspeed_jtag_xfer(struct jtag *jtag, struct jtag_xfer *xfer, + u8 *xfer_data) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + if (!(aspeed_jtag->mode & JTAG_XFER_HW_MODE)) { + /* SW mode */ + aspeed_jtag_write(aspeed_jtag, ASPEED_JTAG_SW_TDIO, + ASPEED_JTAG_SW); + + aspeed_jtag->llops->xfer_sw(aspeed_jtag, xfer, + (u32 *)xfer_data); + } else { + /* HW mode */ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_SW); + if (aspeed_jtag->llops->xfer_hw(aspeed_jtag, xfer, + (u32 *)xfer_data) != 0) + return -EFAULT; + } + + aspeed_jtag->status = xfer->endstate; + return 0; +} + +static int aspeed_jtag_xfer_hw2(struct aspeed_jtag *aspeed_jtag, + struct jtag_xfer *xfer, u32 *data) +{ + unsigned long remain_xfer = xfer->length; + unsigned long partial_xfer_size = 0; + unsigned long index = 0; + u32 shift_bits; + u32 data_reg; + u32 reg_val; + enum jtag_tapstate shift; + enum jtag_tapstate exit; + enum jtag_tapstate exitx; + enum jtag_tapstate pause; + enum jtag_tapstate endstate; + u32 start_shift; + u32 end_shift; + u32 tms_mask; + int ret; + + if (xfer->type == JTAG_SIR_XFER) { + data_reg = ASPEED_JTAG_SHDATA; + shift = JTAG_STATE_SHIFTIR; + pause = JTAG_STATE_PAUSEIR; + exit = JTAG_STATE_EXIT1IR; + exitx = JTAG_STATE_EXIT1DR; + } else { + data_reg = ASPEED_JTAG_SHDATA; + shift = JTAG_STATE_SHIFTDR; + pause = JTAG_STATE_PAUSEDR; + exit = JTAG_STATE_EXIT1DR; + exitx = JTAG_STATE_EXIT1IR; + } +#ifdef DEBUG_JTAG + dev_dbg(aspeed_jtag->dev, + "HW2 JTAG SHIFT %s, length %d status %s from %s to %s then %s pad 0x%x\n", + (xfer->type == JTAG_SIR_XFER) ? "IR" : "DR", xfer->length, + end_status_str[aspeed_jtag->current_state], + end_status_str[xfer->from], + end_status_str[shift], + end_status_str[xfer->endstate], xfer->padding); +#endif + + if (aspeed_jtag->current_state == shift) + start_shift = 0; + else + start_shift = ASPEED_JTAG_SHCTRL_START_SHIFT; + + if (xfer->endstate == shift) { + /* + * In the case of shifting 1 bit of data and attempting to stay + * in the SHIFT state, the AST2600 JTAG Controller in Hardware + * mode 2 has been observed to go to EXIT1 IR/DR instead of + * staying in the SHIFT IR/DR state. The following code special + * cases this one bit shift and directs the state machine to go + * to the PAUSE IR/DR state instead. + * Alternatively, the application making driver calls can avoid + * this situation as follows: + * 1.) Bundle all of the shift bits together into one call + * AND/OR + * 2.) Direct all partial shifts to move to the PAUSE-IR/DR + * state. + */ + if (xfer->length == 1) { +#ifdef DEBUG_JTAG + dev_warn(aspeed_jtag->dev, "JTAG Silicon WA: going to pause instead of shift"); +#endif + end_shift = ASPEED_JTAG_SHCTRL_END_SHIFT; + endstate = pause; + } else { + end_shift = 0; + endstate = shift; + } + } else { + endstate = xfer->endstate; + end_shift = ASPEED_JTAG_SHCTRL_END_SHIFT; + } + + aspeed_jtag_write(aspeed_jtag, xfer->padding, ASPEED_JTAG_PADCTRL0); + + while (remain_xfer) { + unsigned long partial_xfer; + unsigned long partial_index; + + if (remain_xfer > ASPEED_JTAG_HW2_DATA_CHUNK_SIZE) + partial_xfer_size = ASPEED_JTAG_HW2_DATA_CHUNK_SIZE; + else + partial_xfer_size = remain_xfer; + + partial_index = index; + partial_xfer = partial_xfer_size; + + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + aspeed_jtag_write(aspeed_jtag, reg_val | + ASPEED_JTAG_GBLCTRL_RESET_FIFO, + ASPEED_JTAG_GBLCTRL); + + /* Switch internal FIFO into CPU mode */ + reg_val = reg_val & ~BIT(24); + aspeed_jtag_write(aspeed_jtag, reg_val, + ASPEED_JTAG_GBLCTRL); + + while (partial_xfer) { + if (partial_xfer > ASPEED_JTAG_DATA_CHUNK_SIZE) + shift_bits = ASPEED_JTAG_DATA_CHUNK_SIZE; + else + shift_bits = partial_xfer; + + if (xfer->direction & JTAG_WRITE_XFER) + aspeed_jtag_write(aspeed_jtag, + data[partial_index++], + data_reg); + else + aspeed_jtag_write(aspeed_jtag, 0, data_reg); + if (aspeed_jtag->llops->xfer_hw_fifo_delay) + aspeed_jtag->llops->xfer_hw_fifo_delay(); + partial_xfer = partial_xfer - shift_bits; + } + if (remain_xfer > ASPEED_JTAG_HW2_DATA_CHUNK_SIZE) { + shift_bits = ASPEED_JTAG_HW2_DATA_CHUNK_SIZE; + + /* + * Transmit bytes that were not equals to column length + * and after the transfer go to Pause IR/DR. + */ + + ret = aspeed_jtag_shctrl_tms_mask(aspeed_jtag->current_state, shift, exit, + endstate, start_shift, 0, &tms_mask); + if (ret) + return ret; + + reg_val = aspeed_jtag_read(aspeed_jtag, + ASPEED_JTAG_GBLCTRL); + reg_val = reg_val & ~(GENMASK(22, 20)); + aspeed_jtag_write(aspeed_jtag, reg_val | + ASPEED_JTAG_GBLCTRL_FIFO_CTRL_MODE | + ASPEED_JTAG_GBLCTRL_UPDT_SHIFT( + shift_bits), + ASPEED_JTAG_GBLCTRL); + + aspeed_jtag_write(aspeed_jtag, tms_mask | + ASPEED_JTAG_SHCTRL_LWRDT_SHIFT(shift_bits), + ASPEED_JTAG_SHCTRL); + aspeed_jtag_wait_shift_complete(aspeed_jtag); + } else { + /* + * Read bytes equals to column length + */ + shift_bits = remain_xfer; + ret = aspeed_jtag_shctrl_tms_mask(aspeed_jtag->current_state, shift, exit, + endstate, start_shift, end_shift, + &tms_mask); + if (ret) + return ret; + + reg_val = aspeed_jtag_read(aspeed_jtag, + ASPEED_JTAG_GBLCTRL); + reg_val = reg_val & ~(GENMASK(22, 20)); + aspeed_jtag_write(aspeed_jtag, reg_val | + ASPEED_JTAG_GBLCTRL_FIFO_CTRL_MODE | + ASPEED_JTAG_GBLCTRL_UPDT_SHIFT( + shift_bits), + ASPEED_JTAG_GBLCTRL); + + aspeed_jtag_write(aspeed_jtag, tms_mask | + ASPEED_JTAG_SHCTRL_LWRDT_SHIFT( + shift_bits), + ASPEED_JTAG_SHCTRL); + + aspeed_jtag_wait_shift_complete(aspeed_jtag); + } + + partial_index = index; + partial_xfer = partial_xfer_size; + while (partial_xfer) { + if (partial_xfer > + ASPEED_JTAG_DATA_CHUNK_SIZE) { + shift_bits = + ASPEED_JTAG_DATA_CHUNK_SIZE; + data[partial_index++] = + aspeed_jtag_read(aspeed_jtag, + data_reg); + + } else { + shift_bits = partial_xfer; + data[partial_index++] = + aspeed_jtag_read(aspeed_jtag, + data_reg); + } + if (aspeed_jtag->llops->xfer_hw_fifo_delay) + aspeed_jtag->llops->xfer_hw_fifo_delay(); + partial_xfer = partial_xfer - shift_bits; + } + + remain_xfer = remain_xfer - partial_xfer_size; + index = partial_index; + start_shift = 0; + } + aspeed_jtag->current_state = endstate; + return 0; +} + +static int aspeed_jtag_status_get(struct jtag *jtag, u32 *status) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + *status = aspeed_jtag->current_state; + return 0; +} + +static irqreturn_t aspeed_jtag_interrupt(s32 this_irq, void *dev_id) +{ + struct aspeed_jtag *aspeed_jtag = dev_id; + irqreturn_t ret; + u32 status; + + status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_ISR); + + if (status & ASPEED_JTAG_ISR_INT_MASK) { + aspeed_jtag_write(aspeed_jtag, + (status & ASPEED_JTAG_ISR_INT_MASK) | + (status & + ASPEED_JTAG_ISR_INT_EN_MASK), + ASPEED_JTAG_ISR); + aspeed_jtag->flag |= status & ASPEED_JTAG_ISR_INT_MASK; + } + + if (aspeed_jtag->flag) { + wake_up_interruptible(&aspeed_jtag->jtag_wq); + ret = IRQ_HANDLED; + } else { + dev_err(aspeed_jtag->dev, "irq status:%x\n", status); + ret = IRQ_NONE; + } + return ret; +} + +static irqreturn_t aspeed_jtag_interrupt_hw2(s32 this_irq, void *dev_id) +{ + struct aspeed_jtag *aspeed_jtag = dev_id; + irqreturn_t ret; + u32 status; + + status = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_INTCTRL); + + if (status & ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT) { + aspeed_jtag_write(aspeed_jtag, + status | ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT, + ASPEED_JTAG_INTCTRL); + aspeed_jtag->flag |= status & ASPEED_JTAG_INTCTRL_SHCPL_IRQ_STAT; + } + + if (aspeed_jtag->flag) { + wake_up_interruptible(&aspeed_jtag->jtag_wq); + ret = IRQ_HANDLED; + } else { + dev_err(aspeed_jtag->dev, "irq status:%x\n", status); + ret = IRQ_NONE; + } + return ret; +} + +static int aspeed_jtag_enable(struct jtag *jtag) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + aspeed_jtag->llops->controller_enable(aspeed_jtag); + return 0; +} + +static int aspeed_jtag_disable(struct jtag *jtag) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + aspeed_jtag->llops->output_disable(aspeed_jtag); + return 0; +} + +static int aspeed_jtag_init(struct platform_device *pdev, + struct aspeed_jtag *aspeed_jtag) +{ + struct resource *res; +#ifdef CONFIG_USE_INTERRUPTS + int err; +#endif + memset(aspeed_jtag->pad_data_one, ~0, + sizeof(aspeed_jtag->pad_data_one)); + memset(aspeed_jtag->pad_data_zero, 0, + sizeof(aspeed_jtag->pad_data_zero)); + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + aspeed_jtag->reg_base = devm_ioremap_resource(aspeed_jtag->dev, res); + if (IS_ERR(aspeed_jtag->reg_base)) + return -ENOMEM; + + aspeed_jtag->pclk = devm_clk_get(aspeed_jtag->dev, NULL); + if (IS_ERR(aspeed_jtag->pclk)) { + dev_err(aspeed_jtag->dev, "devm_clk_get failed\n"); + return PTR_ERR(aspeed_jtag->pclk); + } + +#ifdef CONFIG_USE_INTERRUPTS + aspeed_jtag->irq = platform_get_irq(pdev, 0); + if (aspeed_jtag->irq < 0) { + dev_err(aspeed_jtag->dev, "no irq specified\n"); + return -ENOENT; + } +#endif + + if (clk_prepare_enable(aspeed_jtag->pclk)) { + dev_err(aspeed_jtag->dev, "no irq specified\n"); + return -ENOENT; + } + + aspeed_jtag->rst = devm_reset_control_get_shared(&pdev->dev, NULL); + if (IS_ERR(aspeed_jtag->rst)) { + dev_err(aspeed_jtag->dev, + "missing or invalid reset controller device tree entry"); + return PTR_ERR(aspeed_jtag->rst); + } + reset_control_deassert(aspeed_jtag->rst); + +#ifdef CONFIG_USE_INTERRUPTS + err = devm_request_irq(aspeed_jtag->dev, aspeed_jtag->irq, + aspeed_jtag->llops->jtag_interrupt, 0, + "aspeed-jtag", aspeed_jtag); + if (err) { + dev_err(aspeed_jtag->dev, "unable to get IRQ"); + clk_disable_unprepare(aspeed_jtag->pclk); + return err; + } +#endif + + aspeed_jtag->llops->output_disable(aspeed_jtag); + + aspeed_jtag->flag = 0; + aspeed_jtag->mode = 0; + aspeed_jtag->tck_cycle_delay_count = 0; + init_waitqueue_head(&aspeed_jtag->jtag_wq); + return 0; +} + +static int aspeed_jtag_deinit(struct platform_device *pdev, + struct aspeed_jtag *aspeed_jtag) +{ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_ISR); + /* Disable clock */ + aspeed_jtag_write(aspeed_jtag, 0, ASPEED_JTAG_CTRL); + reset_control_assert(aspeed_jtag->rst); + clk_disable_unprepare(aspeed_jtag->pclk); + return 0; +} + +static int aspeed_jtag_trst_set_hw1(struct jtag *jtag, u32 active) +{ + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + aspeed_jtag_write(aspeed_jtag, active ? 0 : ASPEED_JTAG_EC_TRST, + ASPEED_JTAG_EC); + return 0; +} + +static int aspeed_jtag_trst_set_hw2(struct jtag *jtag, u32 active) +{ + u32 reg_val; + struct aspeed_jtag *aspeed_jtag = jtag_priv(jtag); + + reg_val = aspeed_jtag_read(aspeed_jtag, ASPEED_JTAG_GBLCTRL); + if (active) + reg_val |= ASPEED_JTAG_GBLCTRL_TRST; + else + reg_val &= ~ASPEED_JTAG_GBLCTRL_TRST; + aspeed_jtag_write(aspeed_jtag, reg_val, ASPEED_JTAG_GBLCTRL); + return 0; +} + +static const struct jtag_ops aspeed_jtag_ops = { + .freq_get = aspeed_jtag_freq_get, + .freq_set = aspeed_jtag_freq_set, + .status_get = aspeed_jtag_status_get, + .status_set = aspeed_jtag_status_set, + .xfer = aspeed_jtag_xfer, + .mode_set = aspeed_jtag_mode_set, + .trst_set = aspeed_jtag_trst_set_hw1, + .bitbang = aspeed_jtag_bitbang, + .enable = aspeed_jtag_enable, + .disable = aspeed_jtag_disable +}; + +static const struct jtag_ops aspeed_jtag_ops_26xx = { +#ifdef ASPEED_JTAG_HW_MODE_2_ENABLE + .freq_get = aspeed_jtag_freq_get_26xx, + .freq_set = aspeed_jtag_freq_set_26xx, + .status_get = aspeed_jtag_status_get, + .status_set = aspeed_jtag_status_set_26xx, + .trst_set = aspeed_jtag_trst_set_hw2, +#else + .freq_get = aspeed_jtag_freq_get, + .freq_set = aspeed_jtag_freq_set, + .status_get = aspeed_jtag_status_get, + .status_set = aspeed_jtag_status_set, + .trst_set = aspeed_jtag_trst_set_hw1, +#endif + .xfer = aspeed_jtag_xfer, + .mode_set = aspeed_jtag_mode_set, + .bitbang = aspeed_jtag_bitbang, + .enable = aspeed_jtag_enable, + .disable = aspeed_jtag_disable +}; + +static const struct jtag_low_level_functions ast25xx_llops = { + .controller_enable = aspeed_jtag_controller, + .output_disable = aspeed_jtag_output_disable, + .xfer_push_data = aspeed_jtag_xfer_push_data, + .xfer_push_data_last = aspeed_jtag_xfer_push_data_last, + .xfer_sw = aspeed_jtag_xfer_sw, + .xfer_hw = aspeed_jtag_xfer_hw, + .xfer_hw_fifo_delay = NULL, + .xfer_sw_delay = NULL, + .xfer_tck_cycle_delay = aspeed_jtag_tck_cycle_delay, + .jtag_interrupt = aspeed_jtag_interrupt +}; + +static const struct aspeed_jtag_functions ast25xx_functions = { + .aspeed_jtag_ops = &aspeed_jtag_ops, + .aspeed_jtag_llops = &ast25xx_llops +}; + +static const struct jtag_low_level_functions ast26xx_llops = { +#ifdef ASPEED_JTAG_HW_MODE_2_ENABLE + .controller_enable = aspeed_jtag_controller_26xx, + .output_disable = aspeed_jtag_output_disable_26xx, + .xfer_push_data = aspeed_jtag_xfer_push_data_26xx, + .xfer_push_data_last = aspeed_jtag_xfer_push_data_last_26xx, + .xfer_sw = aspeed_jtag_xfer_sw, + .xfer_hw = aspeed_jtag_xfer_hw2, + .xfer_hw_fifo_delay = aspeed_jtag_xfer_hw_fifo_delay_26xx, + .xfer_sw_delay = aspeed_jtag_sw_delay_26xx, + .xfer_tck_cycle_delay = aspeed_jtag_tck_cycle_delay, + .jtag_interrupt = aspeed_jtag_interrupt_hw2 +#else + .controller_enable = aspeed_jtag_controller, + .output_disable = aspeed_jtag_output_disable, + .xfer_push_data = aspeed_jtag_xfer_push_data_26xx, + .xfer_push_data_last = aspeed_jtag_xfer_push_data_last_26xx, + .xfer_sw = aspeed_jtag_xfer_sw, + .xfer_hw = aspeed_jtag_xfer_hw, + .xfer_hw_fifo_delay = aspeed_jtag_xfer_hw_fifo_delay_26xx, + .xfer_sw_delay = aspeed_jtag_sw_delay_26xx, + .xfer_tck_cycle_delay = aspeed_jtag_tck_cycle_delay, + .jtag_interrupt = aspeed_jtag_interrupt +#endif +}; + +static const struct aspeed_jtag_functions ast26xx_functions = { + .aspeed_jtag_ops = &aspeed_jtag_ops_26xx, + .aspeed_jtag_llops = &ast26xx_llops +}; + +static const struct of_device_id aspeed_jtag_of_match[] = { + { .compatible = "aspeed,ast2400-jtag", .data = &ast25xx_functions }, + { .compatible = "aspeed,ast2500-jtag", .data = &ast25xx_functions }, + { .compatible = "aspeed,ast2600-jtag", .data = &ast26xx_functions }, + {} +}; + +static int aspeed_jtag_probe(struct platform_device *pdev) +{ + struct aspeed_jtag *aspeed_jtag; + struct jtag *jtag; + const struct of_device_id *match; + const struct aspeed_jtag_functions *jtag_functions; + int err; + + match = of_match_node(aspeed_jtag_of_match, pdev->dev.of_node); + if (!match) + return -ENODEV; + jtag_functions = match->data; + + jtag = jtag_alloc(&pdev->dev, sizeof(*aspeed_jtag), + jtag_functions->aspeed_jtag_ops); + if (!jtag) + return -ENOMEM; + + platform_set_drvdata(pdev, jtag); + aspeed_jtag = jtag_priv(jtag); + aspeed_jtag->dev = &pdev->dev; + + aspeed_jtag->llops = jtag_functions->aspeed_jtag_llops; + + /* Initialize device*/ + err = aspeed_jtag_init(pdev, aspeed_jtag); + if (err) + goto err_jtag_init; + + /* Initialize JTAG core structure*/ + err = devm_jtag_register(aspeed_jtag->dev, jtag); + if (err) + goto err_jtag_register; + + jtag_functions->aspeed_jtag_ops->freq_set(jtag, 1000000); + + return 0; + +err_jtag_register: + aspeed_jtag_deinit(pdev, aspeed_jtag); +err_jtag_init: + jtag_free(jtag); + return err; +} + +static int aspeed_jtag_remove(struct platform_device *pdev) +{ + struct jtag *jtag = platform_get_drvdata(pdev); + + aspeed_jtag_deinit(pdev, jtag_priv(jtag)); + return 0; +} + +static struct platform_driver aspeed_jtag_driver = { + .probe = aspeed_jtag_probe, + .remove = aspeed_jtag_remove, + .driver = { + .name = ASPEED_JTAG_NAME, + .of_match_table = aspeed_jtag_of_match, + }, +}; +module_platform_driver(aspeed_jtag_driver); + +MODULE_AUTHOR("Oleksandr Shamray "); +MODULE_DESCRIPTION("ASPEED JTAG driver"); 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Comments pointed by Paul Fertser - SRST added to documentation. - Remove call flow as it was confusing. - Replaced unsiged int for signed int on file descriptors. - Specify frq for SIOCFREQ and GIOCFREQ in Hertz. - Remvoed usleep that was not used on examples. - Documented padding. v28->v29 Comments pointed by Steven Filary - Expand bitbang function to accept multiples bitbang operations within a single JTAG_IOCBITBANG call. It will receive a buffer with TDI and TMS values and it is expected that driver fills TDO fields with its corresponding output value for every transaction. v27->v28 Comments pointed by Steven Filary - Replace JTAG_IOCRUNTEST with JTAG_SIOCSTATE adding support for all TAPC end states in SW mode using a lookup table to navigate across states. - Add support for simultaneous READ/WRITE transfers(JTAG_READ_WRITE_XFER). - Support for switching JTAG controller mode between target and host controller mode. - Setup JTAG controller mode to host controller only when the driver is opened, letting other HW to own the JTAG bus when it isn't in use. - Include JTAG bit bang IOCTL for low level JTAG control usage (JTAG_IOCBITBANG). v26->v27 v25->v26 Comments pointed by Randy Dunlap - fix spell in ABI documentation v24->v25 Comments pointed by Greg KH - Fixed documentation according to new open() behavior v23->v24 v22->v23 Comments pointed by Randy Dunlap - fix spell in ABI doccumentation v21->v22 Comments pointed by Randy Dunlap - fix spell in ABI doccumentation v20->v21 Comments pointed by Randy Dunlap - Fix JTAG dirver help in Kconfig v19->v20 Comments pointed by Randy Dunlap - Fix JTAG doccumentation v18->v19 Pavel Machek - Added JTAG doccumentation to Documentation/jtag v17->v18 v16->v17 v15->v16 v14->v15 v13->v14 v12->v13 v11->v12 Tobias Klauser Comments pointed by - rename /Documentation/ABI/testing/jatg-dev -> jtag-dev - Typo: s/interfase/interface v10->v11 v9->v10 Changes added by Oleksandr: - change jtag-cdev to jtag-dev in documentation - update KernelVersion and Date in jtag-dev documentation; v8->v9 v7->v8 v6->v7 Comments pointed by Pavel Machek - Added jtag-cdev documentation to Documentation/ABI/testing folder --- Documentation/ABI/testing/jtag-dev | 23 +++ Documentation/jtag/index.rst | 18 +++ Documentation/jtag/jtag-summary.rst | 49 ++++++ Documentation/jtag/jtagdev.rst | 222 ++++++++++++++++++++++++++++ 4 files changed, 312 insertions(+) create mode 100644 Documentation/ABI/testing/jtag-dev create mode 100644 Documentation/jtag/index.rst create mode 100644 Documentation/jtag/jtag-summary.rst create mode 100644 Documentation/jtag/jtagdev.rst diff --git a/Documentation/ABI/testing/jtag-dev b/Documentation/ABI/testing/jtag-dev new file mode 100644 index 000000000000..93821506d70e --- /dev/null +++ b/Documentation/ABI/testing/jtag-dev @@ -0,0 +1,23 @@ +What: /dev/jtag[0-9]+ +Date: July 2018 +KernelVersion: 4.20 +Contact: oleksandrs@mellanox.com +Description: + The misc device files /dev/jtag* are the interface + between JTAG controller interface and userspace. + + The ioctl(2)-based ABI is defined and documented in + [include/uapi]. + + The following file operations are supported: + + open(2) + Opens and allocates file descriptor. + + ioctl(2) + Initiate various actions. + See the inline documentation in [include/uapi] + for descriptions of all ioctls. + +Users: + userspace tools which wants to access to JTAG bus diff --git a/Documentation/jtag/index.rst b/Documentation/jtag/index.rst new file mode 100644 index 000000000000..8a2761d1c17e --- /dev/null +++ b/Documentation/jtag/index.rst @@ -0,0 +1,18 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================== +Joint Test Action Group (JTAG) +============================== + +.. toctree:: + :maxdepth: 1 + + jtag-summary + jtagdev + +.. only:: subproject and html + + Indices + ======= + + * :ref:`genindex` diff --git a/Documentation/jtag/jtag-summary.rst b/Documentation/jtag/jtag-summary.rst new file mode 100644 index 000000000000..07cfa7a761d7 --- /dev/null +++ b/Documentation/jtag/jtag-summary.rst @@ -0,0 +1,49 @@ +.. SPDX-License-Identifier: GPL-2.0 + +==================================== +Linux kernel JTAG support +==================================== + +Introduction to JTAG +==================== + +JTAG is an industry standard for verifying hardware. JTAG provides access to +many logic signals of a complex integrated circuit, including the device pins. + +A JTAG interface is a special interface added to a chip. +Depending on the version of JTAG, two, four, or five pins are added. + +The connector pins are: + * TDI (Test Data In) + * TDO (Test Data Out) + * TCK (Test Clock) + * TMS (Test Mode Select) + * TRST (Test Reset) optional + +JTAG interface is designed to have two parts - basic core driver and +hardware specific driver. The basic driver introduces a general interface +which is not dependent of specific hardware. It provides communication +between user space and hardware specific driver. +Each JTAG device is represented as a char device from (jtag0, jtag1, ...). +Access to a JTAG device is performed through IOCTL calls. + +Call flow example: +:: + + User: open -> /dev/jatgX -> JTAG core driver -> JTAG hardware specific driver + User: ioctl -> /dev/jtagX -> JTAG core driver -> JTAG hardware specific driver + User: close -> /dev/jatgX -> JTAG core driver -> JTAG hardware specific driver + + +THANKS TO +--------- +Contributors to Linux-JTAG discussions include (in alphabetical order, +by last name): + +- Omar Castro +- Ernesto Corona +- Steven Filary +- Vadim Pasternak +- Jiri Pirko +- Oleksandr Shamray +- Billy Tsai \ No newline at end of file diff --git a/Documentation/jtag/jtagdev.rst b/Documentation/jtag/jtagdev.rst new file mode 100644 index 000000000000..883df46ec117 --- /dev/null +++ b/Documentation/jtag/jtagdev.rst @@ -0,0 +1,222 @@ +.. SPDX-License-Identifier: GPL-2.0 + +================== +JTAG userspace API +================== +JTAG controller devices can be accessed through a character misc-device. + +Each JTAG controller interface can be accessed by using /dev/jtagN. + +JTAG system calls set: + * SIR (Scan Instruction Register, IEEE 1149.1 Instruction Register scan); + * SDR (Scan Data Register, IEEE 1149.1 Data Register scan); + * RUNTEST (Forces the IEEE 1149.1 bus to a run state for a specified number of clocks. + +open(), close() +--------------- +Open/Close device: +:: + + jtag_fd = open("/dev/jtag0", O_RDWR); + close(jtag_fd); + +ioctl() +------- +All access operations to JTAG devices are performed through ioctl interface. +The IOCTL interface supports these requests: +:: + + JTAG_SIOCSTATE - Force JTAG state machine to go into a TAPC state + JTAG_SIOCFREQ - Set JTAG TCK frequency + JTAG_GIOCFREQ - Get JTAG TCK frequency + JTAG_IOCXFER - send/receive JTAG data Xfer + JTAG_GIOCSTATUS - get current JTAG TAP state + JTAG_SIOCMODE - set JTAG mode flags. + JTAG_IOCBITBANG - JTAG bitbang low level control. + JTAG_SIOCTRST - Set TRST pin for JTAG. + +JTAG_SIOCFREQ +~~~~~~~~~~~~~ +Set JTAG clock speed: +:: + + unsigned int jtag_fd; + ioctl(jtag_fd, JTAG_SIOCFREQ, &frq); + +JTAG_GIOCFREQ +~~~~~~~~~~~~~ +Get JTAG clock speed: +:: + + unsigned int jtag_fd; + ioctl(jtag_fd, JTAG_GIOCFREQ, &frq); + +JTAG_SIOCSTATE +~~~~~~~~~~~~~~ +Force JTAG state machine to go into a TAPC state +:: + + struct jtag_tap_state { + __u8 reset; + __u8 from; + __u8 endstate; + __u32 tck; + }; + +reset: one of below options +:: + + JTAG_NO_RESET - go through selected endstate from current state + JTAG_FORCE_RESET - go through TEST_LOGIC/RESET state before selected endstate + +endstate: any state listed in jtag_tapstate enum +:: + + enum jtag_tapstate { + JTAG_STATE_TLRESET, + JTAG_STATE_IDLE, + JTAG_STATE_SELECTDR, + JTAG_STATE_CAPTUREDR, + JTAG_STATE_SHIFTDR, + JTAG_STATE_EXIT1DR, + JTAG_STATE_PAUSEDR, + JTAG_STATE_EXIT2DR, + JTAG_STATE_UPDATEDR, + JTAG_STATE_SELECTIR, + JTAG_STATE_CAPTUREIR, + JTAG_STATE_SHIFTIR, + JTAG_STATE_EXIT1IR, + JTAG_STATE_PAUSEIR, + JTAG_STATE_EXIT2IR, + JTAG_STATE_UPDATEIR + }; + +tck: clock counter + +Example: +:: + + struct jtag_tap_state tap_state; + + tap_state.endstate = JTAG_STATE_IDLE; + tap_state.reset = 0; + tap_state.tck = data_p->tck; + usleep(25 * 1000); + ioctl(jtag_fd, JTAG_SIOCSTATE, &tap_state); + +JTAG_GIOCSTATUS +~~~~~~~~~~~~~~~ +Get JTAG TAPC current machine state +:: + + unsigned int jtag_fd; + jtag_tapstate tapstate; + ioctl(jtag_fd, JTAG_GIOCSTATUS, &tapstate); + +JTAG_IOCXFER +~~~~~~~~~~~~ +Send SDR/SIR transaction +:: + + struct jtag_xfer { + __u8 type; + __u8 direction; + __u8 from; + __u8 endstate; + __u32 padding; + __u32 length; + __u64 tdio; + }; + +type: transfer type - JTAG_SIR_XFER/JTAG_SDR_XFER + +direction: xfer direction - JTAG_READ_XFER/JTAG_WRITE_XFER/JTAG_READ_WRITE_XFER + +from: jtag_tapstate enum representing the initial tap state of the chain before xfer. + +endstate: end state after transaction finish any of jtag_tapstate enum + +padding: padding configuration. See the following table with bitfield descriptions. + +=============== ========= ======= ===================================================== +Bit Field Bit begin Bit end Description +=============== ========= ======= ===================================================== +rsvd 25 31 Reserved, not used +pad data 24 24 Value used for pre and post padding. Either 1 or 0. +post pad count 12 23 Number of padding bits to be executed after transfer. +pre pad count 0 11 Number of padding bit to be executed before transfer. +=============== ========= ======= ===================================================== + +length: xfer data length in bits + +tdio : xfer data array + +Example: +:: + + struct jtag_xfer xfer; + static char buf[64]; + static unsigned int buf_len = 0; + [...] + xfer.type = JTAG_SDR_XFER; + xfer.tdio = (__u64)buf; + xfer.length = buf_len; + xfer.from = JTAG_STATE_TLRESET; + xfer.endstate = JTAG_STATE_IDLE; + + if (is_read) + xfer.direction = JTAG_READ_XFER; + else if (is_write) + xfer.direction = JTAG_WRITE_XFER; + else + xfer.direction = JTAG_READ_WRITE_XFER; + + ioctl(jtag_fd, JTAG_IOCXFER, &xfer); + +JTAG_SIOCMODE +~~~~~~~~~~~~~ +If hardware driver can support different running modes you can change it. + +Example: +:: + + struct jtag_mode mode; + mode.feature = JTAG_XFER_MODE; + mode.mode = JTAG_XFER_HW_MODE; + ioctl(jtag_fd, JTAG_SIOCMODE, &mode); + +JTAG_IOCBITBANG +~~~~~~~~~~~~~~~ +JTAG Bitbang low level operation. + +Example: +:: + + struct tck_bitbang bitbang + bitbang.tms = 1; + bitbang.tdi = 0; + ioctl(jtag_fd, JTAG_IOCBITBANG, &bitbang); + tdo = bitbang.tdo; + +JTAG_SIOCTRST +~~~~~~~~~~~~~~~ +Set TRST pin for JTAG. + +Example: +:: + + unsigned int active = 1; + ioctl(jtag_fd, JTAG_SIOCTRST, active); + +THANKS TO +--------- +Contributors to Linux-JTAG discussions include (in alphabetical order, +by last name): + +- Omar Castro +- Ernesto Corona +- Steven Filary +- Vadim Pasternak +- Jiri Pirko +- Oleksandr Shamray +- Billy Tsai From patchwork Tue Jan 30 23:32:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Corona, Ernesto" X-Patchwork-Id: 194393 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1561486dyb; Tue, 30 Jan 2024 15:33:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IFOYC26cPUjlrKC4kEsBMHE1HkDSmhOU/FlGgiM2e/zuhmZ832mwjRYI8HYFZ1sQJamPp30 X-Received: by 2002:a05:6a00:6a04:b0:6de:3521:f046 with SMTP id hy4-20020a056a006a0400b006de3521f046mr127259pfb.32.1706657580383; Tue, 30 Jan 2024 15:33:00 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Tue, 30 Jan 2024 23:32:14 +0000 Received: from LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9]) by LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9%3]) with mapi id 15.20.7228.029; Tue, 30 Jan 2024 23:32:14 +0000 From: "Corona, Ernesto" To: "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" CC: "Corona, Ernesto" , "'oleksandrs@mellanox.com'" , "Castro, Omar Eduardo" , "'omar.eduardo.castro@linux.intel.com'" , "'pombredanne@nexb.com'" , "'corbet@lwn.net'" , "'gregkh@linuxfoundation.org'" , "'gustavo.pimentel@synopsys.com'" , "'lorenzo.pieralisi@arm.com'" , "'kishon@ti.com'" , "'darrick.wong@oracle.com'" , "'bryantly@linux.vnet.ibm.com'" , "'sandeen@redhat.com'" , "'rdunlap@infradead.org'" , "'kusumi.tomohiro@gmail.com'" , "'arnd@arndb.de'" , "'mchehab+samsung@kernel.org'" , "'alexandre.belloni@bootlin.com'" , "'tytso@mit.edu'" , "'ebiggers@google.com'" , "Filary, Steven A" , "'jiri@nvidia.com'" , "'vadimp@mellanox.com'" , "'amithash@fb.com'" , "'patrickw3@fb.com'" , "Chen, Luke" , "'billy_tsai@aspeedtech.com'" , "'rgrs@protonmail.com'" Subject: [PATCH 30 5/7] Add JTAG core driver ioctl number Thread-Topic: [PATCH 30 5/7] Add JTAG core driver ioctl number Thread-Index: AdpTyGmrWVJf1WgfQiS4fB+rHp9BOA== Date: Tue, 30 Jan 2024 23:32:14 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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It provide user layer API interface for flashing and debugging external devices which equipped with JTAG interface using standard transactions. Driver exposes set of IOCTL to user space for: - XFER: SIR (Scan Instruction Register, IEEE 1149.1 Data Register scan); SDR (Scan Data Register, IEEE 1149.1 Instruction Register scan); - GIOCSTATUS read the current TAPC state of the JTAG controller - SIOCSTATE Forces the JTAG TAPC to go into a particular state. - SIOCFREQ/GIOCFREQ for setting and reading JTAG frequency. - IOCBITBANG for low level control of JTAG signals. Signed-off-by: Oleksandr Shamray Signed-off-by: Ernesto Corona Signed-off-by: Omar Castro Acked-by: Philippe Ombredanne Cc: Jonathan Corbet Cc: Greg Kroah-Hartman Cc: Gustavo Pimentel Cc: Lorenzo Pieralisi Cc: Kishon Vijay Abraham I Cc: Darrick J. Wong Cc: Bryant G. Ly Cc: Eric Sandeen Cc: Randy Dunlap Cc: Tomohiro Kusumi Cc: Arnd Bergmann Cc: Mauro Carvalho Chehab Cc: Alexandre Belloni Cc: "Theodore Ts'o" Cc: Eric Biggers Cc: Steven Filary Cc: Jiri Pirko Cc: Vadim Pasternak Cc: Amithash Prasad Cc: Patrick Williams Cc: Luke Chen Cc: Billy Tsai Cc: Rgrs v29->v30 Update Ioctl number to 0xB9 due conflicts. Change email contact. v28->v29 Move ioctl number to userspace-api/ioctl/ioctl-number.rst --- Documentation/userspace-api/ioctl/ioctl-number.rst | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index 457e16f06e04..cf602aa3a853 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -358,6 +358,8 @@ Code Seq# Include File Comments 0xB6 all linux/fpga-dfl.h 0xB7 all uapi/linux/remoteproc_cdev.h 0xB7 all uapi/linux/nsfs.h > +0xB9 00-0F linux/jtag.h JTAG driver + 0xC0 00-0F linux/usb/iowarrior.h 0xCA 00-0F uapi/misc/cxl.h 0xCA 10-2F uapi/misc/ocxl.h From patchwork Tue Jan 30 23:32:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Corona, Ernesto" X-Patchwork-Id: 194394 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1561561dyb; Tue, 30 Jan 2024 15:33:10 -0800 (PST) X-Google-Smtp-Source: AGHT+IFDQDwk51SjuJumSebcbwfW5+PbrIsMoEsuidN3WVjqh247wMjqNdNP2ahzo/ozgN3zZ3ah X-Received: by 2002:a17:903:8d0:b0:1d9:19ae:c5b9 with SMTP id lk16-20020a17090308d000b001d919aec5b9mr90363plb.67.1706657590161; Tue, 30 Jan 2024 15:33:10 -0800 (PST) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Tue, 30 Jan 2024 23:32:48 +0000 Received: from LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9]) by LV8PR11MB8463.namprd11.prod.outlook.com ([fe80::5262:6eb1:2787:8cb9%3]) with mapi id 15.20.7228.029; Tue, 30 Jan 2024 23:32:48 +0000 From: "Corona, Ernesto" To: "linux-doc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" CC: "Corona, Ernesto" , "Castro, Omar Eduardo" , "'omar.eduardo.castro@linux.intel.com'" , "'arnd@arndb.de'" , "'jiri@nvidia.com'" , "'vadimp@mellanox.com'" , "'mchehab+samsung@kernel.org'" , "'gregkh@linuxfoundation.org'" , "'davem@davemloft.net'" , "'nicolas.ferre@microchip.com'" , "'robh@kernel.org'" , "'andriy.shevchenko@linux.intel.com'" , "'lukas.bulwahn@gmail.com'" , "Filary, Steven A" , "'amithash@fb.com'" , "'patrickw3@fb.com'" , "Chen, Luke" , Billy Tsai Subject: [PATCH 30 7/7] Add AST2500 and AST2600 JTAG device in DTS Thread-Topic: [PATCH 30 7/7] Add AST2500 and AST2600 JTAG device in DTS Thread-Index: AdpTycGjGT5ZMGOAQi+KQEUwxl6cwA== Date: Tue, 30 Jan 2024 23:32:48 +0000 Message-ID: Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; 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Miller Cc: Nicolas Ferre Cc: Rob Herring Cc: Andy Shevchenko Cc: Lukas Bulwahn Cc: Steven Filary Cc: Amithash Prasad Cc: Patrick Williams Cc: Luke Chen Cc: Billy Tsai --- arch/arm/boot/dts/aspeed/aspeed-g5.dtsi | 9 +++++++++ arch/arm/boot/dts/aspeed/aspeed-g6.dtsi | 20 ++++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi index 04f98d1dbb97..3610aa758702 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g5.dtsi @@ -445,6 +445,15 @@ vuart: serial@1e787000 { status = "disabled"; }; + jtag: jtag@1e6e4000 { + compatible = "aspeed,ast2500-jtag"; + reg = <0x1e6e4000 0x1c>; + clocks = <&syscon ASPEED_CLK_APB>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER>; + interrupts = <43>; + status = "disabled"; + }; + lpc: lpc@1e789000 { compatible = "aspeed,ast2500-lpc-v2", "simple-mfd", "syscon"; reg = <0x1e789000 0x1000>; diff --git a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi index c4d1faade8be..d5353f728689 100644 --- a/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed/aspeed-g6.dtsi @@ -411,6 +411,26 @@ xdma: xdma@1e6e7000 { status = "disabled"; }; + jtag0: jtag@1e6e4000 { + compatible = "aspeed,ast2600-jtag"; + reg = <0x1e6e4000 0x40>; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER>; + interrupts = ; + status = "disabled"; + }; + + jtag1: jtag@1e6e4100 { + compatible = "aspeed,ast2600-jtag"; + reg = <0x1e6e4100 0x40>; + clocks = <&syscon ASPEED_CLK_APB1>; + resets = <&syscon ASPEED_RESET_JTAG_MASTER2>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_jtagm_default>; + status = "disabled"; + }; + adc0: adc@1e6e9000 { compatible = "aspeed,ast2600-adc0"; reg = <0x1e6e9000 0x100>;