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Tue, 30 Jan 2024 13:51:29 -0600 Received: from lelvsmtp6.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40UJpTKv005747; Tue, 30 Jan 2024 13:51:29 -0600 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 1/2] dt-bindings: mfd: syscon: Add ti,am654-serdes-ctrl compatible Date: Tue, 30 Jan 2024 13:51:27 -0600 Message-ID: <20240130195128.58748-1-afd@ti.com> X-Mailer: git-send-email 2.39.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789546276147693279 X-GMAIL-MSGID: 1789546276147693279 Add TI SERDES control registers compatible. This is a region found in the TI AM65 CTRL_MMR0 register space[0]. Each instance is used to control a SERDES clock and lane select mux. [0] https://www.ti.com/lit/pdf/spruid7 Signed-off-by: Andrew Davis Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/mfd/syscon.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 084b5c2a2a3c2..d8679a2ad4b10 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -73,6 +73,7 @@ properties: - rockchip,rv1126-qos - starfive,jh7100-sysmain - ti,am654-dss-oldi-io-ctrl + - ti,am654-serdes-ctrl - const: syscon From patchwork Tue Jan 30 19:51:28 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Davis X-Patchwork-Id: 194309 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1459937dyb; Tue, 30 Jan 2024 11:52:35 -0800 (PST) X-Google-Smtp-Source: AGHT+IHp33S/jq3art5nHJljfQeuxELvquYDvyieJTASlv5S3mmI+DoHgUt0/a436nXMoEyQVURs X-Received: by 2002:a05:6a20:32a2:b0:19c:97be:56d7 with SMTP id g34-20020a056a2032a200b0019c97be56d7mr1508138pzd.30.1706644355571; Tue, 30 Jan 2024 11:52:35 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706644355; cv=pass; d=google.com; s=arc-20160816; b=lIRpKaS0QKfea2o0eKnsc1H8z5FHTS58+3PKShNGAvDShrzZVptoYwY3j2brzVfPHM B0qh+NfiC126Fe6wSc7eNZ/CkkZnHkkXGZ37FZgbC1Kv5PCX0laZ8b8UVbsfF/INnOvv Oq3XMBrmxtmZu4G8ML+H4kcfXLg+KlwJsCaTCV/t1VRpu4GysHIGBzn58vcpqPqrmAjB F895J2Hj6Pxn6hvAnVNRDElf8iLtxNva2J7znDHi1EczMMXIyt67dk2U/9hwaUje6R7O qnTQy4JFzsp8kreqPkNGf7ikX/2ZtOd10OhdJYK442dT70Swy9RIkMVypncu9TEwmt3e KrIA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=Hz9x1qh2ZfSepIaUFBwFwX4XigsDM5yxW6ZItLlcZW0=; fh=MyUppKttrNuIto4SF/fZZ+PhpsTyrywZS4cOL2Thdt0=; b=rm5OzaKTb3pTuaAqdMCNS+dMVDE87m9q04VN22TCLAYpoY8kt8DxBQY5awQEs4xKzL DyARyaDgBtoGN6MHXbROmycId9mMkWKifYhazdVejoZze3+XrU8ZKmKAGvnkcNemWDD3 d0WSCuzuHl+86YRwmke6ycn6uFhjCMr5I5duBmImm8VKJjDF5KmcYpFhDh13DFVm018M BCx1jD0fIkZFT/6et9G3QnycbABN7bEtpxLGZwEmAmvvvQ7KCthjVyByn2K8UGxX0vZk foRJo1cTSar2EnDDuTA8eBoZiyvvUmJaND8oybsqzUuIJoXBK+VwpqPsOl2AG6Yib+3e Q2Gg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=fFlEkusr; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-45222-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-45222-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Tue, 30 Jan 2024 13:51:30 -0600 Received: from lelvsmtp6.itg.ti.com ([10.249.42.149]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40UJpTKw005747; Tue, 30 Jan 2024 13:51:29 -0600 From: Andrew Davis To: Nishanth Menon , Vignesh Raghavendra , Tero Kristo , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: , , , Andrew Davis Subject: [PATCH 2/2] arm64: dts: ti: k3-am65: Add full compatible to SerDes control nodes Date: Tue, 30 Jan 2024 13:51:28 -0600 Message-ID: <20240130195128.58748-2-afd@ti.com> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20240130195128.58748-1-afd@ti.com> References: <20240130195128.58748-1-afd@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789546311371121159 X-GMAIL-MSGID: 1789546311371121159 This matches the binding for this register region which fixes a couple DTS check warnings. While here trim the leading 0s from the "reg" definition. Signed-off-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi index fcea544656360..62a68740dac6e 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi @@ -483,13 +483,13 @@ scm_conf: scm-conf@100000 { ranges = <0x0 0x0 0x00100000 0x1c000>; serdes0_clk: clock@4080 { - compatible = "syscon"; - reg = <0x00004080 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4080 0x4>; }; serdes1_clk: clock@4090 { - compatible = "syscon"; - reg = <0x00004090 0x4>; + compatible = "ti,am654-serdes-ctrl", "syscon"; + reg = <0x4090 0x4>; }; serdes_mux: mux-controller {