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[2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id y62-20020a636441000000b005d5c9f0d40csi7279830pgb.302.2024.01.30.01.12.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Jan 2024 01:12:58 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-44206-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b="d/oxvNJu"; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-44206-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-44206-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 346032842D8 for ; Tue, 30 Jan 2024 09:07:27 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id AF77A67745; Tue, 30 Jan 2024 09:04:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b="d/oxvNJu" Received: from relay1-d.mail.gandi.net (relay1-d.mail.gandi.net [217.70.183.193]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C15D260894; Tue, 30 Jan 2024 09:04:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.70.183.193 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706605481; cv=none; b=KTKiP7HgDaHl9ZErNnbrqoTRB2HfxvHBWytjNQVzMgRjGBxQyDyOGK2t6sd7r+NSYYZM/NXDwgZqwCuZ5QeRT4uIl/5f01QDX9XngsI2GEjKpzh7k9yhgW8u+RFc97uJvTx0vcdW5dQeRTIGshTmwQ8Qnd9CWS/qqDa89HHOXtk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706605481; c=relaxed/simple; bh=zMZUnh+ptFzCUiMHGRQMzrBIbMYD6NQ3+yiLZXs+Acg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=qYo+Omzjy/gD0hvCrJxQW0OXl+zcgqXSMZ+MEF0FUYXsYZR3bEy++8SIyrGs2n2G9N3VhRwuPZcBUfF9lpaOTsy+gZAyMdEc7lV+5GVQZWg1HrW5F3BFNqLUcYmgoxNuQpwdnFA4ipLbxgV93j6LtlsSzSvslzB5h4VUrZLTc4Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com; spf=pass smtp.mailfrom=bootlin.com; dkim=pass (2048-bit key) header.d=bootlin.com header.i=@bootlin.com header.b=d/oxvNJu; arc=none smtp.client-ip=217.70.183.193 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=reject dis=none) header.from=bootlin.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=bootlin.com Received: by mail.gandi.net (Postfix) with ESMTPA id 1E91D240006; Tue, 30 Jan 2024 09:04:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1706605476; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=BZLD7+4VmFr+Iy4x1r22wPwY17kqHNg9zXXFrmCLK6s=; b=d/oxvNJuzEefAEUXVPikn+2ik3mPEtm6jVEttEQg97iVUiRaLfJPQqa0j7F+DzNo19dsv7 87mjCRV0bns6Y57PcTc/JFJAIFeZi9WnTGidaEmz6ErfSPm9ybWQvyFAmg9bLIvKP2Kqje gsgtSDkfqJ06w/YCLiOIbBYMMPUrj7WZ2s2um1eehUQNoz0oItK3NXLLdByqFMqEvvUVaw fEJ+MDjxnYU+XaPJ0jXa6Iwcd9gb00UGu0xng8F0X/7TUnUOvQxiQutFPBGfKFHd1DJvS8 K8e8XZ1meX+9sPPjywKK+3GZFqLYV9vkzFKd7uinAP3q2YrU315B/SOFTtWHgA== From: Bastien Curutchet To: "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina Subject: [PATCH 1/2] dt-bindings: net: Add TI DP83640 Date: Tue, 30 Jan 2024 09:59:34 +0100 Message-ID: <20240130085935.33722-2-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240130085935.33722-1-bastien.curutchet@bootlin.com> References: <20240130085935.33722-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789506070544888786 X-GMAIL-MSGID: 1789506070544888786 The TI DP83640 is a PTP PHY. Some of his features can be enabled by hardware straps or by registers configuration. Add a device tree binding for configuration through registers Signed-off-by: Bastien Curutchet --- .../devicetree/bindings/net/ti,dp83640.yaml | 113 ++++++++++++++++++ include/dt-bindings/net/ti-dp83640.h | 18 +++ 2 files changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/ti,dp83640.yaml create mode 100644 include/dt-bindings/net/ti-dp83640.h diff --git a/Documentation/devicetree/bindings/net/ti,dp83640.yaml b/Documentation/devicetree/bindings/net/ti,dp83640.yaml new file mode 100644 index 000000000000..b0f389122934 --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,dp83640.yaml @@ -0,0 +1,113 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright 2024 Nanometrics Inc +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,dp83640.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI DP83640 ethernet PHY + +allOf: + - $ref: ethernet-controller.yaml# + +maintainers: + - Bastien Curutchet + +description: | + The DP83640 Precision PHYTER device delivers the highest level of precision + clock synchronization for real time industrial connectivity based on the + IEEE 1588 standard. The DP83640 has deterministic, low latency and allows + choice of microcontroller with no hardware customization required + + This device interfaces directly to the MAC layer through the + IEEE 802.3 Standard Media Independent Interface (MII), or Reduced MII (RMII). + + Specifications about the Ethernet PHY can be found at: + https://www.ti.com/lit/gpn/dp83640 + +properties: + reg: + maxItems: 1 + + ti,clk-output: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + If present, enables or disables the CLK_OUT pin. + CLK_OUT pin disabling can also be strapped. If the strap pin is not set + correctly or not set at all then this can be used to configure it. + - 0 = CLK_OUT pin disabled + - 1 = CLK_OUT pin enabled + - unset = Configured by straps + + ti,led-config: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [1, 2, 3] + description: | + If present, configures the LED Mode (values defined in + dt-bindings/net/ti-dp83640.h). + LED configuration can also be strapped. If the strap pin is not set + correctly or not set at all then this can be used to configure it. + - 1 = Mode 1 + LED_LINK = ON for Good Link, OFF for No Link + LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s + LED_ACT = ON for Activity, OFF for No Activity + - 2 = Mode 2 + LED_LINK = ON for Good Link, BLINK for Activity + LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s + LED_ACT = ON for Collision, OFF for No Collision + - 3 = Mode 3 + LED_LINK = ON for Good Link, BLINK for Activity + LED_SPEED = ON in 100 Mb/s, OFF in 10 Mb/s + LED_ACT = ON for Full Duplex, OFF for Half Duplex + - unset = Configured by straps + + ti,phy-control-frames: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + If present, enables or disables the PHY control frames. + PHY Control Frames support can also be strapped. If the strap pin is not + set correctly or not set at all then this can be used to configure it. + - 0 = PHY Control Frames disabled + - 1 = PHY Control Frames enabled + - unset = Configured by straps + + ti,fiber-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + If present, enables or disables the FX Fiber Mode. + Fiber mode support can also be strapped. If the strap pin is not set + correctly or not set at all then this can be used to configure it. + - 0 = FX Fiber Mode disabled + - 1 = FX Fiber Mode enabled + - unset = Configured by straps + + ti,energy-detect-en: + $ref: /schemas/types.yaml#/definitions/flag + description: | + If present, Energy Detect Mode is enabled. If not present, Energy Detect + Mode is disabled. This feature can not be strapped. + +required: + - reg + +unevaluatedProperties: false + +examples: + - | + #include + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + ethphy0: ethernet-phy@0 { + reg = <0>; + ti,clk-output = <0>; + ti,energy-detect-en; + ti,led-config = ; + ti,phy-control-frames = <1>; + ti,fiber-mode = <1>; + }; + }; diff --git a/include/dt-bindings/net/ti-dp83640.h b/include/dt-bindings/net/ti-dp83640.h new file mode 100644 index 000000000000..5f44f8eeb666 --- /dev/null +++ b/include/dt-bindings/net/ti-dp83640.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Device Tree constants for the Texas Instruments DP83640 PHY + * + * Author: Bastien Curutchet bastien.curutchet@bootlin.com> + * + * Copyright: 2024 Nanometrics Inc. + */ + +#ifndef _DT_BINDINGS_TI_DP83640_H +#define _DT_BINDINGS_TI_DP83640_H + +/* PHY CTRL bits */ +#define DP83640_PHYCR_LED_CNFG_MODE_1 1 +#define DP83640_PHYCR_LED_CNFG_MODE_2 2 +#define DP83640_PHYCR_LED_CNFG_MODE_3 3 + +#endif From patchwork Tue Jan 30 08:59:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bastien Curutchet X-Patchwork-Id: 193900 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp1090284dyb; Tue, 30 Jan 2024 01:08:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IErlAA3XvYyJJfMEvlNVOZ67cvhAGdPwYozq8k3GchHFel6ShgygGXCPZcbBQWa1mwsKoBa X-Received: by 2002:a17:906:1b09:b0:a34:a6af:22f1 with SMTP id o9-20020a1709061b0900b00a34a6af22f1mr5886291ejg.62.1706605713499; Tue, 30 Jan 2024 01:08:33 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706605713; cv=pass; d=google.com; s=arc-20160816; b=GEgu4IDuM1qplJSlOvK5UOG/Rvri/dz/LByNfV6P3JnuxcH5hitPciprXmeK9hujWE GjjtAgM5T8XA1osyka+8mJWGoQJjR8VCROx/ohi12s/y3ttsGkGqi2YovuT8DGLKjrwX wm9+UoznwxGifpQ4KJ+9Bb3I/JlWOD/H1icBpuvrsTEnXn+YipbwJQz7OIPdcwui8qBw LBprR9jXhvNKVkmTcXDWl58Qj/NEvZ4yKSlqfINQieU3AjChoEc84K5MNewKH3V0LnQ6 UwDNVrnf96Jmwk23UKGCwFmX+Ob3Bt79fV2sxinicRXyVXgOjQDT6DcZpLHImEg6neX7 z7Vw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=l/L6bzf2gaHl/JyjqO/iv8M2x2ZxFgKdEPhznPGhi2w=; fh=zDwpaHP8zPRCXncT7CFoA013q2yPieCmPwM51Q3OyGo=; b=kwvoOCBzFXR6Bsrx0AT4kNvQaC8xiH0QYzVNg5ollFxGEqrGCJXeAg3P6JSpo9QlCt vwWBPS8e5cJVz1gbCWmYCOab9y1Xdpk1CuikBBHa07hlVe83rLDqu9AVmTwcb+x24MOF fLccPVNJO4bAvjfPEu2KRltERnYv8NkOMVXJrsUyj26q7lB87y3Ex9fxoXmuCO+lm3YI XCB73VVG/EgBZ1MuNFhGmW/NEKN7IMjvOk1Y515DO7cWnQkFFFog6RXA+8du3TEbbP0U vtImfOy7zMu2j5OEXOMb8/3N/xLevD1UQ6zi8Wnd+VsgEq/AA7f7pyfRpbizx7xLGVCe df4g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@bootlin.com header.s=gm1 header.b=UFdfHjAt; arc=pass (i=1 spf=pass spfdomain=bootlin.com dkim=pass dkdomain=bootlin.com dmarc=pass fromdomain=bootlin.com); spf=pass (google.com: domain of linux-kernel+bounces-44207-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-44207-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=REJECT sp=REJECT dis=NONE) header.from=bootlin.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Richard Cochran , Andrew Lunn , Heiner Kallweit , Russell King , Bastien Curutchet Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Thomas Petazzoni , Herve Codina Subject: [PATCH 2/2] net: phy: Add some configuration from device-tree Date: Tue, 30 Jan 2024 09:59:35 +0100 Message-ID: <20240130085935.33722-3-bastien.curutchet@bootlin.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240130085935.33722-1-bastien.curutchet@bootlin.com> References: <20240130085935.33722-1-bastien.curutchet@bootlin.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-GND-Sasl: bastien.curutchet@bootlin.com X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789505792568965074 X-GMAIL-MSGID: 1789505792568965074 Some features can now be enabled or disabled from device tree. If attributes are present in device-tree, features are enabled or disabled via MDIO registers. Else, hardware configuration is left as is. These features are : Energy Detect Mode, PHY Control Frames, LED configuration and Fiber Mode. Signed-off-by: Bastien Curutchet --- drivers/net/phy/dp83640.c | 131 +++++++++++++++++++++++++++++++++- drivers/net/phy/dp83640_reg.h | 21 +++++- 2 files changed, 150 insertions(+), 2 deletions(-) diff --git a/drivers/net/phy/dp83640.c b/drivers/net/phy/dp83640.c index 5c42c47dc564..f5770002b849 100644 --- a/drivers/net/phy/dp83640.c +++ b/drivers/net/phy/dp83640.c @@ -7,6 +7,7 @@ #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -1418,15 +1420,142 @@ static int dp83640_ts_info(struct mii_timestamper *mii_ts, return 0; } +#ifdef CONFIG_OF_MDIO +static int dp83640_of_init(struct phy_device *phydev) +{ + struct device *dev = &phydev->mdio.dev; + struct device_node *of_node = dev->of_node; + int reg_val; + u32 of_val; + int ret; + + if (!of_node) + return 0; + + /* All configured features reside in PAGE 0 */ + phy_write(phydev, PAGESEL, 0); + + /* Energy detect mode */ + reg_val = phy_read(phydev, EDCR); + if (of_property_present(of_node, "ti,energy-detect-en")) + reg_val |= ED_EN; + else + reg_val &= ~ED_EN; + phy_write(phydev, EDCR, reg_val); + + /* CLK_OUTPUT Pin */ + if (of_property_present(of_node, "ti,clk-output")) { + ret = of_property_read_u32(of_node, "ti,clk-output", &of_val); + if (ret) + return ret; + + reg_val = phy_read(phydev, PHYCR2); + switch (of_val) { + case 0: + reg_val |= CLK_OUT_DIS; + break; + case 1: + reg_val &= ~CLK_OUT_DIS; + break; + default: + phydev_err(phydev, "Invalid value for ti,clk-output property (%d)" + , of_val); + return -EINVAL; + } + phy_write(phydev, PHYCR2, reg_val); + } + + /* LED configuration */ + if (of_property_present(of_node, "ti,led-config")) { + ret = of_property_read_u32(of_node, "ti,led-config", &of_val); + if (ret) + return ret; + + reg_val = phy_read(phydev, PHYCR) & ~(LED_CNFG_1 | LED_CNFG_0); + switch (of_val) { + case DP83640_PHYCR_LED_CNFG_MODE_1: + reg_val |= LED_CNFG_0; + break; + case DP83640_PHYCR_LED_CNFG_MODE_2: + /* Keeping LED_CNFG_1 and LED_CNFG_0 unset */ + break; + case DP83640_PHYCR_LED_CNFG_MODE_3: + reg_val |= LED_CNFG_1; + break; + default: + phydev_err(phydev, "Invalid value for ti,led-config property (%d)" + , of_val); + return -EINVAL; + } + phy_write(phydev, PHYCR, reg_val); + } + if (of_property_present(of_node, "ti,phy-control-frames")) { + of_property_read_u32(of_node, "ti,phy-control-frames", &of_val); + if (ret) + return ret; + + reg_val = phy_read(phydev, PCFCR); + switch (of_val) { + case 0: + reg_val &= ~PCF_EN; + break; + case 1: + reg_val |= PCF_EN; + break; + default: + phydev_err(phydev, "Invalid value for ti,phy-control-frames property (%d)" + , of_val); + return -EINVAL; + } + phy_write(phydev, PCFCR, reg_val); + } + if (of_property_present(of_node, "ti,fiber-mode")) { + ret = of_property_read_u32(of_node, "ti,fiber-mode", &of_val); + if (ret) + return ret; + + reg_val = phy_read(phydev, PCSR); + switch (of_val) { + case 0: + reg_val &= ~FX_EN; + break; + case 1: + reg_val |= FX_EN; + break; + default: + phydev_err(phydev, "Invalid value for ti,fiber-mode property (%d)" + , of_val); + return -EINVAL; + } + phy_write(phydev, PCSR, reg_val); + /* Write SOFT_RESET bit to ensure configuration */ + reg_val = phy_read(phydev, PHYCR2) | SOFT_RESET; + phy_write(phydev, PHYCR2, reg_val); + } + + return 0; +} +#else +static int dp83640_of_init(struct phy_device *phydev) +{ + return 0; +} +#endif /* CONFIG_OF_MDIO */ + static int dp83640_probe(struct phy_device *phydev) { struct dp83640_clock *clock; struct dp83640_private *dp83640; - int err = -ENOMEM, i; + int err, i; if (phydev->mdio.addr == BROADCAST_ADDR) return 0; + err = dp83640_of_init(phydev); + if (err < 0) + return err; + + err = -ENOMEM; clock = dp83640_clock_get_bus(phydev->mdio.bus); if (!clock) goto no_clock; diff --git a/drivers/net/phy/dp83640_reg.h b/drivers/net/phy/dp83640_reg.h index daae7fa58fb8..8877ba560406 100644 --- a/drivers/net/phy/dp83640_reg.h +++ b/drivers/net/phy/dp83640_reg.h @@ -6,7 +6,11 @@ #define HAVE_DP83640_REGISTERS /* #define PAGE0 0x0000 */ +#define PCSR 0x0016 /* PCS Configuration and Status Register */ +#define PHYCR 0x0019 /* PHY Control Register */ #define PHYCR2 0x001c /* PHY Control Register 2 */ +#define EDCR 0x001D /* Energy Detect Control Register */ +#define PCFCR 0x001F /* PHY Control Frames Control Register */ #define PAGE4 0x0004 #define PTP_CTL 0x0014 /* PTP Control Register */ @@ -50,8 +54,23 @@ #define PTP_GPIOMON 0x001e /* PTP GPIO Monitor Register */ #define PTP_RXHASH 0x001f /* PTP Receive Hash Register */ +/* Bit definitions for the PCSR register */ +#define FX_EN BIT(6) /* Enable FX Fiber Mode */ + +/* Bit definitions for the PHYCR register */ +#define LED_CNFG_0 BIT(5) /* LED configuration, bit 0 */ +#define LED_CNFG_1 BIT(6) /* LED configuration, bit 1 */ + /* Bit definitions for the PHYCR2 register */ -#define BC_WRITE (1<<11) /* Broadcast Write Enable */ +#define CLK_OUT_DIS BIT(1) /* Disable CLK_OUT pin */ +#define SOFT_RESET BIT(9) /* Soft Reset */ +#define BC_WRITE BIT(11) /* Broadcast Write Enable */ + +/* Bit definitions for the EDCR register */ +#define ED_EN BIT(15) /* Enable Energy Detect Mode */ + +/* Bit definitions for the PCFCR register */ +#define PCF_EN BIT(0) /* Enable PHY Control Frames */ /* Bit definitions for the PTP_CTL register */ #define TRIG_SEL_SHIFT (10) /* PTP Trigger Select */