From patchwork Tue Nov 15 04:52:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20185 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2521027wru; Mon, 14 Nov 2022 20:57:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5g9iZERUUY37bY5uxrYILe+Bpj6L7Z1Qx598VwZ7O2NFGONnjjxj8VKhyIq8AJF89qQLOj X-Received: by 2002:aa7:c3d1:0:b0:45a:2d7c:f3a0 with SMTP id l17-20020aa7c3d1000000b0045a2d7cf3a0mr13462785edr.98.1668488279886; Mon, 14 Nov 2022 20:57:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488279; cv=none; d=google.com; s=arc-20160816; b=avgKjyhd+xkDg9byV3JxsheWbqyeHJE7jwZGhCp+Cv+U8v2rCdmeGCs7aiM+C0p/W1 8RbKZE8Flq3Yk7GL2uqBkZveL+/M6eo04S50uKcnyi0QYhq8s6AsGchNUkeRDUgO9RTE JZ2JjhpVycYwjPdrpNV3E7ZJeQQYKydDtRzFd2TWTwcQHiwCctzLi0gXVaXU6CfOsYfN KYPKogYesvyPiUSQKzy9Wf7KkdiAeviqPNJLuTSkZeeNr7JlYyDA/hgM6xwte+ep6Dza Geq95xEn3xDjt+kjxcxRaIcPRvm1MMAiVW3ZSWZg1C9uWYHt8S4ivhGlkvf8jRkd8Ln3 QnLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=FGlrJ2DIgymeiAoz8S4rAB8IbcT9ZGJlWjvLrweXXU4=; b=GAlsHQT0nJYwGJa0F4cmyNx3ElKrWWQrneLIl1ISBYdquaaXomMNZ2nvl02B8mJws+ to+IxgeEqUfIn4xsH2FvkiUyXIhca5I1aYM7mSIqiE9DIc7z+wdi+M7LEWgAJ6szcztX ptenN+oGkPykpgfyKTwgb2NJpJr/Yd6e3m4TtBcfaq/+OT3S6GrMJ2+auF67aymNF2Gb 6ctJbp25UDw2z+hKa/e3X97tXK8yzslRBzXUJcixalNiTgM0sUgk60LCyJn57peglFL3 ybsqv/oRXmxJ6EFOU4sjBfV2st/hKB91G0Gr9FlAv9q67ZgJQnt+o60fmSXpEtRe/I8n CIwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=bovNMCl0; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id du4-20020a17090772c400b007aebd20575fsi11039032ejc.466.2022.11.14.20.57.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 20:57:59 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=bovNMCl0; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 696753830B11 for ; Tue, 15 Nov 2022 04:57:53 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 696753830B11 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488273; bh=FGlrJ2DIgymeiAoz8S4rAB8IbcT9ZGJlWjvLrweXXU4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=bovNMCl09SlMcuVA41KI0t5px1b/NbsgRuUE5CQWlzk/2VWeW7YZJ4wqDp3RH0xIM rD6tCIbirNCuOtOvVxrMapK6iBi3EqN+Eg4ZfKLssbw0e0rsd0uY4CxDG5Y4qC0BiU tVp7Qyntzyfn7tkDw8GymYO/yw1Lo4r0IYJiGtCM= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7F07F3832353 for ; Tue, 15 Nov 2022 04:57:45 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7F07F3832353 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D2EEB300089; Tue, 15 Nov 2022 04:57:43 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 01/11] opcodes/riscv-dis.c: More tidying Date: Tue, 15 Nov 2022 04:52:44 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536766377404391?= X-GMAIL-MSGID: =?utf-8?q?1749536766377404391?= This is a general tidying commit. opcodes/ChangeLog: * riscv-dis.c (struct riscv_private_data) Add summary. Make length of hi_addr more meaningful. --- opcodes/riscv-dis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3a31647a2f8..ea45a631a25 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -52,11 +52,12 @@ static riscv_parse_subset_t riscv_rps_dis = false, /* check_unknown_prefixed_ext. */ }; +/* Private data structure for the RISC-V disassembler. */ struct riscv_private_data { bfd_vma gp; bfd_vma print_addr; - bfd_vma hi_addr[OP_MASK_RD + 1]; + bfd_vma hi_addr[NGPR]; bool to_print_addr; bool has_gp; }; From patchwork Tue Nov 15 04:52:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20188 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3423917dyb; Mon, 14 Nov 2022 21:00:17 -0800 (PST) X-Google-Smtp-Source: AA0mqf7+j0HY3Y6vmKG5d4pYFw9d03tvXHLiCgf6LiyaymXUqd/ve+LXTVoAYLXE5QyWFgvcfyuS X-Received: by 2002:a05:6402:457:b0:462:750b:bced with SMTP id p23-20020a056402045700b00462750bbcedmr13064826edw.313.1668488417535; Mon, 14 Nov 2022 21:00:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488417; cv=none; d=google.com; s=arc-20160816; b=ozr20ydeEE7a4L5M6yvcjmJb28xZUIfYA3EyQ4uWTIBhS12ExpkjsLWI6AYsTTxt/O +6mpCnd0NOt2sAjfaVWf/wlZAmghx7bJOSRqkT1M7tFCaIOjt3TJeUwRchFWzRY3by13 HfGD1MDSm1ulFitQyEgCuK4oRgYqDHjMgu7Q84hO+3tQKy3/IZRYiUPUyVF3wROgV+32 sFjSupZBo1uAstXJc9w6RQeeCbJ1iqQk/G/tnqRqeW2U4r3QyEYRDYNbzEFu2svI8Y+Y NjHIXTccUAnPP8KPqlEFpa1Ft2H1HAxGeXEO2WJoNcPU+69BSOlUQrO/3+Y/CJNuf1GV Cs5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=4nJlU4xgMoDZLFxR6ZH0/laDoNw/2B7hz36S+OA4kdQ=; b=jWPAZTee3d1NTyXMjOOOaHVK0wgLd5ty7O3oiWb3CD9vV0BvXx4CRTyWhMq0VGij4U angrUcn2RsKdBJ+UOLsXhEeCZ+VQGW1PGbeOPl2ux5zLJZE4hb+5dfdWs5anUiLIj1CD sZqhBO3MW8Hhzfz/ZkmVlw4+gWi0hJQYbOUhMJK2Cm8SSQt90nJgNT6q2Pxscar9Rxro gzbvi18h9RoO/3IICeiFFwKBemh/LDo8ufSX+3vWCQB4JStpst18YQUqoX1LFATmrs4a JugOsWmFdqt+r/LfAwoCyVtpMggwcuuP91MZ5h2Yq2Q7PZlFN/DjAvNrmLlSq6QFRpIC XJjg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=pFlMt3W8; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id x5-20020aa7d6c5000000b00463d163df67si8431925edr.430.2022.11.14.21.00.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:00:17 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=pFlMt3W8; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9878C382E508 for ; Tue, 15 Nov 2022 04:58:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9878C382E508 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488336; bh=4nJlU4xgMoDZLFxR6ZH0/laDoNw/2B7hz36S+OA4kdQ=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=pFlMt3W8t9a3PYAdpjrfeiYfcpARpRbbI9xYtgkzJ/m8oTJECdvf79fCQBeP6pnpb RP8CfJ/joxDurav+gQQYjOvwXVMHjpKiKLYK2yzPVd1rDnYkBP8JGDZuXh4u982136 mNs8c54/QAeENa7ijTn2M9yKGhS+3VhZEQ7pBwn4= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 030923830B27 for ; Tue, 15 Nov 2022 04:57:56 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 030923830B27 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 58B0C300089; Tue, 15 Nov 2022 04:57:54 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 02/11] RISC-V: Add test for 'Zfinx' register switching Date: Tue, 15 Nov 2022 04:52:45 +0000 Message-Id: <9795298f970f0b8a02796edc2c4249417614103b.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536910956208674?= X-GMAIL-MSGID: =?utf-8?q?1749536910956208674?= Because the author is going to reorganize core RISC-V disassembler, we have to make sure that nothing is broken when disassembling with mapping symbols with ISA string. This commit adds a testcase for 'F' and 'Zfinx' instructions to make sure that "FPR" register names are correctly switched when necessary. gas/ChangeLog: * testsuite/gas/riscv/mapping.s: Add 'F' and 'Zfinx' testcase. * testsuite/gas/riscv/mapping-dis.d: Likewise. * testsuite/gas/riscv/mapping-symbols.d: Likewise. --- gas/testsuite/gas/riscv/mapping-dis.d | 7 +++++++ gas/testsuite/gas/riscv/mapping-symbols.d | 4 ++++ gas/testsuite/gas/riscv/mapping.s | 10 ++++++++++ 3 files changed, 21 insertions(+) diff --git a/gas/testsuite/gas/riscv/mapping-dis.d b/gas/testsuite/gas/riscv/mapping-dis.d index b1a26fbd151..f0508499b72 100644 --- a/gas/testsuite/gas/riscv/mapping-dis.d +++ b/gas/testsuite/gas/riscv/mapping-dis.d @@ -91,3 +91,10 @@ Disassembly of section .text.relax.align: [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop [ ]+[0-9a-f]+:[ ]+00200513[ ]+li[ ]+a0,2 [ ]+[0-9a-f]+:[ ]+00000013[ ]+nop + +Disassembly of section .text.dis.zfinx: + +0+000 <.text.dis.zfinx>: +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+a0,a1,a2 +[ ]+[0-9a-f]+:[ ]+00c5f553[ ]+fadd\.s[ ]+fa0,fa1,fa2 diff --git a/gas/testsuite/gas/riscv/mapping-symbols.d b/gas/testsuite/gas/riscv/mapping-symbols.d index 40df3409736..b28e3306b1b 100644 --- a/gas/testsuite/gas/riscv/mapping-symbols.d +++ b/gas/testsuite/gas/riscv/mapping-symbols.d @@ -42,6 +42,10 @@ SYMBOL TABLE: 0+00 l d .text.relax.align 0+00 .text.relax.align 0+00 l .text.relax.align 0+00 \$xrv32i2p1_c2p0 0+08 l .text.relax.align 0+00 \$xrv32i2p1 +0+00 l d .text.dis.zfinx 0+00 .text.dis.zfinx +0+00 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 +0+04 l .text.dis.zfinx 0+00 \$xrv32i2p1_zicsr2p0_zfinx1p0 +0+08 l .text.dis.zfinx 0+00 \$xrv32i2p1_f2p2_zicsr2p0 0+0a l .text.section.padding 0+00 \$x 0+03 l .text.odd.align.start.insn 0+00 \$d 0+04 l .text.odd.align.start.insn 0+00 \$x diff --git a/gas/testsuite/gas/riscv/mapping.s b/gas/testsuite/gas/riscv/mapping.s index 3014a69e792..4fee2b420f0 100644 --- a/gas/testsuite/gas/riscv/mapping.s +++ b/gas/testsuite/gas/riscv/mapping.s @@ -119,3 +119,13 @@ addi a0, zero, 1 # $x, won't added .align 3 # $x, won't added addi a0, zero, 2 # $xrv32i .option pop + +.section .text.dis.zfinx, "ax" +.option push +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option arch, rv32i_zfinx +fadd.s a0, a1, a2 # $xrv32i_zfinx +.option arch, rv32if +fadd.s fa0, fa1, fa2 # $xrv32if +.option pop From patchwork Tue Nov 15 04:52:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20186 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2521184wru; Mon, 14 Nov 2022 20:58:34 -0800 (PST) X-Google-Smtp-Source: AA0mqf5GAmGJojhEN3CJiyAxlfV3ez36qzGSSadLB1NWogD6pxLdKWJ5FS6C4bAPcDIlv/7M2+Th X-Received: by 2002:a05:6402:1247:b0:461:5542:6884 with SMTP id l7-20020a056402124700b0046155426884mr13069512edw.390.1668488314872; Mon, 14 Nov 2022 20:58:34 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488314; cv=none; d=google.com; s=arc-20160816; b=ObgfnRZXKf8vclvdmYUfZ4uyF7PCT71fY0a+LjYbS7ZQ4CLQ0QX/nOQAWLnP6wCE1T dm5AdlyO6vJlSqkj4tms9Q5HCECfFmkd1nd7tNn+9z2YUjmZsK7QetoCd+NzgvYTxiKG PHv0afaBH5XNlvTsymUA5fMLJnHAM9Z42lcIO1Pk7q9oAqwM68nKI/xV6AZlWKoJ3mb6 eMAV8z5KFAh9jw0TVy2vVpoMLxgLnkE6klt/CvEDRuBggOjS1GA2UN+h4hftuodzs9cN Lrup0w8F/p8H4H++dX7wqkyiuxPTkOY8UzMTCZMfkRN9M8fziLpB+OreAQB45jLc22w9 Qd4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=ZzcX+wTveu/IJQGMxIZMCkFoi4iIbm0NQhyntGQmuKs=; b=JhPa80j7hV1bThrYNvuryu49me3hukCgtrYn6ych1uXwBliwG5jfhEHboc7/lSJ1UB oFVApRbUs9n+jEcBkBFJNQABuxQ40rDW5UgSiXZRn/sWT3g4/yenlUqUhinYVqWlRMoB 1DuaTPBGdR32sf8ALhqCR+oyWU6ikzsh2qfbS3IFaCruu6cjvbg7m1LVShe7qcE/ip43 /5G47BV3ZkloFkoT8k3bbqbR6u2Iizi7zzR46BhIVYhT8u8rhufrF2FGO2UN5hc5pPvG frv8Z9p7CMY68HUEnP0eSqfqTUpTsTrmbdMCdjwOA366jefn8RDC3kcS9y6/pFaMOjWZ /Bfg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=n3egHilH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id hp11-20020a1709073e0b00b0078d2a99972fsi11155960ejc.316.2022.11.14.20.58.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 20:58:34 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=n3egHilH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 32345382EF1F for ; Tue, 15 Nov 2022 04:58:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 32345382EF1F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488295; bh=ZzcX+wTveu/IJQGMxIZMCkFoi4iIbm0NQhyntGQmuKs=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=n3egHilHN+LEAaiAu2SEgtdVte9cyTuGOSsc//+/JKng2iDn1M2bXcB7/YEa5AG27 7Rjp/tsY+lPe6LgCAk7fKF1kwT6x1gDXbUEuf/KgYcl3jKM1zca6u0F33UVZAvc+Dt 24pJA9I8XfQZld8SmEwcMcoWWX52ZWiClLGIrcZs= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 78AC23830B10 for ; Tue, 15 Nov 2022 04:58:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 78AC23830B10 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D017C300089; Tue, 15 Nov 2022 04:58:04 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 03/11] RISC-V: Make mapping symbol checking consistent Date: Tue, 15 Nov 2022 04:52:46 +0000 Message-Id: <6c6c644515c6bc2751062543097eb14ee98e97c8.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536802991755025?= X-GMAIL-MSGID: =?utf-8?q?1749536802991755025?= There were two places where the mapping symbols are checked but had different conditions. - riscv_get_map_state: "$d" or starts with "$x" - riscv_elf_is_mapping_symbols: Starts with either "$x" or "$d" Considering recent mapping symbol proposal, it's better to make symbol checking consistent (whether the symbol _starts_ with "$[xd]"). It only checks prefix "$xrv" (mapping symbol with ISA string) only when the prefix "$x" is matched. opcodes/ChangeLog: * riscv-dis.c (riscv_get_map_state): Change the condition for consistency. --- opcodes/riscv-dis.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index ea45a631a25..d3bd4ceec1e 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -832,16 +832,17 @@ riscv_get_map_state (int n, return false; name = bfd_asymbol_name(info->symtab[n]); - if (strcmp (name, "$x") == 0) - *state = MAP_INSN; - else if (strcmp (name, "$d") == 0) - *state = MAP_DATA; - else if (strncmp (name, "$xrv", 4) == 0) + if (startswith (name, "$x")) { + if (startswith (name + 2, "rv")) + { + riscv_release_subset_list (&riscv_subsets); + riscv_parse_subset (&riscv_rps_dis, name + 2); + } *state = MAP_INSN; - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, name + 2); } + else if (startswith (name, "$d")) + *state = MAP_DATA; else return false; From patchwork Tue Nov 15 04:52:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20187 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2521264wru; Mon, 14 Nov 2022 20:58:56 -0800 (PST) X-Google-Smtp-Source: AA0mqf69nhq+lZ+Tjs93eIXVryBSdqSKYOUpewlrWsRC+43gqZYzE+N3vv/Nlg7tzWsCEHW7VNXg X-Received: by 2002:aa7:d4d3:0:b0:45f:b80f:1fe8 with SMTP id t19-20020aa7d4d3000000b0045fb80f1fe8mr13032517edr.118.1668488335932; Mon, 14 Nov 2022 20:58:55 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488335; cv=none; d=google.com; s=arc-20160816; b=nrauDY6J6/z1Gytvhx9osw47ygRwdqJMIgoTUqtdagQtfNyE/b2qXn0HVZJGCTpKi0 /+6pkEEAOLjF4mZEc7z9f8Nt8UQGKsJomJ/BvViUXxUpPWxyogjcmjsFThkRPz2g0/G6 tV1gFuH4WGrUZTZw4YysR8IWbt4D+n1izEJETmKDaYngxftLS6iaXwTBi67ucorL+Mg+ GIZa20qlpOjSLEI2ZQpa/3LsyIj7FOiz6CApUm0b6nEliqqSGsgarnk6cnnHOYD2atp3 8ee4FVquo8oTZ2mnPDUF76k5nVZDHuNmtbd356WsviPZAaYpp4pJm4vwY2pkgnm/XFSg DhNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=GQRh4n8J1DQh3RBftXPuwECF7e5ZkecXkOX4DGjnfbA=; b=Hiphccb0F7axArlIV86znWtMVnoYPKBTo8Gx3OBCiXBUBNoxUQrGsVQA+Os3xAYZhm aBwDqGDX6lRzQ87vyJa71KZCeZt450bL9n8pFrrB+R1HF6dDG9VZagNRoQPcmSNhDbNT CbeWVUlHFHSF4d1aWWW4Hf3xItN29M4ixQn1sRcu3CNxjIo99RonbJ/maMVIFLU8IeAw YLiF8XST8r8oqGB0HjvfO6icqqWA9ZKOBPeJLUrqmWI8mrDtwobdxmKoiQzhdqNKBEvl Cgh2iyeeWwso4deFZl6TViNvG/BVfvZ6KG+IZ5a6MluDiJgzsTkaIe5eo4nLhQI7JTjY ZlVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=adFaZ0VW; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id wu10-20020a170906eeca00b0078d27c1b499si10910634ejb.500.2022.11.14.20.58.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 20:58:55 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=adFaZ0VW; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CD81C382D3A5 for ; Tue, 15 Nov 2022 04:58:25 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CD81C382D3A5 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488305; bh=GQRh4n8J1DQh3RBftXPuwECF7e5ZkecXkOX4DGjnfbA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=adFaZ0VWGWYO78Gy3C5kivKM/wfXFLJ78VNapiDPg0hmgifcr9seO9kCp5Pjr1D9L hnqjl80VvOcCcyPGe46Vo91iYsXlH2Gd4jmm/musKuHIg4HwxT5lyptBFeGUckakzS SDodZ20G0efFh7zpoOa7E18V+sLbAyuQao2kA3as= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 01E58382EF38 for ; Tue, 15 Nov 2022 04:58:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 01E58382EF38 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 56401300089; Tue, 15 Nov 2022 04:58:15 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 04/11] RISC-V: Split riscv_get_map_state into two steps Date: Tue, 15 Nov 2022 04:52:47 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536825560433114?= X-GMAIL-MSGID: =?utf-8?q?1749536825560433114?= Because mapping symbol optimization would remove riscv_get_map_state function, this commit splits symbol name checking step into a separate function riscv_get_map_state_by_name. Let alone the optimization, splitting the code improves readability. opcodes/ChangeLog: * riscv-dis.c (riscv_get_map_state): Split symbol name checking into a separate function. (riscv_get_map_state_by_name): New. --- opcodes/riscv-dis.c | 41 +++++++++++++++++++++++++++-------------- 1 file changed, 27 insertions(+), 14 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d3bd4ceec1e..3135db30ccd 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -816,6 +816,24 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) return insnlen; } +/* Return new mapping state if a given symbol name is of mapping symbols', + MAP_NONE otherwise. If arch is not NULL and name denotes a mapping symbol + with ISA string, *arch is updated to the ISA string. */ + +static enum riscv_seg_mstate +riscv_get_map_state_by_name (const char *name, const char** arch) +{ + if (startswith (name, "$x")) + { + if (arch && startswith (name + 2, "rv")) + *arch = name + 2; + return MAP_INSN; + } + else if (startswith (name, "$d")) + return MAP_DATA; + return MAP_NONE; +} + /* Return true if we find the suitable mapping symbol, and also update the STATE. Otherwise, return false. */ @@ -824,28 +842,23 @@ riscv_get_map_state (int n, enum riscv_seg_mstate *state, struct disassemble_info *info) { - const char *name; + const char *name, *arch = NULL; /* If the symbol is in a different section, ignore it. */ if (info->section != NULL && info->section != info->symtab[n]->section) return false; - name = bfd_asymbol_name(info->symtab[n]); - if (startswith (name, "$x")) + name = bfd_asymbol_name (info->symtab[n]); + enum riscv_seg_mstate newstate = riscv_get_map_state_by_name (name, &arch); + if (newstate == MAP_NONE) + return false; + *state = newstate; + if (arch) { - if (startswith (name + 2, "rv")) - { - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, name + 2); - } - *state = MAP_INSN; + riscv_release_subset_list (&riscv_subsets); + riscv_parse_subset (&riscv_rps_dis, arch); } - else if (startswith (name, "$d")) - *state = MAP_DATA; - else - return false; - return true; } From patchwork Tue Nov 15 04:52:48 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20192 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3425295dyb; Mon, 14 Nov 2022 21:02:47 -0800 (PST) X-Google-Smtp-Source: AA0mqf6hTOp81x+r5SrHUzD3wxGX3jH2omBBQqm70gmGgWEEPj1tv3YNinbMeuJ1BUOu56Do5XFg X-Received: by 2002:a17:907:cc8a:b0:7ae:f6e8:2502 with SMTP id up10-20020a170907cc8a00b007aef6e82502mr6338692ejc.157.1668488567237; Mon, 14 Nov 2022 21:02:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488567; cv=none; d=google.com; s=arc-20160816; b=cOsRoDjqaJUHSMg1tU0Y2+irOwwoahKCTCr4Y3jtehw8kmhtp7edOHGwJTndmjYggR nlXx3pEQHRJc0XXtNMlNRXqwSmBfebAGfAEQAvCFXN0XwEcSUh6KjwubCbtE78JTGWxX wRy5MAyJHzbzPDgL3mXIrGHs0/Yl7w9eEerKJa3mWDGW77DVdTCauCZBELlJlqQBrLjH Xogjdw17aq4vBTVnbyXk+ta4029pBTHHPDwCYUW0RVMGR1RtvY02Ot4VpJhGhvooBsZb a4SUisGd/Mt9+CLx4Vxy05Q7OkerPVZ8X4mV8SXNciH66memu1orzWwl4jRdRUcjz6dd IX7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=zN0uw+NLIQY6eBUq5ljReYrRgNKJJO6+pILxbE4sqC4=; b=jv91903vdACl2c7+yaC3or5UKMRRihz9Gw2WWANaf9t0RVhy2aOXQOM94o9+cypdaL eilXBPaerQfvg/0+HHeW7n/FmHDFpqZy5GHjiBwR45q0p3X/14oQNkHevlgq9PhVgHFd r0xgW+tJ78kJGdNbdkemB0oPpvVdLpRoIQ5XM2+/BeqWwkaOzOot1Rc5j/yFD0AkcUW6 jozVRqhmQBWqKyjJGqV1ZiX9E64rFvDR9XVDFgIcYtdIaXXEX9YRo2Exo8DUY8M/DHqj DndIDdnuvoJurXkdiABFVgEMZepV8+3FHQMpxvYmSFWE7jp8UMxLrDHSmIl+CG30HVnK w+tg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wnSiSzuH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id wt13-20020a170906ee8d00b0078d1e08f1e5si11097083ejb.919.2022.11.14.21.02.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:02:47 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=wnSiSzuH; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 69EA43947C25 for ; Tue, 15 Nov 2022 05:00:03 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 69EA43947C25 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488403; bh=zN0uw+NLIQY6eBUq5ljReYrRgNKJJO6+pILxbE4sqC4=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=wnSiSzuHqENp9y3qyr1BNlj9XNb5sRZxz1/f4InnPQRKHISOoLLOQinsHaOzricwu vv0AjP01YwcSe+y4YgzweLOvUA+LE5oaQdKo0mvdlgPaRJoBL11Q6lD3vcM2xU6HKH 1hdsqpxDQB8MOhX8TC5DD2MJUtOHOtkalf7txPNw= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 79F0D382D39A for ; Tue, 15 Nov 2022 04:58:27 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 79F0D382D39A Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D0F21300089; Tue, 15 Nov 2022 04:58:25 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 05/11] RISC-V: One time CSR hash table initialization Date: Tue, 15 Nov 2022 04:52:48 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537067859008886?= X-GMAIL-MSGID: =?utf-8?q?1749537067859008886?= The current disassembler intends to initialize the CSR hash table when CSR name parsing is required at the first time. This is managed by a function- scope static variable init_csr but... there's a problem. It's never set to true. Because of this issue, current disassembler actually initializes the CSR hash table every time when CSR name parsing is required. This commit sets init_csr to true once the CSR hash table is initialized. It is expected to have about 30% performance improvements alone when thousands of only CSR instructions are disassembled (CSR instructions are rare in general so real world performance improvement is not that high). This commit alone will not affect real world performance that much but after the efficient opcode hash is implemented, it will be much effective (sometimes >x10 effect than this commit alone) so that even some regular programs can benefit from it. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Make sure that CSR hash table initialization occurs only once. --- opcodes/riscv-dis.c | 1 + 1 file changed, 1 insertion(+) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3135db30ccd..ec38bed747a 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -564,6 +564,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info DECLARE_CSR (name, num, class, define_version, abort_version) #include "opcode/riscv-opc.h" #undef DECLARE_CSR + init_csr = true; } if (riscv_csr_hash[csr] != NULL) From patchwork Tue Nov 15 04:52:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20193 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3425907dyb; Mon, 14 Nov 2022 21:04:08 -0800 (PST) X-Google-Smtp-Source: AA0mqf5OaTmz+mOGOlqojJztrWc/7mF8s1amLy95bL7iZMTq8EoBZs+VIx52LFF1qhpypLvSGjlQ X-Received: by 2002:aa7:cdc8:0:b0:463:f8aa:d2bf with SMTP id h8-20020aa7cdc8000000b00463f8aad2bfmr13704354edw.358.1668488648191; Mon, 14 Nov 2022 21:04:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488648; cv=none; d=google.com; s=arc-20160816; b=OZd6OUshQlM+delcIz0ZWDlAV3GZOVeDB0uM1H6K+mY1lVYB8tQ26/ESSwPaJESzCJ oodHj44jMFOG7vYB0MOuwp0aaBYMHScP3/O1jXITI1zKYLBLNH3+iCvm73/gyWZl22n4 IjTgsj63svJif/YHIez4Hw1yY0D9JzOxQ4NnnAI0/du07djfYRqxcOBO1JiVoumBZ2TL ocKpbTrD4FkJ+UHI/wA6h9E8jI2ZNZ6mHnv7XlDQQN8t9aAkxKqQg6XFUJ7nhkqfW54H Z9u/RqwvUqQxQ0pxJB8E/OzlEQEKYoKraS8RFtU9mwTs5OLgvOpIENzyFEttjYI/J2Ig 0rUA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=6kSYCSmk24BBvknILrjTyXlbPsCkfQkwLlk6z02RMK8=; b=FQIit4MvkOfaP6G5G91llQx2E7kmey13uE0YReWrPKV9zI9PC3io21hKdm4kXGqvWj AQQWdqKmnMj+OWfhM0vhvIOJ6GctqvUk6Ys3TrMounmFFQRMuNnoHyW2QZFHk3BVU2wf sLOx6vb0o959hpHMk7iVfLJey9XFPQ+715AjSBM/Ld5QIn9mDMHkR0n0780WKUChJ7ui cFKZSWi9cYOIgt5v7zJfmsgcP+56Uwj08AEy5EJBz7JyzZhZs5edpXwLQFaHRBfq/Srw U26Sh2elXazlXNfgZDkFhG9zw/x8td/niwjl3EIVTYNd7DUQsQyU4sOSvx2+3IvT0XPo Xe0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=KkPwBNSV; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id nd32-20020a17090762a000b007addff99f09si9775243ejc.1004.2022.11.14.21.04.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:04:08 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=KkPwBNSV; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB57E3887F47 for ; Tue, 15 Nov 2022 05:01:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB57E3887F47 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488467; bh=6kSYCSmk24BBvknILrjTyXlbPsCkfQkwLlk6z02RMK8=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=KkPwBNSVTgyjtHdPaJDgl7xIBWAnMW1fGTE2639Yjivfy6UbEazN5cQhx0Yi/wmYc rn9XfDZHm3q/O2L2MsWR9PiJf1P/chB49U3tGOSsTpIba1XhGCkGKQBZtJspdh1aU3 hebyG7SHniMRy6EyNX4AHNw+oCInaQ4qY/LW8fnA= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id F2BE43889E12 for ; Tue, 15 Nov 2022 04:58:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F2BE43889E12 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 54AF4300089; Tue, 15 Nov 2022 04:58:36 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 06/11] RISC-V: Use static xlen on ADDIW sequence Date: Tue, 15 Nov 2022 04:52:49 +0000 Message-Id: <9734125736efc8b63be17df87d38cf24bb14a156.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537152408723609?= X-GMAIL-MSGID: =?utf-8?q?1749537152408723609?= Because XLEN for the disassembler is computed and stored in the xlen variable, this commit replaces uses of info->mach with xlen (when testing for ADDIW / C.ADDIW address sequence). Not just we used two ways to determine current XLEN, info->mach and xlen, xlen is going to be more important in the future commits. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Use xlen variable to determine whether XLEN is larger than 32. --- opcodes/riscv-dis.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index ec38bed747a..d4a6cdd4d4e 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -261,7 +261,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'j': if (((l & MASK_C_ADDI) == MATCH_C_ADDI) && rd != 0) maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 0); - if (info->mach == bfd_mach_riscv64 + if (xlen > 32 && ((l & MASK_C_ADDIW) == MATCH_C_ADDIW) && rd != 0) maybe_print_address (pd, rd, EXTRACT_CITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", @@ -461,7 +461,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info if (((l & MASK_ADDI) == MATCH_ADDI && rs1 != 0) || (l & MASK_JALR) == MATCH_JALR) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 0); - if (info->mach == bfd_mach_riscv64 + if (xlen > 32 && ((l & MASK_ADDIW) == MATCH_ADDIW) && rs1 != 0) maybe_print_address (pd, rs1, EXTRACT_ITYPE_IMM (l), 1); print (info->stream, dis_style_immediate, "%d", From patchwork Tue Nov 15 04:52:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20191 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3424610dyb; Mon, 14 Nov 2022 21:01:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf6HHd5130T/M5qjNkkO5bAD2U2quYWqpgJPXJGgN61T9yUcLQMady5UHu7CvM08vjlu8PS0 X-Received: by 2002:a17:906:c259:b0:7ae:df97:a033 with SMTP id bl25-20020a170906c25900b007aedf97a033mr9699028ejb.344.1668488485394; Mon, 14 Nov 2022 21:01:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488485; cv=none; d=google.com; s=arc-20160816; b=t2WUSfHLX4RjZyQ8CbKxfxg1iXP1HDkrzQ9Rn5FQU0KaSlvbcOEm1ZWCJEi6ErdPjq +WRJz3dWuToHPQ9XPurBzSrvbRLHCsAIRUrApdZoUQW4w6Gl9umD52mbt86CYc6k2aWn YjUDi9qoREuClo4l6vHuSmgVOsxoyOIRE8jRdbRNI1c3HCqSpdlObwu7KoUxd4bjvoWa oSRmmT/tJez17x3b4G9fjeV0EHkPzYITOLHPPdJP23lzAZYkpDLwvtjNe1AFKVpnfBop EF5SchIdH6F73Bi27ZFz+WEk/Rn2g5vAkemagG5fd3QMSgErHo7/zV3gJLef8g4T2Mdf YJoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=zdcFI9JK5wNabYnh9BDHYatvFmERdrEPLGNJILnFAIA=; b=pf/tYuVodaupfeatG+P3MvlvfuulbEkxpARUcX6jgKGjtDTGlBGrvMDzjaSQzTfNcp AywTUAjA0zKnbc1cXzZwO2qSqSfQGhR564jnja1iT7hMr4JietFpKe8UNKElIIlrleLq dYLoES16btOpJcZ//AHck8ebWwAJJdQAHUzjtPhFlLDdnAx26XTwJbGILHZC+C4emiAx 7zP1PbGezJ9JpqvQ4MYWrt+lp2qtaTQikLSh4Pqp5brRC3WnWLRyFvrcKNbrWxrSJtKE yvqu1+Oace2cSEQtpb+RazMGKFibwYKt4tfwQbip5Mowr+dKUKbrKuZ6cHAOHetyGm8h 25ww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=eMUgiRZN; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id mp36-20020a1709071b2400b0078d450cbb02si11681076ejc.452.2022.11.14.21.01.25 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:01:25 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=eMUgiRZN; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BA67538A4838 for ; Tue, 15 Nov 2022 04:59:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BA67538A4838 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488370; bh=zdcFI9JK5wNabYnh9BDHYatvFmERdrEPLGNJILnFAIA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=eMUgiRZNE6uqHUa67ODS9W+sUxv4X3HbWL0x8Q5JKmTjQazP2Fnuh0ZGrbg1sVsS3 TlV1I2HO56zugu2XRw4lixFOybXZ+MPFHWOm1xe6AupXQSDQLQWqxCNhd/r86nyqF2 4m+EWA9JzRIzAeIEPTOVMPptRwfg3jLJWG8ho3pY= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 7F763382EF3D for ; Tue, 15 Nov 2022 04:58:48 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7F763382EF3D Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D0AF9300089; Tue, 15 Nov 2022 04:58:46 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 07/11] opcodes/riscv-dis.c: Add form feed for separation Date: Tue, 15 Nov 2022 04:52:50 +0000 Message-Id: <34dbd0c82de0af284887a3bff649c8c53d67e752.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536982044941449?= X-GMAIL-MSGID: =?utf-8?q?1749536982044941449?= This is a general tidying commit. opcodes/ChangeLog: * riscv-dis.c: Add lines with form feed to separate functional sections. --- opcodes/riscv-dis.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d4a6cdd4d4e..d9c16dad615 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -72,7 +72,7 @@ static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; - + /* Set default RISC-V disassembler options. */ @@ -174,6 +174,7 @@ parse_riscv_dis_options (const char *opts_in) free (opts); } + /* Print one argument from an array. */ From patchwork Tue Nov 15 04:52:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20190 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3424381dyb; Mon, 14 Nov 2022 21:01:04 -0800 (PST) X-Google-Smtp-Source: AA0mqf5O2/viroqEwZHheLsFT6bfZ+dQbyXGJERZMEj2jyTECUY55sFELQLHAcCqduPYiRyoKf/E X-Received: by 2002:aa7:de88:0:b0:458:b42e:46e6 with SMTP id j8-20020aa7de88000000b00458b42e46e6mr13766419edv.375.1668488463879; Mon, 14 Nov 2022 21:01:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488463; cv=none; d=google.com; s=arc-20160816; b=laWnhFwmbeAd3XT5Z8wU7e89SPqDecJFcAjHEfpy56Vy6ZVNzDv43wLmjBoUAGHAL7 oy5ucaqkpmeqRTyo0RhZGYwgpKl/uBAkNIkt9L2FeROciOkQZ4nSCXpUY4+cTPEU0jPx KmjvWaFiGhGGwd9xrhvdLVY8P+w3GE1k4BytL/BL41wD1DE38hp+Ae/YLSxuznC0hHSc c6pz6JUK344z3wqH6PLpEod+TRTzy3McROqhMhj4SGNqfy5t7p34L+ioaVB5/Ei4UWsS ar8vdk6hpW65IUzVkgLGLJ+eJ1zj3T5c3u2kcqyUL5EWyvagkY+44b8N5OMZ00yuWhrK t1LQ== ARC-Message-Signature: i=1; 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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id j10-20020a05640211ca00b00454599abf52si12682699edw.92.2022.11.14.21.01.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:01:03 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=AtplthCW; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 7D319382EF28 for ; Tue, 15 Nov 2022 04:59:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7D319382EF28 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488360; bh=rH8mxvEGOFghryGPjYWDBEhxXyhVT3aW5oEj3Y+hF9s=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=AtplthCWcpKUMNEB6HMog+SwGIPHc7stHnxUVR9ImrEfwyUVnnatTdBTHUSd3wpEg Do0t9NzP4Rk+5WqpR2VQWq1KWa3pThnbgN5KKVyPhTPntEU1VNif3yZKK1cKZ2cICi cm1WKiSaa+XuksGkvZUj6pTwb95TpmQv9kxqnBDQ= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 07538382D39F for ; Tue, 15 Nov 2022 04:58:59 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 07538382D39F Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 5A277300089; Tue, 15 Nov 2022 04:58:57 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 08/11] RISC-V: Split match/print steps on disassembler Date: Tue, 15 Nov 2022 04:52:51 +0000 Message-Id: <1352fb8c63539727204df94651f371ed09bbce4c.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536959919471200?= X-GMAIL-MSGID: =?utf-8?q?1749536959919471200?= For further optimization and more disassembler features, we may need to change the core RISC-V instruction matching. For this purpose, it is inconvenient to have "match" and "print" steps in the same loop. This commit rewrites riscv_disassemble_insn function so that we store matched_op for matching RISC-V opcode and then print it (if not NULL). Although it looks a bit inefficient, it also lowers the indent of opcode matching loop to clarify the opcode matching changes on the next optimization commit. Unfortunately, this commit alone will impose some performance penalty (<5% on most cases but sometimes about 15% worse) but it can be easily paid back by other optimizations. opcodes/ChangeLog: * riscv-dis.c (riscv_disassemble_insn): Split instruction handling to two separate steps - opcode matching and printing. --- opcodes/riscv-dis.c | 151 +++++++++++++++++++++++--------------------- 1 file changed, 79 insertions(+), 72 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index d9c16dad615..316c6c97607 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -646,7 +646,7 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info static int riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) { - const struct riscv_opcode *op; + const struct riscv_opcode *op, *matched_op; static bool init = false; static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; struct riscv_private_data *pd; @@ -702,85 +702,92 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) info->target = 0; info->target2 = 0; + matched_op = NULL; op = riscv_hash[OP_HASH_IDX (word)]; - if (op != NULL) + + /* If XLEN is not known, get its value from the ELF class. */ + if (info->mach == bfd_mach_riscv64) + xlen = 64; + else if (info->mach == bfd_mach_riscv32) + xlen = 32; + else if (info->section != NULL) { - /* If XLEN is not known, get its value from the ELF class. */ - if (info->mach == bfd_mach_riscv64) - xlen = 64; - else if (info->mach == bfd_mach_riscv32) - xlen = 32; - else if (info->section != NULL) - { - Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); - xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; - } + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } - /* If arch has the Zfinx extension, replace FPR with GPR. */ - if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names; - else - riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi ? - riscv_fpr_names_abi : riscv_fpr_names_numeric; + /* If arch has the Zfinx extension, replace FPR with GPR. */ + if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) + riscv_fpr_names = riscv_gpr_names; + else + riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi + ? riscv_fpr_names_abi + : riscv_fpr_names_numeric; - for (; op->name; op++) - { - /* Does the opcode match? */ - if (! (op->match_func) (op, word)) - continue; - /* Is this a pseudo-instruction and may we print it as such? */ - if (no_aliases && (op->pinfo & INSN_ALIAS)) - continue; - /* Is this instruction restricted to a certain value of XLEN? */ - if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) - continue; - /* Is this instruction supported by the current architecture? */ - if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) - continue; - - /* It's a match. */ - (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, - "%s", op->name); - print_insn_args (op->args, word, memaddr, info); - - /* Try to disassemble multi-instruction addressing sequences. */ - if (pd->to_print_addr) - { - info->target = pd->print_addr; - (*info->fprintf_styled_func) - (info->stream, dis_style_comment_start, " # "); - (*info->print_address_func) (info->target, info); - pd->to_print_addr = false; - } + for (; op && op->name; op++) + { + /* Does the opcode match? */ + if (!(op->match_func) (op, word)) + continue; + /* Is this a pseudo-instruction and may we print it as such? */ + if (no_aliases && (op->pinfo & INSN_ALIAS)) + continue; + /* Is this instruction restricted to a certain value of XLEN? */ + if ((op->xlen_requirement != 0) && (op->xlen_requirement != xlen)) + continue; + /* Is this instruction supported by the current architecture? */ + if (!riscv_multi_subset_supports (&riscv_rps_dis, op->insn_class)) + continue; - /* Finish filling out insn_info fields. */ - switch (op->pinfo & INSN_TYPE) - { - case INSN_BRANCH: - info->insn_type = dis_branch; - break; - case INSN_CONDBRANCH: - info->insn_type = dis_condbranch; - break; - case INSN_JSR: - info->insn_type = dis_jsr; - break; - case INSN_DREF: - info->insn_type = dis_dref; - break; - default: - break; - } + matched_op = op; + break; + } - if (op->pinfo & INSN_DATA_SIZE) - { - int size = ((op->pinfo & INSN_DATA_SIZE) - >> INSN_DATA_SIZE_SHIFT); - info->data_size = 1 << (size - 1); - } + if (matched_op != NULL) + { + /* There is a match. */ + op = matched_op; + + (*info->fprintf_styled_func) (info->stream, dis_style_mnemonic, + "%s", op->name); + print_insn_args (op->args, word, memaddr, info); - return insnlen; + /* Try to disassemble multi-instruction addressing sequences. */ + if (pd->to_print_addr) + { + info->target = pd->print_addr; + (*info->fprintf_styled_func) (info->stream, dis_style_comment_start, + " # "); + (*info->print_address_func) (info->target, info); + pd->to_print_addr = false; } + + /* Finish filling out insn_info fields. */ + switch (op->pinfo & INSN_TYPE) + { + case INSN_BRANCH: + info->insn_type = dis_branch; + break; + case INSN_CONDBRANCH: + info->insn_type = dis_condbranch; + break; + case INSN_JSR: + info->insn_type = dis_jsr; + break; + case INSN_DREF: + info->insn_type = dis_dref; + break; + default: + break; + } + + if (op->pinfo & INSN_DATA_SIZE) + { + int size = ((op->pinfo & INSN_DATA_SIZE) >> INSN_DATA_SIZE_SHIFT); + info->data_size = 1 << (size - 1); + } + + return insnlen; } /* We did not find a match, so just print the instruction bits. */ From patchwork Tue Nov 15 04:52:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20189 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3424327dyb; Mon, 14 Nov 2022 21:00:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf5MVE8n/GEckWDOcOgI3mmiK/plsVfcnU+cW1bzMP4R0AfTiM7fl+T5CE/gwDuArQ65hK6G X-Received: by 2002:a05:6402:5cf:b0:462:845:ba98 with SMTP id n15-20020a05640205cf00b004620845ba98mr13343544edx.12.1668488459057; Mon, 14 Nov 2022 21:00:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488459; cv=none; d=google.com; s=arc-20160816; b=pk4dens6A7J3o6thGRqhUNMQs0J7Oqdv8jxfBcFnQ4G9TQAeBfVMvE5crJFvR6NFGA OxQcxUuzxuoFpxV+1ezZ/BpvQJQPxex0YnCOBCsRVIisnRs1r9ZGUz+bvMoWgES+ZKFY bIgJLeMz0af+dLa+VK76WLpYH2JQtaos47fcPrCt6U+o8hlNhjCBVtkd4QOPJuQ0x3YT fv9oeRTCuez9s8+Kv47AqLdD1hzGy3fg9mw5jilXSYXZSkGHkWXwkQmtcf5SeDiYqAUc id906impAv2S0y/SeUPFWSfAFTTZGGTDP7PyhchtT0NnhYcwH2+dJZFXdc26bsZH+fLU hNqQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=MwhMjvwqPE8K+BtqsEf7oahoAH6kD0V9tM9JHXWR+t0=; b=NKKYEDg+KIom4b35eMHuDpre5FYBBHvanPoPXUndwhZNa75mGLQ2mVg47PFEIwj8Ky sZ1f8eN4LM48yclaiCfUNgN4EjuYy8HBZG8Unxu8MFuJFWhwLVpoKC0EqK4ZqeBq8UZ0 UyxXVO4vDnT1to39756i07BcMmLsEhTKSyJA42E2AWX2KzXENuQEXqiw8a7gg0cD5aan zm3bM/Cjg7glqFaZilim2NZpHbRlMq7yGedbTUeB2RE3SciWGRQs/UU64ZuTz/p/fFp9 qsXEA11W7MfrwWuJ1L2Y/fPMMrjWq99fvvlygjEs6Ym+uEsYCpC5cUUBI6DmL1GcjeYa Uv8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OhjfAH2v; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id v14-20020a056402348e00b00461e63fe88fsi12538452edc.596.2022.11.14.21.00.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:00:59 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=OhjfAH2v; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 88B8E389839F for ; Tue, 15 Nov 2022 04:59:18 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 88B8E389839F DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488358; bh=MwhMjvwqPE8K+BtqsEf7oahoAH6kD0V9tM9JHXWR+t0=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=OhjfAH2vPjVY2cADbxsE/A3WXhRxCIX1lbE4SzeBYPxmzPR3eHL6uSfWz4gACFNSe NOwHrFUq7iJmisX4lJgsit3izTvIsYpe1rdmXrEX3w3MUPBQlfL19lF+buIQHhO6LI sZeIKx8DVD+eI3rzUM0FvxAE1yT6G0weqzH+shZo= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 7ED223885C36 for ; Tue, 15 Nov 2022 04:59:09 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7ED223885C36 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id D700A300089; Tue, 15 Nov 2022 04:59:07 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 09/11] RISC-V: Reorganize disassembler state initialization Date: Tue, 15 Nov 2022 04:52:52 +0000 Message-Id: <12cd8820841f695708875206b6461b6322c74428.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749536954487615344?= X-GMAIL-MSGID: =?utf-8?q?1749536954487615344?= The current disassembler repeatedly checks current state per instruction: - Whether riscv_gpr_names is initialized to a non-NULL value - Whether the Zfinx extension is available - Whether the hash table is initialized ... but they are not frequently changed. riscv_gpr_names is initialized to a non-NULL value when - The first disassembler option is specified, or - Not initialized with disassembler options (in the first print_insn_riscv function call). We can safely initialize the default disassembler options prior to the print_insn_riscv function call and this per-instruction checking of riscv_gpr_names can be safely removed. The opcode hash table initialization will be taken care with a later commit. To group disassembler state initialization, this commit utilizes the disassemble_init_for_target function. As a side effect, this will also fix a potential issue when disassembler options is set and then unset on GDB. This idea is based on opcodes/ppc-dis.c and opcodes/wasm32-dis.c. New callback function init_riscv_dis_state_for_arch_and_options is called when either the architecture string or an option is possibly changed. We can now group the disassembler state initialization together. It makes state initialization clearer and makes further changes easier. In performance perspective, this commit has various effects (-5% to 6%). However, this commit makes implementing large optimizations easier as well as "RISC-V: Split match/print steps on disassembler". include/ChangeLog: * dis-asm.h (disassemble_init_riscv): Add declaration of disassemble_init_riscv. opcodes/ChangeLog: * disassemble.c (disassemble_init_for_target): Call disassemble_init_riscv to group state initialization together. * riscv-dis.c (xlen_by_mach, xlen_by_elf): New variables to store environment-inferred XLEN. (is_numeric): New. Instead of directly setting riscv_{gpr,fpr}_names, use this to store an option. (update_riscv_dis_xlen): New function to set actual XLEN from xlen_by_mach and xlen_by_elf variables. (init_riscv_dis_state_for_arch_and_options): New callback function called when either the architecture or an option is changed. Set riscv_{gpr,fpr}_names here. (set_default_riscv_dis_options): Initialize is_numeric instead of riscv_gpr_names and riscv_fpr_names. (parse_riscv_dis_option_without_args): When the "numeric" option is specified, write to is_numeric instead of register names. (parse_riscv_dis_options): Suppress setting the default options here and let disassemble_init_riscv to initialize them. (riscv_disassemble_insn): Move probing Zfinx and setting XLEN portions to init_riscv_dis_state_for_arch_and_options and update_riscv_dis_xlen. (riscv_get_map_state): If a mapping symbol with ISA string is suitable, call init_riscv_dis_state_for_arch_and_options function to update disassembler state. (print_insn_riscv): Update XLEN only if we haven't guessed correct XLEN for the disassembler. Stop checking disassembler options for every instruction and let disassemble_init_riscv to parse options. (riscv_get_disassembler): Call init_riscv_dis_state_for_arch_and_options because the architecture string is updated here. (disassemble_init_riscv): New function to initialize the structure, reset/guess correct XLEN and reset/parse disassembler options. --- include/dis-asm.h | 1 + opcodes/disassemble.c | 2 +- opcodes/riscv-dis.c | 112 +++++++++++++++++++++++++++++------------- 3 files changed, 79 insertions(+), 36 deletions(-) diff --git a/include/dis-asm.h b/include/dis-asm.h index 4921c040710..11537b432ff 100644 --- a/include/dis-asm.h +++ b/include/dis-asm.h @@ -393,6 +393,7 @@ extern bool arm_symbol_is_valid (asymbol *, struct disassemble_info *); extern bool csky_symbol_is_valid (asymbol *, struct disassemble_info *); extern bool riscv_symbol_is_valid (asymbol *, struct disassemble_info *); extern void disassemble_init_powerpc (struct disassemble_info *); +extern void disassemble_init_riscv (struct disassemble_info *); extern void disassemble_init_s390 (struct disassemble_info *); extern void disassemble_init_wasm32 (struct disassemble_info *); extern void disassemble_init_nds32 (struct disassemble_info *); diff --git a/opcodes/disassemble.c b/opcodes/disassemble.c index 0a8f2da629f..704fb476ea9 100644 --- a/opcodes/disassemble.c +++ b/opcodes/disassemble.c @@ -717,7 +717,7 @@ disassemble_init_for_target (struct disassemble_info * info) #endif #ifdef ARCH_riscv case bfd_arch_riscv: - info->symbol_is_valid = riscv_symbol_is_valid; + disassemble_init_riscv (info); info->created_styled_output = true; break; #endif diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 316c6c97607..76387efbe4b 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -35,6 +35,12 @@ /* Current XLEN for the disassembler. */ static unsigned xlen = 0; +/* XLEN as inferred by the machine architecture. */ +static unsigned xlen_by_mach = 0; + +/* XLEN as inferred by ELF header. */ +static unsigned xlen_by_elf = 0; + /* Default ISA specification version (constant as of now). */ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; @@ -72,6 +78,48 @@ static const char * const *riscv_fpr_names; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; + +/* If set, disassemble with numeric register names. */ +static bool is_numeric = false; + + +/* Guess and update current XLEN. */ + +static void +update_riscv_dis_xlen (struct disassemble_info *info) +{ + /* Set XLEN with following precedence rules: + 1. BFD machine architecture set by either: + a. -m riscv:rv[32|64] option (GDB: set arch riscv:rv[32|64]) + b. ELF class in actual ELF header (only on RISC-V ELF) + This is only effective if XLEN-specific BFD machine architecture is + chosen. If XLEN-neutral (like riscv), BFD machine architecture is + ignored on XLEN selection. + 2. ELF class in dummy ELF header. */ + if (xlen_by_mach != 0) + xlen = xlen_by_mach; + else if (xlen_by_elf != 0) + xlen = xlen_by_elf; + else if (info != NULL && info->section != NULL) + { + Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); + xlen = xlen_by_elf = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; + } +} + +/* Initialization (for arch and options). */ + +static void +init_riscv_dis_state_for_arch_and_options (void) +{ + /* Set GPR register names to disassemble. */ + riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi; + /* Set FPR register names to disassemble. */ + riscv_fpr_names + = !riscv_subset_supports (&riscv_rps_dis, "zfinx") + ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi) + : riscv_gpr_names; +} /* Set default RISC-V disassembler options. */ @@ -79,9 +127,8 @@ static bool no_aliases = false; static void set_default_riscv_dis_options (void) { - riscv_gpr_names = riscv_gpr_names_abi; - riscv_fpr_names = riscv_fpr_names_abi; no_aliases = false; + is_numeric = false; } /* Parse RISC-V disassembler option (without arguments). */ @@ -92,10 +139,7 @@ parse_riscv_dis_option_without_args (const char *option) if (strcmp (option, "no-aliases") == 0) no_aliases = true; else if (strcmp (option, "numeric") == 0) - { - riscv_gpr_names = riscv_gpr_names_numeric; - riscv_fpr_names = riscv_fpr_names_numeric; - } + is_numeric = true; else return false; return true; @@ -163,8 +207,6 @@ parse_riscv_dis_options (const char *opts_in) { char *opts = xstrdup (opts_in), *opt = opts, *opt_end = opts; - set_default_riscv_dis_options (); - for ( ; opt_end != NULL; opt = opt_end + 1) { if ((opt_end = strchr (opt, ',')) != NULL) @@ -705,25 +747,6 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) matched_op = NULL; op = riscv_hash[OP_HASH_IDX (word)]; - /* If XLEN is not known, get its value from the ELF class. */ - if (info->mach == bfd_mach_riscv64) - xlen = 64; - else if (info->mach == bfd_mach_riscv32) - xlen = 32; - else if (info->section != NULL) - { - Elf_Internal_Ehdr *ehdr = elf_elfheader (info->section->owner); - xlen = ehdr->e_ident[EI_CLASS] == ELFCLASS64 ? 64 : 32; - } - - /* If arch has the Zfinx extension, replace FPR with GPR. */ - if (riscv_subset_supports (&riscv_rps_dis, "zfinx")) - riscv_fpr_names = riscv_gpr_names; - else - riscv_fpr_names = riscv_gpr_names == riscv_gpr_names_abi - ? riscv_fpr_names_abi - : riscv_fpr_names_numeric; - for (; op && op->name; op++) { /* Does the opcode match? */ @@ -867,6 +890,7 @@ riscv_get_map_state (int n, { riscv_release_subset_list (&riscv_subsets); riscv_parse_subset (&riscv_rps_dis, arch); + init_riscv_dis_state_for_arch_and_options (); } return true; } @@ -1063,14 +1087,9 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) enum riscv_seg_mstate mstate; int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); - if (info->disassembler_options != NULL) - { - parse_riscv_dis_options (info->disassembler_options); - /* Avoid repeatedly parsing the options. */ - info->disassembler_options = NULL; - } - else if (riscv_gpr_names == NULL) - set_default_riscv_dis_options (); + /* Guess and update XLEN if we haven't determined it yet. */ + if (xlen == 0) + update_riscv_dis_xlen (info); mstate = riscv_search_mapping_symbol (memaddr, info); @@ -1132,9 +1151,32 @@ riscv_get_disassembler (bfd *abfd) riscv_release_subset_list (&riscv_subsets); riscv_parse_subset (&riscv_rps_dis, default_arch); + init_riscv_dis_state_for_arch_and_options (); return print_insn_riscv; } +/* Initialize disassemble_info and parse options. */ + +void +disassemble_init_riscv (struct disassemble_info *info) +{ + info->symbol_is_valid = riscv_symbol_is_valid; + /* Clear previous XLEN and guess by mach. */ + xlen = 0; + xlen_by_mach = 0; + xlen_by_elf = 0; + if (info->mach == bfd_mach_riscv64) + xlen_by_mach = 64; + else if (info->mach == bfd_mach_riscv32) + xlen_by_mach = 32; + update_riscv_dis_xlen (info); + /* Parse disassembler options. */ + set_default_riscv_dis_options (); + if (info->disassembler_options != NULL) + parse_riscv_dis_options (info->disassembler_options); + init_riscv_dis_state_for_arch_and_options (); +} + /* Prevent use of the fake labels that are generated as part of the DWARF and for relaxable relocations in the assembler. */ From patchwork Tue Nov 15 04:52:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20194 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3426205dyb; Mon, 14 Nov 2022 21:04:53 -0800 (PST) X-Google-Smtp-Source: AA0mqf5u9ccWcmzt0rdwIunAJdko5ZLuxd56b39LAxr+W03fBa8SNRpAM/lbyAvktTd5QOY1J1xO X-Received: by 2002:a17:906:858a:b0:7ae:63e3:bfc4 with SMTP id v10-20020a170906858a00b007ae63e3bfc4mr12689607ejx.348.1668488692854; Mon, 14 Nov 2022 21:04:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488692; cv=none; d=google.com; s=arc-20160816; b=HILoerP2PJr76atiJGQdeZ7PQLpAEiaaVvFWiyK9ocnJvchmhoZXH73SCKYDXEX5K3 mojq6L9seqWdaH02j/RtxFdaG/K0xaC+iBfsNCFjHam5b7J5gOWJig4/L6ZvCQfkIB1w HDc3hXIdRw+EU3ydKRsMkvTIQWnoiUOvxbcojz4n1EmOXH8yfyxNuV2MZMDmkvSIUoI5 Fvz8Hh5DN1G8lx+jvwbdC/MX3W0brFvqX1ERkoCogrSE4g473xIlJ/AHoF4mEx/e1pJe Pjx/fKXdfCc4MwOwRDpG8mKCYHsmP3InN2RmrquKRUCTpvQddhL0sH9wie5CYqio2fkR mHCg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=79z9+PQNTYNOci/p/agO3Q48ACwR7FjtemhnOl0D4iA=; b=MH/n4MoY7yWuYza8AOUYnnerop5/MHzJB4oJnyKQVr21oPUDMTXVOovWR4molfLUUz xxg2U3CSZn7HWrXT3uGoYl7PXArm0d7zzL6ExIkFeDXb98xsEpOMxwJBs/J93P2Rt4Cq o/0YL++puNJwYWcj0Xp0bvip87vzmeu3S/sJbNUCIcY9IUdOeJWo7WryFBeMPGeCRexq 8Ki9awEp2WjzNuSVi740rZzP9O2hyIvnozXd8kaLWxUFBtu0xHm7RAqXhcUVqpt9PmzA yxGzB37FnXsdzjyqupBtMoNcHjaZmY2vTRG4l+6cgyJMiHODNi/dJxWausYWkWpRny1K JFAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BNZPzlYI; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id k9-20020a17090646c900b0073dc32ccd9fsi2984776ejs.104.2022.11.14.21.04.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:04:52 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=BNZPzlYI; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 0D005388B6A7 for ; Tue, 15 Nov 2022 05:02:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 0D005388B6A7 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488531; bh=79z9+PQNTYNOci/p/agO3Q48ACwR7FjtemhnOl0D4iA=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=BNZPzlYI7tcR0LXwbA0PeAuTl3Ydqygzk36zvH8f3B1RO3UZLFP9WO+erAbk3BdMC oQvZkZcPFmUJi5QyAdX5b5xGxrFHlm4WiIaIYgmg+bO4d+ajrKWiFdA2nMS93MFVeq ps3PFPCYIKnhZecb1ZY/wvLJvIbgzdNbaEMYbLwk= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender.a4lg.com [153.120.152.154]) by sourceware.org (Postfix) with ESMTPS id 0ED223899421 for ; Tue, 15 Nov 2022 04:59:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0ED223899421 Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id 60A66300089; Tue, 15 Nov 2022 04:59:18 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 10/11] RISC-V: Reorganize arch-related initialization and management Date: Tue, 15 Nov 2022 04:52:53 +0000 Message-Id: <6aade17e12ce2a928d044d9f148c874cf9922da8.1668487922.git.research_trasio@irq.a4lg.com> In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537199887855908?= X-GMAIL-MSGID: =?utf-8?q?1749537199887855908?= objdump reuses the disassembler function returned by the disassembler function. That's good and benefits well from various optimizations. However, by default, GDB (default_print_insn in gdb/arch-utils.c) assumes that the disassembler function logic is simple and calls that function for every instruction to be disassembled. This is clearly a waste of time because it probes BFD (ELF information) and re-initializes riscv_rps_dis for every instruction. After the support of mapping symbol with ISA string with commit 40f1a1a4564b ("RISC-V: Output mapping symbols with ISA string."), this kind of per- instruction initialization of riscv_rps_dis can also occur on ELF files with mapping symbol + ISA string (in riscv_get_map_state function). It can be worse if the object is assembled using Binutils commit 0ce50fc900a5 ("RISC-V: Always generate mapping symbols at the start of the sections.") or later. To avoid repeated initialization, this commit - Caches the default / override architectures (in two "contexts") and - enables switching between them. riscv_dis_arch_context_t and new utility functions are defined for this purpose. We still have to read the ".riscv.attributes" section on every instruction on GDB but at least the most time-consuming part (updating the actual architecture from the architecture string) is avoided. Likewise, we still have to probe whether we have to update the architecture for every instruction with a mapping symbol with ISA string is suitable but at least we don't actually update the architecture unless necessary (either context itself or the ISA string of the current context is changed). This commit improves the disassembler performance well in those situations: - When long "disas" command is used on GDB - When ELF files with mapping symbols + ISA string is used This commit now implements new mapping symbol handling ("$x" means revert to the previous architecture [with "$x+arch"] if exists, otherwise revert to the default one usually read from an ELF attribute), the recent consensus made by Kito and Nelson. On the benchmark using GDB batch files, the author measured significant performance improvements (35-96% on various big RISC-V programs). Unfortunately, on interactive usecases of GDB, this improvement is rarely observable since we don't usually disassemble such a big chunk at once and the current disassembler is not very slow. On the benchmark using unstripped ELF files with mapping symbols + ISA string "$xrv...", performance improvements are significant and easily observable in the real world (150%-264% performance improvments). Aside from optimization, this commit, along with "RISC-V: Reorganize disassembler state initialization", makes state initialization clearer and makes further changes easier. Also, although not practical in the real world, this commit now allows multi-XLEN object disassembling if the object file has mapping symbols with ISA string and the machine is XLEN-neutral (e.g. objdump with "-m riscv" option). It may help testing Binutils / GAS. opcodes/ChangeLog: * riscv-dis.c (initial_default_arch): Special default architecture string which is handled separately. (riscv_dis_arch_context_t): New type to manage RISC-V architecture context for the disassembler. Two instance of this type is defined in this file - "default" and "override". (dis_arch_context_default): New. Architecture context inferred from either an ELF attribute or initial_default_arch. (dis_arch_context_override): New. Architecture context inferred from mapping symbols with ISA string. (dis_arch_context_current): New. A pointer to either dis_arch_context_default or dis_arch_context_override. (riscv_rps_dis): Add summary. Use initial values from the initial value of dis_arch_context_current - dis_arch_context_default. (from_last_map_symbol): Make it file scope to decide whether we should revert the architecture to the default in riscv_get_map_state function. (set_riscv_current_dis_arch_context): New function to update riscv_rps_dis and dis_arch_context_current. (set_riscv_dis_arch_context): New function to update the architecture for the given context. (update_riscv_dis_xlen): Consider dis_arch_context_current->xlen when guessing correct XLEN. (is_arch_changed): New. Set to true if the architecture is changed. (init_riscv_dis_state_for_arch): New function to track whether the architecture string is changed. (init_riscv_dis_state_for_arch_and_options): Keep track of the architecture string change and update XLEN if it has changed. (update_riscv_dis_arch): New function to set both the architecture and the context. Call initialization functions if needed. (riscv_get_map_state): Add update argument. Keep track of the mapping symbols with ISA string and update the architecture and the context if required. (riscv_search_mapping_symbol): Move from_last_map_symbol to file scope. Call riscv_get_map_state function with architecture and context updates enabled. (riscv_data_length): Call riscv_get_map_state function with architecture and context updates disabled. (riscv_get_disassembler): Add an error handling on Tag_RISCV_arch. Call update_riscv_dis_arch function to update the architecture and the context. Co-developed-by: Nelson Chu --- opcodes/riscv-dis.c | 174 ++++++++++++++++++++++++++++++++++++++------ 1 file changed, 152 insertions(+), 22 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 76387efbe4b..a57f4208f68 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -32,6 +32,9 @@ #include #include +/* Default architecture string (if not available). */ +static const char *const initial_default_arch = "rv64gc"; + /* Current XLEN for the disassembler. */ static unsigned xlen = 0; @@ -48,14 +51,36 @@ static enum riscv_spec_class default_isa_spec = ISA_SPEC_CLASS_DRAFT - 1; (as specified by the ELF attributes or the `priv-spec' option). */ static enum riscv_spec_class default_priv_spec = PRIV_SPEC_CLASS_NONE; -static riscv_subset_list_t riscv_subsets; +/* RISC-V disassembler architecture context type. */ +typedef struct +{ + const char *arch_str; + const char *default_arch; + riscv_subset_list_t subsets; + unsigned xlen; + bool no_xlen_if_default; +} riscv_dis_arch_context_t; + +/* Context: default (either initial_default_arch or ELF attribute). */ +static riscv_dis_arch_context_t dis_arch_context_default + = { NULL, initial_default_arch, { }, 0, true }; + +/* Context: override (mapping symbols with ISA string). */ +static riscv_dis_arch_context_t dis_arch_context_override + = { NULL, NULL, {}, 0, false }; + +/* Pointer to the current disassembler architecture context. */ +static riscv_dis_arch_context_t *dis_arch_context_current + = &dis_arch_context_default; + +/* RISC-V ISA string parser structure (current). */ static riscv_parse_subset_t riscv_rps_dis = { - &riscv_subsets, /* subset_list. */ - opcodes_error_handler,/* error_handler. */ - &xlen, /* xlen. */ - &default_isa_spec, /* isa_spec. */ - false, /* check_unknown_prefixed_ext. */ + &(dis_arch_context_default.subsets), /* subset_list. */ + opcodes_error_handler, /* error_handler. */ + &(dis_arch_context_default.xlen), /* xlen. */ + &default_isa_spec, /* isa_spec. */ + false, /* check_unknown_prefixed_ext. */ }; /* Private data structure for the RISC-V disassembler. */ @@ -71,6 +96,7 @@ struct riscv_private_data /* Used for mapping symbols. */ static int last_map_symbol = -1; static bfd_vma last_stop_offset = 0; +static bool from_last_map_symbol = false; /* Register names as used by the disassembler. */ static const char * const *riscv_gpr_names; @@ -83,6 +109,59 @@ static bool no_aliases = false; static bool is_numeric = false; +/* Set current disassembler context (dis_arch_context_current). + Return true if successfully updated. */ + +static bool +set_riscv_current_dis_arch_context (riscv_dis_arch_context_t* context) +{ + if (context == dis_arch_context_current) + return false; + dis_arch_context_current = context; + riscv_rps_dis.subset_list = &(context->subsets); + riscv_rps_dis.xlen = &(context->xlen); + return true; +} + +/* Update riscv_dis_arch_context_t by an ISA string. + Return true if the architecture is updated by arch. */ + +static bool +set_riscv_dis_arch_context (riscv_dis_arch_context_t *context, + const char *arch) +{ + /* Check whether the architecture is changed and + return false if the architecture will not be changed. */ + if (context->arch_str) + { + if (context->default_arch && arch == context->default_arch) + return false; + if (strcmp (context->arch_str, arch) == 0) + return false; + } + /* Update architecture string. */ + if (context->arch_str != context->default_arch) + free ((void *) context->arch_str); + context->arch_str = (arch != context->default_arch) + ? xstrdup (arch) + : context->default_arch; + /* Update other contents (subset list and XLEN). */ + riscv_subset_list_t *prev_subsets = riscv_rps_dis.subset_list; + unsigned *prev_xlen = riscv_rps_dis.xlen; + riscv_rps_dis.subset_list = &(context->subsets); + riscv_rps_dis.xlen = &(context->xlen); + context->xlen = 0; + riscv_release_subset_list (&context->subsets); + riscv_parse_subset (&riscv_rps_dis, context->arch_str); + riscv_rps_dis.subset_list = prev_subsets; + riscv_rps_dis.xlen = prev_xlen; + /* Special handling on the default architecture. */ + if (context->no_xlen_if_default && arch == context->default_arch) + context->xlen = 0; + return true; +} + + /* Guess and update current XLEN. */ static void @@ -95,9 +174,13 @@ update_riscv_dis_xlen (struct disassemble_info *info) This is only effective if XLEN-specific BFD machine architecture is chosen. If XLEN-neutral (like riscv), BFD machine architecture is ignored on XLEN selection. - 2. ELF class in dummy ELF header. */ + 2. Non-default RISC-V architecture string set by either an ELF + attribute or a mapping symbol with ISA string. + 3. ELF class in dummy ELF header. */ if (xlen_by_mach != 0) xlen = xlen_by_mach; + else if (dis_arch_context_current->xlen != 0) + xlen = dis_arch_context_current->xlen; else if (xlen_by_elf != 0) xlen = xlen_by_elf; else if (info != NULL && info->section != NULL) @@ -107,11 +190,24 @@ update_riscv_dis_xlen (struct disassemble_info *info) } } +/* Initialization (for arch). */ + +static bool is_arch_changed = false; + +static void +init_riscv_dis_state_for_arch (void) +{ + is_arch_changed = true; +} + /* Initialization (for arch and options). */ static void init_riscv_dis_state_for_arch_and_options (void) { + /* If the architecture string is changed, update XLEN. */ + if (is_arch_changed) + update_riscv_dis_xlen (NULL); /* Set GPR register names to disassemble. */ riscv_gpr_names = is_numeric ? riscv_gpr_names_numeric : riscv_gpr_names_abi; /* Set FPR register names to disassemble. */ @@ -119,6 +215,25 @@ init_riscv_dis_state_for_arch_and_options (void) = !riscv_subset_supports (&riscv_rps_dis, "zfinx") ? (is_numeric ? riscv_fpr_names_numeric : riscv_fpr_names_abi) : riscv_gpr_names; + /* Save previous options and mark them "unchanged". */ + is_arch_changed = false; +} + +/* Update architecture for disassembler with its context. + Call initialization functions if either: + - the architecture for current context is changed or + - context is updated to a new one. */ + +static void +update_riscv_dis_arch (riscv_dis_arch_context_t *context, const char *arch) +{ + if ((set_riscv_dis_arch_context (context, arch) + && dis_arch_context_current == context) + || set_riscv_current_dis_arch_context (context)) + { + init_riscv_dis_state_for_arch (); + init_riscv_dis_state_for_arch_and_options (); + } } @@ -872,7 +987,8 @@ riscv_get_map_state_by_name (const char *name, const char** arch) static bool riscv_get_map_state (int n, enum riscv_seg_mstate *state, - struct disassemble_info *info) + struct disassemble_info *info, + bool update) { const char *name, *arch = NULL; @@ -886,12 +1002,25 @@ riscv_get_map_state (int n, if (newstate == MAP_NONE) return false; *state = newstate; - if (arch) - { - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, arch); - init_riscv_dis_state_for_arch_and_options (); - } + if (newstate == MAP_INSN && update) + { + if (arch) + { + /* Override the architecture. */ + update_riscv_dis_arch (&dis_arch_context_override, arch); + } + else if (!from_last_map_symbol + && set_riscv_current_dis_arch_context (&dis_arch_context_default)) + { + /* Revert to the default architecture and call init functions if: + - there's no ISA string in the mapping symbol, + - mapping symbol is not reused and + - current disassembler context is changed to the default one. + This is a shortcut path to avoid full update_riscv_dis_arch. */ + init_riscv_dis_state_for_arch (); + init_riscv_dis_state_for_arch_and_options (); + } + } return true; } @@ -903,7 +1032,6 @@ riscv_search_mapping_symbol (bfd_vma memaddr, struct disassemble_info *info) { enum riscv_seg_mstate mstate; - bool from_last_map_symbol; bool found = false; int symbol = -1; int n; @@ -943,7 +1071,7 @@ riscv_search_mapping_symbol (bfd_vma memaddr, /* We have searched all possible symbols in the range. */ if (addr > memaddr) break; - if (riscv_get_map_state (n, &mstate, info)) + if (riscv_get_map_state (n, &mstate, info, true)) { symbol = n; found = true; @@ -970,7 +1098,7 @@ riscv_search_mapping_symbol (bfd_vma memaddr, if (addr < (info->section ? info->section->vma : 0)) break; /* Stop searching once we find the closed mapping symbol. */ - if (riscv_get_map_state (n, &mstate, info)) + if (riscv_get_map_state (n, &mstate, info, true)) { symbol = n; found = true; @@ -1006,7 +1134,7 @@ riscv_data_length (bfd_vma memaddr, { bfd_vma addr = bfd_asymbol_value (info->symtab[n]); if (addr > memaddr - && riscv_get_map_state (n, &m, info)) + && riscv_get_map_state (n, &m, info, false)) { if (addr - memaddr < length) length = addr - memaddr; @@ -1130,7 +1258,7 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) disassembler_ftype riscv_get_disassembler (bfd *abfd) { - const char *default_arch = "rv64gc"; + const char *default_arch = initial_default_arch; if (abfd && bfd_get_flavour (abfd) == bfd_target_elf_flavour) { @@ -1146,12 +1274,14 @@ riscv_get_disassembler (bfd *abfd) attr[Tag_c].i, &default_priv_spec); default_arch = attr[Tag_RISCV_arch].s; + /* For ELF files with (somehow) no architecture string + in the attributes, use the default value. */ + if (!default_arch) + default_arch = initial_default_arch; } } - riscv_release_subset_list (&riscv_subsets); - riscv_parse_subset (&riscv_rps_dis, default_arch); - init_riscv_dis_state_for_arch_and_options (); + update_riscv_dis_arch (&dis_arch_context_default, default_arch); return print_insn_riscv; } From patchwork Tue Nov 15 04:52:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tsukasa OI X-Patchwork-Id: 20195 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:a40e:b0:83:7221:86ba with SMTP id ck14csp3426472dyb; Mon, 14 Nov 2022 21:05:35 -0800 (PST) X-Google-Smtp-Source: AA0mqf5RW89DI+cXqaiY8yMgMGEJajeza5exDkfba1vYqOc4YD7zc7jqIcjyFdATs4fzikxQuD1Y X-Received: by 2002:a17:906:4dc2:b0:7ae:50c6:fd0a with SMTP id f2-20020a1709064dc200b007ae50c6fd0amr12311133ejw.184.1668488735163; Mon, 14 Nov 2022 21:05:35 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668488735; cv=none; d=google.com; s=arc-20160816; b=sNSuUlhooPvLk0i44NS3wq/Gmh/F3mthcaPIgynHqVopY/KlnqYlE50mQscmd/g5mo f+nWhrLzLdntExqBEYOAjr3dDD0rsGIY/fgz92jAExhp7Q4uMpAfYxjcij2LF2Nnvr+1 paDQI40JaVA7UrFC0IY2CPT9c9WY3a64vauViF9uaPl7TqGHo+hg0aX9u0e6ga3231mt fbKmz8V/X29JJlMYNnZWYAToyHvmctXH0hWRGRAriJEiG7gZ3b09J3RLrK5P6etTcny8 zWrBVz/yeancrFROWMMSy5Lv7CJGm74qV9eKK0C0uBawvTxTC92RYOJIUe+7A7Zje8q4 yxeQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:reply-to:from:list-subscribe:list-help:list-post :list-archive:list-unsubscribe:list-id:precedence :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:dmarc-filter:delivered-to :dkim-signature:dkim-filter; bh=HUteqaulL0ixHyMs7sxLR6+4V+OSDyOvDkVzmxPXq6o=; b=O9duD6TSU5N3US7hs2EA1QZYqMa5SJkHsAZ8sZbUKu1xIEr1aqrlBBlubWYa/+dhmE akVte8+bTGguitTHVc5kjYcW3LpyNaASyxxdBibeE3F1OBfxBKdz+tX1h9syYullehq0 s0gFyIHnnlRFT+iAg7KPIp1VuqYGdlGo19hz0TNk+8E8aE57GGgjUbsFqr7nbqXd1yN3 56k7bfYC88bnl8fudly/b8EbIOv2I28LljcOVRwsQIagXjCGKc4Ma94DrNJRUHAP8mlV MwwQa1AMup2Eq3oVDkwXhb++mtrFLGIgwur5BqSNp5+RSOo52zlU+T1mrPurkSYYAWKL KwhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=D2dRKmBD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from sourceware.org (ip-8-43-85-97.sourceware.org. [8.43.85.97]) by mx.google.com with ESMTPS id c12-20020a50d64c000000b00458cbb6b6easi9776981edj.167.2022.11.14.21.05.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 21:05:35 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=D2dRKmBD; spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5054038AA246 for ; Tue, 15 Nov 2022 05:03:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5054038AA246 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sourceware.org; s=default; t=1668488592; bh=HUteqaulL0ixHyMs7sxLR6+4V+OSDyOvDkVzmxPXq6o=; h=To:Cc:Subject:Date:In-Reply-To:References:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From:Reply-To:From; b=D2dRKmBDpf1LjjUTzF+/R46iQOeoeQsOMA/HzhcHzvl/qLjQh69vcudIFVXannZ9k 25RlwOdLuKZNAVd+Hyuwr/g7FaxKThW99XMs02KSvyKx7Kfl10W1N+hu6sunU3jtxM jeaa0ytByhZOxY/TUD3Brszs2lpFNl/2aVQUudR0= X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail-sender-0.a4lg.com (mail-sender-0.a4lg.com [IPv6:2401:2500:203:30b:4000:6bfe:4757:0]) by sourceware.org (Postfix) with ESMTPS id 8CE1F3889E0B for ; Tue, 15 Nov 2022 04:59:30 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 8CE1F3889E0B Received: from [127.0.0.1] (localhost [127.0.0.1]) by mail-sender-0.a4lg.com (Postfix) with ESMTPSA id DB4B0300089; Tue, 15 Nov 2022 04:59:28 +0000 (UTC) To: Tsukasa OI , Nelson Chu , Kito Cheng , Palmer Dabbelt Cc: binutils@sourceware.org Subject: [PATCH 11/11] RISC-V: Move disassembler private data initialization Date: Tue, 15 Nov 2022 04:52:54 +0000 Message-Id: In-Reply-To: References: Mime-Version: 1.0 X-Spam-Status: No, score=-12.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Tsukasa OI via Binutils From: Tsukasa OI Reply-To: Tsukasa OI Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org Sender: "Binutils" X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749537243984054289?= X-GMAIL-MSGID: =?utf-8?q?1749537243984054289?= Because disassemble_info.private_data could be used not only by riscv_disassemble_insn, this commit splits the initialization of the private data to a separate function. This commit now allows storing mapping symbol and/or section-related information to riscv_private_data. In performance perspective, it also has a penalty. However, it can be easily paid back by other optimizations and it makes implementing some optimizations easier. opcodes/ChangeLog: * riscv-dis.c (init_riscv_dis_private_data): New. (riscv_disassemble_insn): Move private data initialization to init_riscv_dis_private_data. (print_insn_riscv): Start initializing the private data instead of instruction only riscv_disassemble_insn function. --- opcodes/riscv-dis.c | 51 +++++++++++++++++++++++++-------------------- 1 file changed, 28 insertions(+), 23 deletions(-) diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index a57f4208f68..80eb8cbbea4 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -219,6 +219,29 @@ init_riscv_dis_state_for_arch_and_options (void) is_arch_changed = false; } +/* Initialize private data of the disassemble_info. */ + +static void +init_riscv_dis_private_data (struct disassemble_info *info) +{ + struct riscv_private_data *pd; + + pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); + pd->gp = 0; + pd->print_addr = 0; + for (int i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) + pd->hi_addr[i] = -1; + pd->to_print_addr = false; + pd->has_gp = false; + + for (int i = 0; i < info->symtab_size; i++) + if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) + { + pd->gp = bfd_asymbol_value (info->symtab[i]); + pd->has_gp = true; + } +} + /* Update architecture for disassembler with its context. Call initialization functions if either: - the architecture for current context is changed or @@ -806,7 +829,7 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) const struct riscv_opcode *op, *matched_op; static bool init = false; static const struct riscv_opcode *riscv_hash[OP_MASK_OP + 1]; - struct riscv_private_data *pd; + struct riscv_private_data *pd = info->private_data; int insnlen; #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : OP_MASK_OP)) @@ -821,28 +844,6 @@ riscv_disassemble_insn (bfd_vma memaddr, insn_t word, disassemble_info *info) init = true; } - if (info->private_data == NULL) - { - int i; - - pd = info->private_data = xcalloc (1, sizeof (struct riscv_private_data)); - pd->gp = 0; - pd->print_addr = 0; - for (i = 0; i < (int)ARRAY_SIZE (pd->hi_addr); i++) - pd->hi_addr[i] = -1; - pd->to_print_addr = false; - pd->has_gp = false; - - for (i = 0; i < info->symtab_size; i++) - if (strcmp (bfd_asymbol_name (info->symtab[i]), RISCV_GP_SYMBOL) == 0) - { - pd->gp = bfd_asymbol_value (info->symtab[i]); - pd->has_gp = true; - } - } - else - pd = info->private_data; - insnlen = riscv_insn_length (word); /* RISC-V instructions are always little-endian. */ @@ -1215,6 +1216,10 @@ print_insn_riscv (bfd_vma memaddr, struct disassemble_info *info) enum riscv_seg_mstate mstate; int (*riscv_disassembler) (bfd_vma, insn_t, struct disassemble_info *); + /* Initialize the private data. */ + if (info->private_data == NULL) + init_riscv_dis_private_data (info); + /* Guess and update XLEN if we haven't determined it yet. */ if (xlen == 0) update_riscv_dis_xlen (info);