From patchwork Mon Jan 29 13:55:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 193488 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp581383dyb; Mon, 29 Jan 2024 06:00:15 -0800 (PST) X-Google-Smtp-Source: AGHT+IHp2l+V6Nv6oTnxRg5YBjiqyml8EFog1UHOljq8zVueXqQapgphrS7Th7UY175IihCLR1KO X-Received: by 2002:a05:6830:10d3:b0:6e1:1570:d4a2 with SMTP id z19-20020a05683010d300b006e11570d4a2mr6735229oto.33.1706536814977; Mon, 29 Jan 2024 06:00:14 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706536814; cv=pass; d=google.com; s=arc-20160816; b=AzSE1CKYhSALpfSxQszsAwDzx/y4wlrffTDn2i9U87URGn482pALfKFffsDmyqeMXX f7yfYtYcP79/+U4ce/7TLqm2D4mMSIOhkmXQk73XLE+pM6APOQXXhmzBUFV1TV3Z1tEN zPy4IiCK8zU0DNzNK5OsOvCuKPncVPpAwHvGkwxAMGYM60S7RC5tNVkZwJ0+w5hBIJjL XhizgRLN9tLTUIO/Wg66QYquP11Vv2PfLhaAZ4IVaS7V7bc8RDv+F8wkAd2UeKhkHE50 laqSZpX9RvD34RXSC1xTz/I07eRSVktwl3EiJpO9FDB08CwTLJOl9KugnuiV36pwe+kE BF/A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=GfIWoQHy7z0V0yUTX2XoUCJ/M52iXXotNEoKtHwDMZA=; fh=9jERyHaBVkSYjvKDLj7G39aR/G88vFciZPp35CZ8FfY=; b=lxhnNvhduhckdgBt3k57xGmLcnBMEnoZ1PbnIZ73UPGXOkEoId9Ljk3wfOAIELLHsG t4bWvgQddg7U/NapmqKR+2Q+pAaQMdXDDqHtj1qEJDqVLccyyFgxaI7eio+4nx/1+/yw /BECbIi4VESk+ZkvgMmqP/d5Hhytj+C2j5vVxIgSCC55x3dM6Lc4s0oJF7mkADXGLgPy CNlY8ViLyeBF9ll5MLDSM0pX1FMCm2IuSl6clgNXjIB1XjM0DcHhPpAYPSCk50maVqg6 HNqvy9h3GrI7wo/wdMNwk9yyEMQBV4JfVA0EenMsY0iTJoXOVIdidpJOuUibsvQOIvX6 9CNg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=OVVbshUu; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42843-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42843-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [2604:1380:45e3:2400::1]) by mx.google.com with ESMTPS id d25-20020a637359000000b005c65c11ad09si5613070pgn.768.2024.01.29.06.00.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 06:00:14 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-42843-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) client-ip=2604:1380:45e3:2400::1; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=OVVbshUu; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42843-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42843-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id C53C22839B2 for ; Mon, 29 Jan 2024 13:57:22 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F1BD4664D5; Mon, 29 Jan 2024 13:56:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="OVVbshUu" Received: from mail-wr1-f51.google.com (mail-wr1-f51.google.com [209.85.221.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A371657B9; Mon, 29 Jan 2024 13:56:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536588; cv=none; b=Nrx0a+FMr6NKFoy/BapEQQ8zxtN0np5ETaRg2cjYcxR2toYrp32B5x1t1PD86Iyr7GxZOP+Mez4AU8C5awaaVD0Tbs+QIZ7FVeMYgxEVIWvCz7ouNkv9Vbw0UnZ5IqKVSIJFzq7lFKjvh+S+XiiZMlqtDcpInGNKhR4iSK++abk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536588; c=relaxed/simple; bh=mTtSqAY9WSHR3XRmwFrnCt/54qdX28p1oaTlKRQzAag=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=qScrprobfrfW7DgRLHUZcpuekPLuMJsfJ0C4IT+YMnlzW/f3tvXW12cvwLuoCWwgCvK/roEp7rCGBx/A/oCAWM7U5dhQIZ/8vOZ3oQweNXZcY5dWiZT4NWJ0Z0MPtrmxJGgouVqYQXjZZi/BBYRf0MW4H2OzAu2foai2Gt3TzTI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=OVVbshUu; arc=none smtp.client-ip=209.85.221.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f51.google.com with SMTP id ffacd0b85a97d-3392b045e0aso2281215f8f.2; Mon, 29 Jan 2024 05:56:25 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706536584; x=1707141384; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GfIWoQHy7z0V0yUTX2XoUCJ/M52iXXotNEoKtHwDMZA=; b=OVVbshUuD3zfDF7w1oNuJCbLqPLhUQjgDM6Tr8ahzjcBnircVLRhnQTzXvnd4zLXpW kNiryUNjMykz3dsnLT8Yk/CmxFvSN9Fb8jRvKrPiHlkd6xrxJN+Q66kgHvTyf0+MVRGc Kuh8zVRGT0v0yghOZ2rUOg2TSF1LeKft43L7UqQwlQpDp0fdnW7IqJ08NrsLq0oyuRbj /psNxUSfOia9/4zndKMJusWnUgYT3d4gcRvLGQaUvigbvr2eiciSJxM4wdFUmJFjTdWO OENjkdpib1dEaf9v0XGtiJJLm20e0wxoAAo9yUYyrcy/mfvVE80DR+TZhs50ABu7T/zl 4FwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706536584; x=1707141384; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GfIWoQHy7z0V0yUTX2XoUCJ/M52iXXotNEoKtHwDMZA=; b=Mk7mrPIesuhAEx+ttoGLGj4zBrX6yJt539tBsJtaLPUmcRXljtMzAFyc8wbxLKplKj uEdzGesdz1kbiN61zMMP53yYiMudGmEcVXm70Dg/16tvLJplGMYynEyt7nbXxxvyyaUj G/vlVCs9usqx7vLYDW4Bizp7HnfKWhrUYT25rPTFKrGESBsAZZBamRCqJuz8eeg2w4S7 qQv45KAr5AN8pB9nrED7ScGt1TREqdHI2g2dpsKjbyhytgCq3fR7LT4C85b8LCWtRKnj vqFL/rv0KIHplbguI4S62O6agTRjW0uPmANO8eyI3c4gjLCdr6qfg0EfriMwaHPJfVqY ngvg== X-Gm-Message-State: AOJu0YwmtK71ExUl/oyglzyDoFQCd0pcfH8DgpY1rcyR3g6eC9v7Wh8Y HQC/zjRcroc3LQNp2eC/mZGlHH5RQtMn+40MGGbOK5hzMOtsU+IY X-Received: by 2002:a5d:6692:0:b0:33a:e773:5f3c with SMTP id l18-20020a5d6692000000b0033ae7735f3cmr2922585wru.3.1706536583999; Mon, 29 Jan 2024 05:56:23 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:5616:a18c:ea50:2995]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b0033aed46956csm3058057wrb.80.2024.01.29.05.56.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:56:23 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v6 1/4] pinctrl: renesas: rzg2l: Improve code for readability Date: Mon, 29 Jan 2024 13:55:53 +0000 Message-Id: <20240129135556.63466-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789433546989390828 X-GMAIL-MSGID: 1789433546989390828 From: Lad Prabhakar As the RZ/G2L pinctrl driver is extensively utilized by numerous SoCs and has experienced substantial growth, enhance code readability by incorporating FIELD_PREP_CONST/FIELD_GET macros wherever necessary. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 41 +++++++++++++++---------- 1 file changed, 24 insertions(+), 17 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 80fb5011c7bb..c7dc32176bfe 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -5,6 +5,7 @@ * Copyright (C) 2021 Renesas Electronics Corporation. */ +#include #include #include #include @@ -38,8 +39,6 @@ */ #define MUX_PIN_ID_MASK GENMASK(15, 0) #define MUX_FUNC_MASK GENMASK(31, 16) -#define MUX_FUNC_OFFS 16 -#define MUX_FUNC(pinconf) (((pinconf) & MUX_FUNC_MASK) >> MUX_FUNC_OFFS) /* PIN capabilities */ #define PIN_CFG_IOLH_A BIT(0) @@ -81,8 +80,12 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define RZG2L_GPIO_PORT_PACK(n, a, f) (((n) << 28) | ((a) << 20) | (f)) -#define RZG2L_GPIO_PORT_GET_PINCNT(x) (((x) & GENMASK(30, 28)) >> 28) +#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) +#define PIN_CFG_MASK GENMASK(19, 0) +#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) /* * BIT(31) indicates dedicated pin, p is the register index while @@ -90,14 +93,18 @@ * (b * 8) and f is the pin configuration capabilities supported. */ #define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) +#define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) + #define RZG2L_SINGLE_PIN_PACK(p, b, f) (RZG2L_SINGLE_PIN | \ - ((p) << 24) | ((b) << 20) | (f)) -#define RZG2L_SINGLE_PIN_GET_BIT(x) (((x) & GENMASK(22, 20)) >> 20) + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_INDEX_MASK, (p)) | \ + FIELD_PREP_CONST(RZG2L_SINGLE_PIN_BITS_MASK, (b)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) -#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & GENMASK(19, 0)) +#define RZG2L_PIN_CFG_TO_CAPS(cfg) ((cfg) & PIN_CFG_MASK) #define RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg) ((cfg) & RZG2L_SINGLE_PIN ? \ - (((cfg) & GENMASK(30, 24)) >> 24) : \ - (((cfg) & GENMASK(26, 20)) >> 20)) + FIELD_GET(RZG2L_SINGLE_PIN_INDEX_MASK, (cfg)) : \ + FIELD_GET(PIN_CFG_PIN_REG_MASK, (cfg))) #define P(off) (0x0000 + (off)) #define PM(off) (0x0100 + (off) * 2) @@ -432,8 +439,8 @@ static int rzg2l_dt_subnode_to_map(struct pinctrl_dev *pctldev, ret = of_property_read_u32_index(np, "pinmux", i, &value); if (ret) goto done; - pins[i] = value & MUX_PIN_ID_MASK; - psel_val[i] = MUX_FUNC(value); + pins[i] = FIELD_GET(MUX_PIN_ID_MASK, value); + psel_val[i] = FIELD_GET(MUX_FUNC_MASK, value); } if (parent) { @@ -560,7 +567,7 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, u32 cfg, u32 port, u8 bit) { - u8 pincount = RZG2L_GPIO_PORT_GET_PINCNT(cfg); + u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); u32 data; @@ -868,7 +875,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit = RZG2L_PIN_ID_TO_PIN(_pin); @@ -972,7 +979,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); cfg = RZG2L_PIN_CFG_TO_CAPS(*pin_data); if (*pin_data & RZG2L_SINGLE_PIN) { - bit = RZG2L_SINGLE_PIN_GET_BIT(*pin_data); + bit = FIELD_GET(RZG2L_SINGLE_PIN_BITS_MASK, *pin_data); } else { bit = RZG2L_PIN_ID_TO_PIN(_pin); @@ -1608,12 +1615,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_ bit = virq % 8; if (port >= data->n_ports || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[port])) + bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port])) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += RZG2L_GPIO_PORT_GET_PINCNT(data->port_pin_configs[i]); + gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); return gpioint; } @@ -1788,7 +1795,7 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, bit = offset % 8; if (port >= pctrl->data->n_ports || - bit >= RZG2L_GPIO_PORT_GET_PINCNT(pctrl->data->port_pin_configs[port])) + bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port])) clear_bit(offset, valid_mask); } } From patchwork Mon Jan 29 13:55:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 193486 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp580102dyb; Mon, 29 Jan 2024 05:57:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IE0WrpGAdFV2O9Ily76DkyoQHswBsKhFcqBbz0B2XElLAhkpp8YgCkzP/ns9qRZrOBZzzZu X-Received: by 2002:a05:6214:1944:b0:68c:4687:36de with SMTP id q4-20020a056214194400b0068c468736demr5009805qvk.100.1706536671931; Mon, 29 Jan 2024 05:57:51 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706536671; cv=pass; d=google.com; s=arc-20160816; b=cFFw05ffQIl6m4nx2HFiXLSE5Bm91qvcBElKpN011Y7rIlI2r+tNKT6bEVJB+2ve63 Sqw3HYNEYmR19hSA1Ab7nEm83rZIXqt3rXZS4OhDQElmh24MeD0juyIiSD1/QT4h3zCr UpOewFWJ4bDn8HsLKUr1oyXDgCKNy5jIAMYIjpLlgfCbbKhwCSS7pWPfWf1/6SJkO/+R IPMgv9Uh1lktShnPQxKX16ps48DTrkaEBxFxLebL2o9XFOvhlM+5u9S5xAV4R3jzOdNO Q1egpRlpvf/KF8H5lHB5PU0lKtA6yUl/zRAOfxBGHIsBV50kFTTtuiLAGuSMWDSNlw5n RwVw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=TGZ7g8+GW2jddKqidzCnSKvqoGpmSbkCQHK3oOQ56iw=; fh=9jERyHaBVkSYjvKDLj7G39aR/G88vFciZPp35CZ8FfY=; b=C9aBCwpoJm7jty02eG+4o1EIa6nKFNFf5IHB2YbG3UDChXmdkbpz1QlpNXFEPfqKkD MzQqtahQiXF8rKgs2kIiCoY6WLpzKv3kRSGkAIYYnlhLi4IyMbXpPn12Ydb5BEQGYaGn 0HUcGYFyO3kwL9WBOs7yseJ3KN+Bo6KOs5r6Nu42klm+zOFnrYB5gezK2W4mR1RmkFbN PwDQxCsPkAwOG/qZts3Teew8lq8bIPk8JHR2nUpOYcYg0mtWhx3CNIZiCDkpLHukI0/X wPIUgkkWdidt5jkWT4tdSGUQvxjLKWNDvzm9w0gmvRHV//AaLhB0r3SQ89sKPxwCu3h1 3wIQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="SzmIW2u/"; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42844-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42844-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [147.75.199.223]) by mx.google.com with ESMTPS id gv2-20020a056214262200b0068064f2dc53si7779071qvb.434.2024.01.29.05.57.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:57:51 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-42844-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) client-ip=147.75.199.223; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="SzmIW2u/"; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42844-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42844-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id A08CB1C20C2D for ; Mon, 29 Jan 2024 13:57:51 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 695EA66B53; Mon, 29 Jan 2024 13:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="SzmIW2u/" Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 84A86657CB; Mon, 29 Jan 2024 13:56:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536589; cv=none; b=tqkDNmWB3s4C0nzJqcsx6HoxZPB1Ih2B53+iEANAk5wiKdRq9usOhRNmpnxEfVxWHwHHsHmW9HqflcJRDNMn6tcHc6CYhvVFaB/IQOR7Chbpf8xx3I+FZvW3ZTmASg678WfYIzeuXGPbrS9iGkns7800S1viG5SYmSH7HTiUz30= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536589; c=relaxed/simple; bh=LE0UJhi2UDP0MTQE6T2yWuU0twLWJsvTjl7WIk9UoXw=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=nKTsh5trRSW/hr64zWVLLmbfdQCXcVNpU7leqZjHrjrxh4zKJjJZcUpKii7wr/fVuet23ZVoKaFnDwC7D0EATB0VoSS/fJkeqjutJcn0fzclCpERvCLeKF+l9aG4gznWbx/Z1rtJCqMazkJ9zAPOQArbRMo3+zsCdmQMfDIkRdE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=SzmIW2u/; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-40ed356a6ecso24409265e9.2; Mon, 29 Jan 2024 05:56:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706536586; x=1707141386; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TGZ7g8+GW2jddKqidzCnSKvqoGpmSbkCQHK3oOQ56iw=; b=SzmIW2u/d3iLHkbpFi97DlAkzNnOV/87Yagi7oc0/LzmRHF87OQCY8byORIMPBefEx fWkt+c+mRBpaTDFWuPWlw73+1zy1C6wcQCpr8Ziqd4fkU0AMQJkHZFe3w5lcmVpOYliD 6zhOFCNJUnMPg0+bdMJcJrE4B3cFB1AILT78Je/jn2WQWqRnUQZYB8rDow5wPeB2Zr9l LBhCsfUIqfVQxatJe1bRw82hmwAxXm14ITd7uW5NTQm07tGl3gXSC4bVyfth3I0QH81i fzCq6yyfhLPDn5VhaPbK3dgWjUQ7T0n+aBNnZ7mdFilUuXR9EKXt6olj2LT5s82P2+5x Q0LQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706536586; x=1707141386; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TGZ7g8+GW2jddKqidzCnSKvqoGpmSbkCQHK3oOQ56iw=; b=n/UJ0CT+beB7N/CgtpxBKIN6LW5uOiG0zWGUwTkgJsZztqJY1uBwYRNQk899d0A3mr yV50HTJp9fI8d3CR3JW9CBWr7IX/hwFoAO/ZlfspRa6GhGftZy5jouANA5fNpFBS80S9 d/qA+TvYBdqrsnHTmJIClkQ4eiAeVVv8o+I+RfgqoM20g/z4atnfaWGNZHrLlhbH9Sg1 DWTRaGBH4t+OmqNvg44r8NVDHMJ2e3O+zdiUU+0ZeVHsTfdmyzuXJVK6+AOnomN0PKE9 ek6QKwq82CFTQ+kwkSnRAHLBCcYbz+Kaeea6So6I9QtjonjJ6ufwhBzgOreHHNJajxmG Ihvw== X-Gm-Message-State: AOJu0YyNL8RxVsbDSvizqJBjN0W7eqZU/W9/5Vmx6/FmWVK5p6XNo/YM SPIFtgMqukPch4dynm+ff1m8Lo61ESVgUYn0OZahgFUpV/I/S6Ds X-Received: by 2002:adf:ff92:0:b0:33a:e791:d8a6 with SMTP id j18-20020adfff92000000b0033ae791d8a6mr3190741wrr.47.1706536585346; Mon, 29 Jan 2024 05:56:25 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:5616:a18c:ea50:2995]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b0033aed46956csm3058057wrb.80.2024.01.29.05.56.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:56:24 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v6 2/4] pinctrl: renesas: rzg2l: Include pinmap in RZG2L_GPIO_PORT_PACK() macro Date: Mon, 29 Jan 2024 13:55:54 +0000 Message-Id: <20240129135556.63466-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789433397500642614 X-GMAIL-MSGID: 1789433397500642614 From: Lad Prabhakar Currently we assume all the port pins are sequential ie always PX_0 to PX_n (n=1..7) exist, but on RZ/Five SoC we have additional pins P19_1 to P28_5 which have holes in them, for example only one pin on port19 is available and that is P19_1 and not P19_0. So to handle such cases include pinmap for each port which would indicate the pin availability on each port. As the pincount can be calculated based on pinmap drop this from RZG2L_GPIO_PORT_PACK() macro. Previously we had a max of 7 pins on each port but on RZ/Five Port-20 has 8 pins, so move the single pin configuration to BIT(63). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 56 +++++++++++++------------ 1 file changed, 29 insertions(+), 27 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index c7dc32176bfe..33ea5f8dc998 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -80,19 +80,20 @@ * n indicates number of pins in the port, a is the register index * and f is pin configuration capabilities supported. */ -#define PIN_CFG_PIN_CNT_MASK GENMASK(30, 28) +#define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) -#define RZG2L_GPIO_PORT_PACK(n, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_CNT_MASK, (n)) | \ + +#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ FIELD_PREP_CONST(PIN_CFG_MASK, (f))) /* - * BIT(31) indicates dedicated pin, p is the register index while + * BIT(63) indicates dedicated pin, p is the register index while * referencing to SR/IEN/IOLH/FILxx registers, b is the register bits * (b * 8) and f is the pin configuration capabilities supported. */ -#define RZG2L_SINGLE_PIN BIT(31) +#define RZG2L_SINGLE_PIN BIT_ULL(63) #define RZG2L_SINGLE_PIN_INDEX_MASK GENMASK(30, 24) #define RZG2L_SINGLE_PIN_BITS_MASK GENMASK(22, 20) @@ -196,12 +197,12 @@ struct rzg2l_hwcfg { struct rzg2l_dedicated_configs { const char *name; - u32 config; + u64 config; }; struct rzg2l_pinctrl_data { const char * const *port_pins; - const u32 *port_pin_configs; + const u64 *port_pin_configs; unsigned int n_ports; const struct rzg2l_dedicated_configs *dedicated_pins; unsigned int n_port_pins; @@ -302,7 +303,7 @@ static int rzg2l_pinctrl_set_mux(struct pinctrl_dev *pctldev, pins = group->grp.pins; for (i = 0; i < group->grp.npins; i++) { - unsigned int *pin_data = pctrl->desc.pins[pins[i]].drv_data; + u64 *pin_data = pctrl->desc.pins[pins[i]].drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 pin = RZG2L_PIN_ID_TO_PIN(pins[i]); @@ -565,13 +566,13 @@ static int rzg2l_dt_node_to_map(struct pinctrl_dev *pctldev, } static int rzg2l_validate_gpio_pin(struct rzg2l_pinctrl *pctrl, - u32 cfg, u32 port, u8 bit) + u64 cfg, u32 port, u8 bit) { - u8 pincount = FIELD_GET(PIN_CFG_PIN_CNT_MASK, cfg); + u8 pinmap = FIELD_GET(PIN_CFG_PIN_MAP_MASK, cfg); u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(cfg); - u32 data; + u64 data; - if (bit >= pincount || port >= pctrl->data->n_port_pins) + if (!(pinmap & BIT(bit)) || port >= pctrl->data->n_port_pins) return -EINVAL; data = pctrl->data->port_pin_configs[port]; @@ -863,7 +864,7 @@ static int rzg2l_pinctrl_pinconf_get(struct pinctrl_dev *pctldev, enum pin_config_param param = pinconf_to_config_param(*config); const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; unsigned int arg = 0; u32 off, cfg; int ret; @@ -966,7 +967,7 @@ static int rzg2l_pinctrl_pinconf_set(struct pinctrl_dev *pctldev, const struct pinctrl_pin_desc *pin = &pctrl->desc.pins[_pin]; const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct rzg2l_pinctrl_pin_settings settings = pctrl->settings[_pin]; - unsigned int *pin_data = pin->drv_data; + u64 *pin_data = pin->drv_data; enum pin_config_param param; unsigned int i, arg, index; u32 cfg, off; @@ -1171,7 +1172,7 @@ static int rzg2l_gpio_request(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - u32 *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u32 port = RZG2L_PIN_ID_TO_PORT(offset); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1203,7 +1204,7 @@ static void rzg2l_gpio_set_direction(struct rzg2l_pinctrl *pctrl, u32 offset, bool output) { const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1224,7 +1225,7 @@ static int rzg2l_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); @@ -1255,7 +1256,7 @@ static void rzg2l_gpio_set(struct gpio_chip *chip, unsigned int offset, { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); unsigned long flags; @@ -1288,7 +1289,7 @@ static int rzg2l_gpio_get(struct gpio_chip *chip, unsigned int offset) { struct rzg2l_pinctrl *pctrl = gpiochip_get_data(chip); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[offset]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(offset); u16 reg16; @@ -1373,7 +1374,7 @@ static const char * const rzg2l_gpio_names[] = { "P48_0", "P48_1", "P48_2", "P48_3", "P48_4", "P48_5", "P48_6", "P48_7", }; -static const u32 r9a07g044_gpio_configs[] = { +static const u64 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x11, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(2, 0x12, RZG2L_MPXED_PIN_FUNCS), @@ -1425,7 +1426,7 @@ static const u32 r9a07g044_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(5, 0x40, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a07g043_gpio_configs[] = { +static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x10, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(5, 0x11, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), RZG2L_GPIO_PORT_PACK(4, 0x12, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IO_VMC_ETH0)), @@ -1447,7 +1448,7 @@ static const u32 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), }; -static const u32 r9a08g045_gpio_configs[] = { +static const u64 r9a08g045_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(4, 0x20, RZG3S_MPXED_PIN_FUNCS(A)), /* P0 */ RZG2L_GPIO_PORT_PACK(5, 0x30, RZG2L_MPXED_ETH_PIN_FUNCS(PIN_CFG_IOLH_C | PIN_CFG_IO_VMC_ETH0)) | @@ -1615,12 +1616,12 @@ static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_ bit = virq % 8; if (port >= data->n_ports || - bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[port])) + bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[port]))) return -EINVAL; gpioint = bit; for (i = 0; i < port; i++) - gpioint += FIELD_GET(PIN_CFG_PIN_CNT_MASK, data->port_pin_configs[i]); + gpioint += hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, data->port_pin_configs[i])); return gpioint; } @@ -1631,7 +1632,7 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1658,7 +1659,7 @@ static void rzg2l_gpio_irq_enable(struct irq_data *d) struct rzg2l_pinctrl *pctrl = container_of(gc, struct rzg2l_pinctrl, gpio_chip); unsigned int hwirq = irqd_to_hwirq(d); const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[hwirq]; - unsigned int *pin_data = pin_desc->drv_data; + u64 *pin_data = pin_desc->drv_data; u32 off = RZG2L_PIN_CFG_TO_PORT_OFFSET(*pin_data); u8 bit = RZG2L_PIN_ID_TO_PIN(hwirq); unsigned long flags; @@ -1795,7 +1796,8 @@ static void rzg2l_init_irq_valid_mask(struct gpio_chip *gc, bit = offset % 8; if (port >= pctrl->data->n_ports || - bit >= FIELD_GET(PIN_CFG_PIN_CNT_MASK, pctrl->data->port_pin_configs[port])) + bit >= hweight8(FIELD_GET(PIN_CFG_PIN_MAP_MASK, + pctrl->data->port_pin_configs[port]))) clear_bit(offset, valid_mask); } } @@ -1877,7 +1879,7 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) const struct rzg2l_hwcfg *hwcfg = pctrl->data->hwcfg; struct pinctrl_pin_desc *pins; unsigned int i, j; - u32 *pin_data; + u64 *pin_data; int ret; pctrl->desc.name = DRV_NAME; From patchwork Mon Jan 29 13:55:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 193489 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp581765dyb; Mon, 29 Jan 2024 06:00:41 -0800 (PST) X-Google-Smtp-Source: AGHT+IG95CrpJf3D1LFPFQAjZe8lEHLCZPLc3JT5FFz1woeW8gP1oh0gptg5fchQhB/jyosLCOQY X-Received: by 2002:a05:6870:9409:b0:210:b0f1:2700 with SMTP id d9-20020a056870940900b00210b0f12700mr3109314oal.54.1706536841240; Mon, 29 Jan 2024 06:00:41 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706536841; cv=pass; d=google.com; s=arc-20160816; b=K0xsqgqCH/drzG8qQWCsjqkLBEV5Pu143uCoxU7hzQArHQ1oaQQP7WS+4NxeQ9uwP5 vxxztHiwUohxi89ES3MTuXKEqI4UDqfrLzG6rHzAUoQTObjQpPkanY+8m9WFvpvF/OWa b9fllRLB8LDq64rKCqCzkTpZUphFE9QFeDBxHYZowiXGHNKiuR4PumqHwiYha0xbxEWM 6Nla78wNQz/73qpYUlD2tEkVOHVBjTIwI0V0o/b76MPN+7QA/Fre70odg3AWe4a3qWc3 pgATr4AeyHD9i5EpfYajHtiO5X53G4qGPWp+1RTsO/cT/2M6khS6zCNL6RU9zJrMlgLB FGpg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=lSuvJDsIeu/noXriCuOK1Pr7/Fad1f+UMujsbtdvC+8=; fh=9jERyHaBVkSYjvKDLj7G39aR/G88vFciZPp35CZ8FfY=; b=ur62aWnoFFf7oHOV3/Jx2rlIxBL7mp5lxMH2/Hzg4VR5ICSlQcqNBBoclubfGq0vVG Z3KuAunoo+2EmgfEnfdR5tAacZynAxqyIVJOjxkm21mSuzyPpl/nZfAm1j6P2yz/FOwN Yu/Ilo5L92ka4rcMskJ9Xsa6CBcE2jl48KWK8iW95aUs68mCMlXlT2wDkPwh+/6h4tRA N2imVbVUClj+vx9vUB6N2jO3Qu16pYSOF/IefrnXSVK3JxQ+L+J8WoJEwf0Syq0FPfbG Ah2SqzqeLNoX7NSSS0O1D4+1vdtkhHGBZyvI8Dsy5xXtzL5wk4CPdReRIBFS8eGveARP Ne9g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=a5S24n+G; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42845-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42845-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. [139.178.88.99]) by mx.google.com with ESMTPS id h17-20020a633851000000b005cd966560b7si5867527pgn.626.2024.01.29.06.00.41 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 06:00:41 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-42845-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) client-ip=139.178.88.99; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=a5S24n+G; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42845-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42845-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sv.mirrors.kernel.org (Postfix) with ESMTPS id 69195285B48 for ; Mon, 29 Jan 2024 13:58:00 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E62196772B; Mon, 29 Jan 2024 13:56:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="a5S24n+G" Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A5BB65BC9; Mon, 29 Jan 2024 13:56:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536591; cv=none; b=hUkN94yLnv5L3YsuOep0RmFJ5/q2RF1ysxGMfl0PQ21TO7WI3ThCFV/IAzMfhEWbOyl10daou4RLIx1TMISzvBDHEOLV4tudFbhd+B8CHuO0Rk0UmzFZgcYPMqQGcTrlfs2Opz/beVE0H8VNPRwnaUUFkmEnFCLRsLc7Z1U9Stk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536591; c=relaxed/simple; bh=+uOz9YVWBX/nm8+vTvC/BPDrlHz07CVvEpVx+5Qpgsc=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=jA9cebrgYSHM8GiagxM/s/ehjTC1TBa1GkVAXT2o2Ag1N9ZVoOv/l9mJnbywPara8Zfe6fA6kNvX6ZhvJScEnBUvykbjpHAPRLlrjgZEy/ScZmt24nrEWCrsCkXyRh0GQknvBrdGqSps3sFsDmIExtUDprPsUosxu+4TewwV3ZA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=a5S24n+G; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-51031ae95a1so1918479e87.0; Mon, 29 Jan 2024 05:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706536587; x=1707141387; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lSuvJDsIeu/noXriCuOK1Pr7/Fad1f+UMujsbtdvC+8=; b=a5S24n+G586rZPQeo8uVHpjWt895v/1P972pc9bnOYBKA2stmraqNwgoYrdnQjEwMs DgTR2KKXq6BAznSlSwwmbObakQgPhH7rRfZhWThrK/lGbxfBVfM81qc2P1FwBHaFlJ2v VhhNuYWzcNqvaoI6no8AMwjbpBTMDyDwm2LJsSi32YoA60ooswQ5rCwWMVzSFK6TDDZY 5ibFsKy8fxz4/eU8jiBzmJObZ/DUYzHDys9Tof6LZGaJCf4Zfci4waMnN/n5xSwDWFyW cnG2uBk8CqoWwe5m3+DgBJXzbC0Zr+hiH85FAzQcEdfKG4DyfZhnvbbqg99zoW+VhtHb 1v9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706536587; x=1707141387; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lSuvJDsIeu/noXriCuOK1Pr7/Fad1f+UMujsbtdvC+8=; b=WJx8dJWpx5l8qqR19WZZUa/Q9hijV7Cx6Hfh+G6mO2PZYNFW31KBOZsuBJsnuK7X9D qKzxJAx2G4rv6mkG/pkLKBq/Clu+RjQYAOBLEezAF78FT4i82Thb3Oli34/etSoDJc3r 8muDv33Mt6gLAcaOGHvAGF82Hg46VOlRItAi/JK0M1//VTG6cCMOBB8jHBDlmr6OtUNH A4CB7Wz7DLfB8xSzjvR8rwx6jpKSAFPIQkXyx5di4WbLXNuwA2reiee51AbByewVB1UI sT+An+2KXEtI5cIIS+KRb4qbRosI07u7HKeuUC2ecli8gB9ibXll1uqSwu/Lk5QYOm7b rtNg== X-Gm-Message-State: AOJu0YwZycI11uvHxPJAQIaBazjPHAGsbC0c+7vHJVFkb0WRXXZjr9z7 21tUefCz2VsCMBpXNc9maLhbGClLg6LIY5oJ1cNfrvPA/eqq8H8Z X-Received: by 2002:a05:6512:e8f:b0:511:f41:6144 with SMTP id bi15-20020a0565120e8f00b005110f416144mr2458512lfb.61.1706536586965; Mon, 29 Jan 2024 05:56:26 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:5616:a18c:ea50:2995]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b0033aed46956csm3058057wrb.80.2024.01.29.05.56.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:56:25 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v6 3/4] pinctrl: renesas: pinctrl-rzg2l: Add the missing port pins P19 to P28 Date: Mon, 29 Jan 2024 13:55:55 +0000 Message-Id: <20240129135556.63466-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789433574489811088 X-GMAIL-MSGID: 1789433574489811088 From: Lad Prabhakar Add the missing port pins P19 to P28 for RZ/Five SoC. These additional pins provide expanded capabilities and are exclusive to the RZ/Five SoC. Couple of port pins have different configuration and are not identical for the complete port so introduce struct rzg2l_variable_pin_cfg to handle such cases and introduce the PIN_CFG_VARIABLE macro. The actual pin config is then assigned in rzg2l_pinctrl_get_variable_pin_cfg(). Add an additional check in rzg2l_gpio_get_gpioint() to only allow GPIO pins which support interrupt facility. While at define RZG2L_GPIO_PORT_PACK() using RZG2L_GPIO_PORT_SPARSE_PACK(). Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- drivers/pinctrl/renesas/pinctrl-rzg2l.c | 213 +++++++++++++++++++++++- 1 file changed, 204 insertions(+), 9 deletions(-) diff --git a/drivers/pinctrl/renesas/pinctrl-rzg2l.c b/drivers/pinctrl/renesas/pinctrl-rzg2l.c index 33ea5f8dc998..ac44b0f9dfa7 100644 --- a/drivers/pinctrl/renesas/pinctrl-rzg2l.c +++ b/drivers/pinctrl/renesas/pinctrl-rzg2l.c @@ -57,6 +57,8 @@ #define PIN_CFG_IOLH_C BIT(13) #define PIN_CFG_SOFT_PS BIT(14) #define PIN_CFG_OEN BIT(15) +#define PIN_CFG_VARIABLE BIT(16) +#define PIN_CFG_NOGPIO_INT BIT(17) #define RZG2L_MPXED_COMMON_PIN_FUNCS(group) \ (PIN_CFG_IOLH_##group | \ @@ -76,17 +78,23 @@ PIN_CFG_FILNUM | \ PIN_CFG_FILCLKSEL) -/* - * n indicates number of pins in the port, a is the register index - * and f is pin configuration capabilities supported. - */ #define PIN_CFG_PIN_MAP_MASK GENMASK_ULL(35, 28) #define PIN_CFG_PIN_REG_MASK GENMASK(27, 20) #define PIN_CFG_MASK GENMASK(19, 0) -#define RZG2L_GPIO_PORT_PACK(n, a, f) ((((1ULL << (n)) - 1) << 28) | \ - FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ - FIELD_PREP_CONST(PIN_CFG_MASK, (f))) +/* + * m indicates the bitmap of supported pins, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_SPARSE_PACK(m, a, f) (FIELD_PREP_CONST(PIN_CFG_PIN_MAP_MASK, (m)) | \ + FIELD_PREP_CONST(PIN_CFG_PIN_REG_MASK, (a)) | \ + FIELD_PREP_CONST(PIN_CFG_MASK, (f))) + +/* + * n indicates number of pins in the port, a is the register index + * and f is pin configuration capabilities supported. + */ +#define RZG2L_GPIO_PORT_PACK(n, a, f) RZG2L_GPIO_PORT_SPARSE_PACK((1ULL << (n)) - 1, (a), (f)) /* * BIT(63) indicates dedicated pin, p is the register index while @@ -200,6 +208,18 @@ struct rzg2l_dedicated_configs { u64 config; }; +/** + * struct rzg2l_variable_pin_cfg - pin data cfg + * @cfg: port pin configuration + * @port: port number + * @pin: port pin + */ +struct rzg2l_variable_pin_cfg { + u32 cfg:20; + u32 port:5; + u32 pin:3; +}; + struct rzg2l_pinctrl_data { const char * const *port_pins; const u64 *port_pin_configs; @@ -208,6 +228,8 @@ struct rzg2l_pinctrl_data { unsigned int n_port_pins; unsigned int n_dedicated_pins; const struct rzg2l_hwcfg *hwcfg; + const struct rzg2l_variable_pin_cfg *variable_pin_cfg; + unsigned int n_variable_pin_cfg; }; /** @@ -243,6 +265,143 @@ struct rzg2l_pinctrl { static const u16 available_ps[] = { 1800, 2500, 3300 }; +#ifdef CONFIG_RISCV +static u64 rzg2l_pinctrl_get_variable_pin_cfg(struct rzg2l_pinctrl *pctrl, + u64 pincfg, + unsigned int port, + u8 pin) +{ + unsigned int i; + + for (i = 0; i < pctrl->data->n_variable_pin_cfg; i++) { + if (pctrl->data->variable_pin_cfg[i].port == port && + pctrl->data->variable_pin_cfg[i].pin == pin) + return (pincfg & ~PIN_CFG_VARIABLE) | pctrl->data->variable_pin_cfg[i].cfg; + } + + return 0; +} + +static const struct rzg2l_variable_pin_cfg r9a07g043f_variable_pin_cfg[] = { + { + .port = 20, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 6, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 20, + .pin = 7, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT + }, + { + .port = 23, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 23, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 0, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 1, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 2, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 3, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 4, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_NOGPIO_INT, + }, + { + .port = 24, + .pin = 5, + .cfg = PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT, + }, +}; +#endif + static void rzg2l_pinctrl_set_pfc_mode(struct rzg2l_pinctrl *pctrl, u8 pin, u8 off, u8 func) { @@ -1446,6 +1605,25 @@ static const u64 r9a07g043_gpio_configs[] = { RZG2L_GPIO_PORT_PACK(2, 0x20, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(4, 0x21, RZG2L_MPXED_PIN_FUNCS), RZG2L_GPIO_PORT_PACK(6, 0x22, RZG2L_MPXED_PIN_FUNCS), +#ifdef CONFIG_RISCV + /* Below additional port pins (P19 - P28) are exclusively available on RZ/Five SoC only */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x06, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_FILONOFF | PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P19 */ + RZG2L_GPIO_PORT_PACK(8, 0x07, PIN_CFG_VARIABLE), /* P20 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x08, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P21 */ + RZG2L_GPIO_PORT_PACK(4, 0x09, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_PUPD | + PIN_CFG_IEN | PIN_CFG_NOGPIO_INT), /* P22 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x3e, 0x0a, PIN_CFG_VARIABLE), /* P23 */ + RZG2L_GPIO_PORT_PACK(6, 0x0b, PIN_CFG_VARIABLE), /* P24 */ + RZG2L_GPIO_PORT_SPARSE_PACK(0x2, 0x0c, PIN_CFG_IOLH_B | PIN_CFG_SR | PIN_CFG_FILONOFF | + PIN_CFG_FILNUM | PIN_CFG_FILCLKSEL | + PIN_CFG_NOGPIO_INT), /* P25 */ + 0x0, /* P26 */ + 0x0, /* P27 */ + RZG2L_GPIO_PORT_PACK(6, 0x0f, RZG2L_MPXED_PIN_FUNCS | PIN_CFG_NOGPIO_INT), /* P28 */ +#endif }; static const u64 r9a08g045_gpio_configs[] = { @@ -1606,12 +1784,18 @@ static const struct rzg2l_dedicated_configs rzg3s_dedicated_pins[] = { PIN_CFG_IO_VMC_SD1)) }, }; -static int rzg2l_gpio_get_gpioint(unsigned int virq, const struct rzg2l_pinctrl_data *data) +static int rzg2l_gpio_get_gpioint(unsigned int virq, struct rzg2l_pinctrl *pctrl) { + const struct pinctrl_pin_desc *pin_desc = &pctrl->desc.pins[virq]; + const struct rzg2l_pinctrl_data *data = pctrl->data; + u64 *pin_data = pin_desc->drv_data; unsigned int gpioint; unsigned int i; u32 port, bit; + if (*pin_data & PIN_CFG_NOGPIO_INT) + return -EINVAL; + port = virq / 8; bit = virq % 8; @@ -1721,7 +1905,7 @@ static int rzg2l_gpio_child_to_parent_hwirq(struct gpio_chip *gc, unsigned long flags; int gpioint, irq; - gpioint = rzg2l_gpio_get_gpioint(child, pctrl->data); + gpioint = rzg2l_gpio_get_gpioint(child, pctrl); if (gpioint < 0) return gpioint; @@ -1907,6 +2091,13 @@ static int rzg2l_pinctrl_register(struct rzg2l_pinctrl *pctrl) if (i && !(i % RZG2L_PINS_PER_PORT)) j++; pin_data[i] = pctrl->data->port_pin_configs[j]; +#ifdef CONFIG_RISCV + if (pin_data[i] & PIN_CFG_VARIABLE) + pin_data[i] = rzg2l_pinctrl_get_variable_pin_cfg(pctrl, + pin_data[i], + j, + i % RZG2L_PINS_PER_PORT); +#endif pins[i].drv_data = &pin_data[i]; } @@ -2058,6 +2249,10 @@ static struct rzg2l_pinctrl_data r9a07g043_data = { .n_port_pins = ARRAY_SIZE(r9a07g043_gpio_configs) * RZG2L_PINS_PER_PORT, .n_dedicated_pins = ARRAY_SIZE(rzg2l_dedicated_pins.common), .hwcfg = &rzg2l_hwcfg, +#ifdef CONFIG_RISCV + .variable_pin_cfg = r9a07g043f_variable_pin_cfg, + .n_variable_pin_cfg = ARRAY_SIZE(r9a07g043f_variable_pin_cfg), +#endif }; static struct rzg2l_pinctrl_data r9a07g044_data = { From patchwork Mon Jan 29 13:55:56 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 193487 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2087:b0:106:209c:c626 with SMTP id gs7csp580148dyb; Mon, 29 Jan 2024 05:58:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEtSRrv8UgNrFKntjb3A0ALoZ0ZLy9EZ4Lw3RgelbH+kFAy/fjxZvPkdzCysmXuuYBoyurq X-Received: by 2002:a17:906:298d:b0:a31:7aca:a429 with SMTP id x13-20020a170906298d00b00a317acaa429mr4406733eje.4.1706536680606; Mon, 29 Jan 2024 05:58:00 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706536680; cv=pass; d=google.com; s=arc-20160816; b=I4A2jcL91Db5Y/iWErywmjUZ/tfgbrW+Prik5W+FjbXZg91gvbg8HTL+ZD5F3fT5Pk 0tRjzFdYA9kwA8kNUat5wOlj7tHu//5xq5KzzwZeFkiJ30arRKXsQfJvuugmKPW16xRb ltYo4YPIOzGwO6i3PjvA5mKTD3Pv5JWDGwiwb3uXYxRB5AlpY9Z/i57iwwP0wkvU8h41 DMyrDAA0VNMS6gszoIZRndg48CgiiblBXI3Ew7wogUIokSSBnQWvLmCaz1mUb3Axa0Jq ytnUiSRy0RWardWZUF2fhngbmnh1EAfEqKbTOvcGLAtpxtxCqPX+HCkYMGg+xWVlogGa kaqQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=WclvSvESBcB1ccyxeqjrdGj+frspJc0esD0QtgwrkCo=; fh=9jERyHaBVkSYjvKDLj7G39aR/G88vFciZPp35CZ8FfY=; b=ksl9MAdytnQ+OKXfS6uPgHDCUq7fXoK8KV5BpNMxghROVdHruFegPEqn6763/5qPt2 rL4FPLCT/7/IP6KpquFk31yT/IWk/Q9w7pd9di6TKJaZh70WRyGfbX+C3gFShGgyws/H fcj0cMrsH/A3ZUPRy1gsN4EStRDEK3t/k5XAeVSo1DF0lG46lkADAGMg4CIuyRdWCOiA hwZ3IuM1GGx2sDeE6IjABUNhg0lyzz68svLLfxs+HrmBJYUxo5XqJzJeg3LxOxPe6uWC nRe2PnVyLZ+pIdo76k+mxx/F7PeEXJ5+JIL3W7oQNiRWKqJRGwI+Vid8+9HKVVY5BVvy NlHQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="UPdF4R/4"; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42846-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42846-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id s22-20020a170906355600b00a28e70f483dsi3410952eja.164.2024.01.29.05.58.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:58:00 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-42846-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b="UPdF4R/4"; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-42846-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-42846-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 496141F22309 for ; Mon, 29 Jan 2024 13:57:54 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A449466B5B; Mon, 29 Jan 2024 13:56:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="UPdF4R/4" Received: from mail-wr1-f43.google.com (mail-wr1-f43.google.com [209.85.221.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3F11965BBC; Mon, 29 Jan 2024 13:56:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536591; cv=none; b=QprtkRb3e9ZQ8u0sKCeEJqEZwgnxN0iiDgPD+XYiqNl9kVXU1hpxVY2To8W2wAerIlSTonAIGiZ5d0i1cXX9KK7dwjOifZS/kGdSFGI107YdmnjvB2B6qrZsb/dT4265kg9xwoVtpFtv2M65CL+JQLeJHM6LyGJg0y8YA3AfPFQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706536591; c=relaxed/simple; bh=FGSEzWn1LxVZjMRgXwDQ9AesgqJ5I8CYMNMEr12U7U8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=ao9lcxjSoCDnqksUnkiwu0Qc6tBuu8lHwxUpECVQsUXZm69/BjCC/aXHGU9guS0Bcbxkn77hB4AGQm84t5M23Jc0SpOGIdU7odJhugwvimycHYCnlO33ngu1s9ygmM50k3UBr1o2oVOPNmPqFjHgUoRXsjXKH/XnJ6CPdp4vZmQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=UPdF4R/4; arc=none smtp.client-ip=209.85.221.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wr1-f43.google.com with SMTP id ffacd0b85a97d-33ae3cc8a6aso1439272f8f.2; Mon, 29 Jan 2024 05:56:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1706536588; x=1707141388; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WclvSvESBcB1ccyxeqjrdGj+frspJc0esD0QtgwrkCo=; b=UPdF4R/4HpA0gTA5h7cj7VbUvWgfDWse7bQ3LQ9tIRNuF4M8u5mMelc5FlsZhZipH1 jzrOf2dBLibSfYiV1iwNCJTYVJ7SvnyFpFnC8oDTXxtmqDNAaeJkL8TIrAkCvlOWb3Rc k2f++sgdECqMthvxKaBRZQy/wPzPhqMwKWLWpDMMsdpCZEliTT7ncJT1Chk8UgExMR1V H+DGNpoYS7kEQuZAge5sPH4iI/Yg0Flwc3KZ9I3Jy7rvEWtNKKM6JNagRy5VwhfqjWE5 fJ22P2aWtnIZFGJtqLk+3j1R+0LWQkzsoVHMG45o17LHZZIVijLfZV+vd1yugUC2VYII TRmg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1706536588; x=1707141388; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WclvSvESBcB1ccyxeqjrdGj+frspJc0esD0QtgwrkCo=; b=nXUOOPoplC0BNmwaHyjFbN5RUPqNlEPceFmsuPyMkxcEXLvFxs/53wk3jf+C1wrLba aSwQ4H2obu4hmUXaxi1LUz1Yd8b8g0hFmpYjnunuUUmkT5FR1SBK4bAyoOMhPP/GzMKl 6TndNIImjXyHO+DMCkhFhw2y3qT1ZKXX9d7aXa1rF/N+6icd9MhiXEof5cEFJouQ0jns BR7cnHffoAesYACi8j/BasagO1BO5ECcmdxjan3h8mayd7DEHZ7uNg7GHiEg8yXQxpQ3 5I2km9KTF6NtddoTxScC2ALLcWmkMKpKeTn4ORARzNj3GJ2HctCjo9rDFx4EmwgNoAwJ 5Tcw== X-Gm-Message-State: AOJu0YypyoHlK9YpVF98iMqi7WNURn+CEfqTz8cIOxTGPxiPuWCobA/v Iq7kyEPl/AHSOe/61iWxWcYc6ddFfLdeAYf2wC3Eb7d3pUAkJS18 X-Received: by 2002:a5d:6da3:0:b0:33a:ed3b:3739 with SMTP id u3-20020a5d6da3000000b0033aed3b3739mr2973996wrs.30.1706536588205; Mon, 29 Jan 2024 05:56:28 -0800 (PST) Received: from prasmi.home ([2a00:23c8:2500:a01:5616:a18c:ea50:2995]) by smtp.gmail.com with ESMTPSA id bh5-20020a05600005c500b0033aed46956csm3058057wrb.80.2024.01.29.05.56.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Jan 2024 05:56:27 -0800 (PST) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Magnus Damm , Linus Walleij Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, Prabhakar , Biju Das , Claudiu Beznea , Lad Prabhakar Subject: [PATCH v6 4/4] riscv: dts: renesas: r9a07g043f: Update gpio-ranges property Date: Mon, 29 Jan 2024 13:55:56 +0000 Message-Id: <20240129135556.63466-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20240129135556.63466-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789433406721312969 X-GMAIL-MSGID: 1789433406721312969 From: Lad Prabhakar On RZ/Five we have additional pins compared to the RZ/G2UL SoC so update the gpio-ranges property in RZ/Five SoC DTSI. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi index d2272a0bfb61..aa3b1d2b999d 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi @@ -46,6 +46,10 @@ cpu0_intc: interrupt-controller { }; }; +&pinctrl { + gpio-ranges = <&pinctrl 0 0 232>; +}; + &soc { dma-noncoherent; interrupt-parent = <&plic>;