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[2620:137:e000::1:20]) by mx.google.com with ESMTP id x13-20020a50ba8d000000b004597aa082ddsi8772607ede.257.2022.11.14.18.57.39; Mon, 14 Nov 2022 18:58:06 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=eHKUxvms; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232553AbiKOCyo (ORCPT + 99 others); Mon, 14 Nov 2022 21:54:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38012 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232514AbiKOCye (ORCPT ); Mon, 14 Nov 2022 21:54:34 -0500 Received: from mail-ej1-x632.google.com (mail-ej1-x632.google.com [IPv6:2a00:1450:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 580BE13F95 for ; Mon, 14 Nov 2022 18:54:31 -0800 (PST) Received: by mail-ej1-x632.google.com with SMTP id k2so32947652ejr.2 for ; Mon, 14 Nov 2022 18:54:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f8ThKzFAu45hOG2t4OpvstiYsckpTwgeVuyWuBxUZV0=; b=eHKUxvmsq1tf63Ca+kF/7sozldkxCqBu02HHCOpSR0bWsYV2VLU8EEe2uUknl4v4wi LrtNcg9gfQhJqpUyaQ4oIwlv0BSyz/p/xJcZLviM+bmja72AQga1KhFRsNR200tsSgrM r7h+Hz1N0iGHHnCddNfJc3M0TpzlkbRkhbLiJ/bSLKkjBgNaajP3EGZ9Bz8vHNnF8Fm9 rRhXZm+s9r3XDD7OR4Jl8yaf2fs626LdnQSGc8yFOho8qByGEH3escOAOvuylzD/rl/o 443eS83q+axrhVhJeG2pBSBq8RrSWhSclR54oe/ifnZYVB10Jy4S2Bz7T/TkhxbsV8CR KCbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f8ThKzFAu45hOG2t4OpvstiYsckpTwgeVuyWuBxUZV0=; b=E0pgnEUbC480bfmii7EUxWg7dv1mU34dQ1DDaTz8I92pTGM7JxqxVqA8eNQDhndWDZ 4xjWOVwPS1Dlt9LUUGEFMl2YCC+yqni1Jm0TXDWq03yjJjaDwdLmDISAjhGOryxqMVAg BsqDpnUIkwZmP56V8/PTdYPPyBDVnQc7lQyvGWZisDOvw0wVYcifEKYSJSxvLpX1nAcl /98OSSutbvzCkWPu2iJSG49B0C+3XnNaCgsEDTP5pB0CKap1+QyAWPHIN7t4PtV/Hpkh BAKAjz5vMYuRVkXjI6WvwmwPBYmU1eyKkWNjMxsqi67SLzXtfIoj4jXDccArWqBu/m/3 k9NA== X-Gm-Message-State: ANoB5pnrO6vmlO4Np5RBHrdPXHzNGONYtFmF50CLrqtBdRMC5FVY2OGJ ocqa2LVlocZ5S2jXy8mJrj6Cwg== X-Received: by 2002:a17:906:abd7:b0:7ad:b791:1390 with SMTP id kq23-20020a170906abd700b007adb7911390mr12063972ejb.279.1668480869824; Mon, 14 Nov 2022 18:54:29 -0800 (PST) Received: from c64.fritz.box ([2a01:2a8:8108:8301:7643:bec8:f62b:b074]) by smtp.gmail.com with ESMTPSA id l9-20020a1709063d2900b0073d9a0d0cbcsm4861177ejf.72.2022.11.14.18.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 14 Nov 2022 18:54:29 -0800 (PST) From: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= To: linux-mediatek@lists.infradead.org Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com Subject: [PATCH v2 01/15] arm64: dts: mediatek: Initial mt8365-evk support Date: Tue, 15 Nov 2022 03:54:07 +0100 Message-Id: <20221115025421.59847-2-bero@baylibre.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221115025421.59847-1-bero@baylibre.com> References: <20221107211001.257393-1-bero@baylibre.com> <20221115025421.59847-1-bero@baylibre.com> MIME-Version: 1.0 X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1748873977122490161?= X-GMAIL-MSGID: =?utf-8?q?1749529224146895727?= From: Fabien Parent This adds minimal support for the Mediatek 8365 SOC and the EVK reference board, allowing the board to boot to initramfs with serial port I/O. GPIO keys are supported, MMC is partially supported (needs the clocks driver for full support). Signed-off-by: Fabien Parent [bero@baylibre.com: Removed parts depending on drivers that aren't upstream yet, cleanups] Signed-off-by: Bernhard Rosenkränzer --- arch/arm64/boot/dts/mediatek/Makefile | 1 + arch/arm64/boot/dts/mediatek/mt8365-evk.dts | 344 +++++++++++ arch/arm64/boot/dts/mediatek/mt8365.dtsi | 601 ++++++++++++++++++++ 3 files changed, 946 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8365-evk.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8365.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 0ec90cb3ef289..e668fd50a3326 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -46,4 +46,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts new file mode 100644 index 0000000000000..74e0f75231637 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -0,0 +1,344 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2021-2022 BayLibre, SAS. + * Authors: + * Fabien Parent + * Bernhard Rosenkränzer + */ + +/dts-v1/; + +#include +#include +#include +#include "mt8365.dtsi" + +/ { + model = "MediaTek MT8365 Open Platform EVK"; + compatible = "mediatek,mt8365-evk", "mediatek,mt8365"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + input-name = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys>; + + key-volume-up { + gpios = <&pio 24 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = ; + wakeup-source; + debounce-interval = <15>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0 0xc0000000>; + }; + + usb_otg_vbus: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 16 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&pio { + dpi_func_pins: dpi-func-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + drive-strength = ; + }; + }; + + dpi_idle_pins: dpi-idle-pins { + pins { + pinmux = , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + }; + }; + + gpio_keys: gpio-keys-pins { + pins { + pinmux = ; + bias-pull-up; + input-enable; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = , + ; + mediatek,pull-up-adv = <3>; + mediatek,drive-strength-adv = <00>; + bias-pull-up; + }; + }; + + ite_pins: ite-pins { + pins-rst-ite { + pinmux = ; + output-high; + }; + + pins-irq-ite { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-pwr { + pinmux = , + ; + output-high; + }; + }; + + mmc0_pins_default: mmc0-default-pins { + pins-clk { + pinmux = ; + bias-pull-down; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + bias-pull-up; + }; + + pins-rst { + pinmux = ; + bias-pull-up; + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + + pins-ds { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-rst { + pinmux = ; + drive-strength = ; + bias-pull-up; + }; + }; + + mmc1_pins_default: mmc1-default-pins { + pins-cd { + pinmux = ; + bias-pull-up; + }; + + pins-clk { + pinmux = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + bias-pull-up = ; + }; + }; + + mmc1_pins_uhs: mmc1-uhs-pins { + pins-clk { + pinmux = ; + drive-strength = ; + bias-pull-down = ; + }; + + pins-cmd-dat { + pinmux = , + , + , + , + ; + input-enable; + drive-strength = ; + bias-pull-up = ; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = , + ; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = , + ; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = , + ; + }; + }; + + usb_pins: usb-pins { + pins-id { + pinmux = ; + input-enable; + bias-pull-up; + }; + + pins-usb0-vbus { + pinmux = ; + output-high; + }; + + pin-usb1-vbus { + pinmux = ; + output-high; + }; + }; + + pwm_pins: pwm-pins { + pins { + pinmux = , + ; + }; + }; +}; + +&pwm { + pinctrl-0 = <&pwm_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi new file mode 100644 index 0000000000000..1cf2172081b20 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -0,0 +1,601 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * (C) 2018 MediaTek Inc. + * Copyright (C) 2022 BayLibre SAS + * Fabien Parent + * Bernhard Rosenkränzer + */ +#include +#include +#include +#include +#include + +/ { + compatible = "mediatek,mt8365"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus: cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0: cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + #cooling-cells = <2>; + enable-method = "psci"; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 128 KiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@43000000 { + no-map; + reg = <0 0x43000000 0 0x20000>; + }; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x80000>, + <0 0x0c080000 0 0x80000>; + + interrupts = ; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8365-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + pericfg: syscon@10003000 { + compatible = "mediatek,mt8365-pericfg", "syscon"; + reg = <0 0x10003000 0 0x1000>; + #clock-cells = <1>; + }; + + syscfg_pctl: syscfg-pctl@10005000 { + compatible = "mediatek,mt8365-syscfg", "syscon"; + reg = <0 0x10005000 0 0x1000>; + }; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8365-wdt", + "mediatek,mt6589-wdt"; + reg = <0 0x10007000 0 0x100>; + #reset-cells = <1>; + }; + + gpt: apxgpt@10008000 { + compatible = "mediatek,mt8365-timer", + "mediatek,mt6577-timer"; + reg = <0 0x10008000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_SYS_26M_D2>; + clock-names = "clk13m"; + }; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8365-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + pwrap: pwrap@1000d000 { + compatible = "mediatek,mt8365-pwrap"; + reg = <0 0x1000d000 0 0x1000>; + reg-names = "pwrap"; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWRAP_SPI>, + <&infracfg CLK_IFR_PMIC_AP>, + <&infracfg CLK_IFR_PWRAP_SYS>, + <&infracfg CLK_IFR_PWRAP_TMR>; + clock-names = "spi", "wrap", "sys", "tmr"; + }; + + keypad: keypad@10010000 { + compatible = "mediatek,mt6779-keypad"; + reg = <0 0x10010000 0 0x1000>; + wakeup-source; + interrupts = ; + clocks = <&clk26m>; + clock-names = "kpd"; + status = "disabled"; + }; + + mcucfg: syscon@10200000 { + compatible = "mediatek,mt8365-mcucfg", "syscon"; + reg = <0 0x10200000 0 0x2000>; + #clock-cells = <1>; + }; + + sysirq: interrupt-controller@10200a80 { + compatible = "mediatek,mt8365-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x10200a80 0 0x20>; + }; + + infracfg: infracfg@1020e000 { + compatible = "mediatek,mt8365-infracfg", "syscon"; + reg = <0 0x1020e000 0 0x1000>; + }; + + rng: rng@1020f000 { + compatible = "mediatek,mt8365-rng", + "mediatek,mt7623-rng"; + reg = <0 0x1020f000 0 0x100>; + clocks = <&infracfg CLK_IFR_TRNG>; + clock-names = "rng"; + }; + + apdma: dma-controller@11000280 { + compatible = "mediatek,mt8365-uart-dma", + "mediatek,mt6577-uart-dma"; + reg = <0 0x11000280 0 0x80>, + <0 0x11000300 0 0x80>, + <0 0x11000380 0 0x80>, + <0 0x11000400 0 0x80>, + <0 0x11000580 0 0x80>, + <0 0x11000600 0 0x80>; + interrupts = , + , + , + , + , + ; + dma-requests = <6>; + clocks = <&infracfg CLK_IFR_AP_DMA>; + clock-names = "apdma"; + #dma-cells = <1>; + }; + + auxadc: adc@11001000 { + compatible = "mediatek,mt8365-auxadc", + "mediatek,mt8173-auxadc"; + reg = <0 0x11001000 0 0x1000>; + clocks = <&infracfg CLK_IFR_AUXADC>; + clock-names = "main"; + #io-channel-cells = <1>; + }; + + uart0: serial@11002000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11002000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>; + clock-names = "baud", "bus"; + dmas = <&apdma 0>, <&apdma 1>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart1: serial@11003000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11003000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>; + clock-names = "baud", "bus"; + dmas = <&apdma 2>, <&apdma 3>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + uart2: serial@11004000 { + compatible = "mediatek,mt8365-uart", + "mediatek,mt6577-uart"; + reg = <0 0x11004000 0 0x1000>; + interrupts = ; + clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>; + clock-names = "baud", "bus"; + dmas = <&apdma 4>, <&apdma 5>; + dma-names = "tx", "rx"; + status = "disabled"; + }; + + pwm: pwm@11006000 { + compatible = "mediatek,mt8365-pwm"; + reg = <0 0x11006000 0 0x1000>; + #pwm-cells = <2>; + interrupts = ; + clocks = <&infracfg CLK_IFR_PWM_HCLK>, + <&infracfg CLK_IFR_PWM>, + <&infracfg CLK_IFR_PWM1>, + <&infracfg CLK_IFR_PWM2>, + <&infracfg CLK_IFR_PWM3>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; + }; + + i2c0: i2c@11007000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11007000 0 0xa0>, + <0 0x11000080 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C0_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c1: i2c@11008000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11008000 0 0xa0>, + <0 0x11000100 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C1_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c2: i2c@11009000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x11009000 0 0xa0>, + <0 0x11000180 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C2_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi: spi@1100a000 { + compatible = "mediatek,mt8365-spi", + "mediatek,mt7622-spi"; + reg = <0 0x1100a000 0 0x100>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>, + <&topckgen CLK_TOP_SPI_SEL>, + <&infracfg CLK_IFR_SPI0>; + clock-names = "parent-clk", "sel-clk", "spi-clk"; + status = "disabled"; + }; + + thermal: thermal@1100b000 { + compatible = "mediatek,mt8365-thermal"; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_IFR_THERM>, + <&infracfg CLK_IFR_AUXADC>; + clock-names = "therm", "auxadc"; + mediatek,auxadc = <&auxadc>; + mediatek,apmixedsys = <&apmixedsys>; + nvmem-cells = <&thermal_calibration>; + nvmem-cell-names = "calibration-data"; + #thermal-sensor-cells = <1>; + }; + + i2c3: i2c@1100f000 { + compatible = "mediatek,mt8365-i2c", + "mediatek,mt8168-i2c"; + reg = <0 0x1100f000 0 0xa0>, + <0 0x11000200 0 0x80>; + interrupts = ; + clock-div = <1>; + clocks = <&infracfg CLK_IFR_I2C3_AXI>, + <&infracfg CLK_IFR_AP_DMA>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ssusb: usb@11201000 { + compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3"; + reg = <0 0x11201000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = ; + phys = <&u2port0 PHY_TYPE_USB2>, + <&u2port1 PHY_TYPE_USB2>; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + usb_host: usb@11200000 { + compatible = "mediatek,mt8365-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = ; + clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>, + <&infracfg CLK_IFR_SSUSB_REF>, + <&infracfg CLK_IFR_SSUSB_SYS>, + <&infracfg CLK_IFR_ICUSB>, + <&infracfg CLK_IFR_SSUSB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", + "dma_ck", "xhci_ck"; + status = "disabled"; + }; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11cd0000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>, + <&infracfg CLK_IFR_MSDC0_HCLK>, + <&infracfg CLK_IFR_MSDC0_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + mmc1: mmc@11240000 { + compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc"; + reg = <0 0x11240000 0 0x1000>, + <0 0x11c90000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>, + <&infracfg CLK_IFR_MSDC1_HCLK>, + <&infracfg CLK_IFR_MSDC1_SRC>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + ethernet: ethernet@112a0000 { + compatible = "mediatek,mt8365-eth"; + reg = <0 0x112a0000 0 0x1000>; + mediatek,pericfg = <&infracfg>; + interrupts = ; + clocks = <&topckgen CLK_TOP_ETH_SEL>, + <&infracfg CLK_IFR_NIC_AXI>, + <&infracfg CLK_IFR_NIC_SLV_AXI>; + clock-names = "core", "reg", "trans"; + status = "disabled"; + }; + + mipi_tx0: dsi-phy@11c00000 { + compatible = "mediatek,mt8365-mipi-tx", + "mediatek,mt8183-mipi-tx"; + reg = <0 0x11c00000 0 0x800>; + clocks = <&clk26m>; + clock-names = "ref_clk"; + #clock-cells = <0>; + #phy-cells = <0>; + clock-output-names = "mipi_tx0_pll"; + }; + + efuse: efuse@11c50000 { + compatible = "mediatek,mt8365-efuse", "mediatek,efuse"; + reg = <0 0x11c50000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + thermal_calibration: calib@180 { + reg = <0x180 0xc>; + }; + }; + + u3phy: t-phy@11cc0000 { + compatible = "mediatek,mt8365-tphy", + "mediatek,generic-tphy-v2"; + #address-cells = <2>; + #size-cells = <2>; + #phy-cells = <1>; + ranges; + + u2port0: usb-phy@11cc0000 { + reg = <0 0x11cc0000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + + u2port1: usb-phy@11cc1000 { + reg = <0 0x11cc1000 0 0x400>; + clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>, + <&topckgen CLK_TOP_USB20_48M_EN>; + clock-names = "ref", "da_ref"; + #phy-cells = <1>; + }; + }; + + mfgcfg: syscon@13000000 { + compatible = "mediatek,mt8365-mfgcfg", "syscon"; + reg = <0 0x13000000 0 0x1000>; + #clock-cells = <1>; + }; + + mmsys: syscon@14000000 { + compatible = "mediatek,mt8365-mmsys", "syscon"; + reg = <0 0x14000000 0 0x1000>; + #clock-cells = <1>; + }; + + camsys: syscon@15000000 { + compatible = "mediatek,mt8365-imgsys", "syscon"; + reg = <0 0x15000000 0 0x1000>; + #clock-cells = <1>; + }; + + vdecsys: syscon@16000000 { + compatible = "mediatek,mt8365-vdecsys", "syscon"; + reg = <0 0x16000000 0 0x1000>; + #clock-cells = <1>; + }; + + vencsys: syscon@17000000 { + compatible = "mediatek,mt8365-vencsys", "syscon"; + reg = <0 0x17000000 0 0x1000>; + #clock-cells = <1>; + }; + + apu: syscon@19020000 { + compatible = "mediatek,mt8365-apu", "syscon"; + reg = <0 0x19020000 0 0x1000>; + #clock-cells = <1>; + }; + }; + + thermal-zones { + cpu_thermal: cpu-thermal { + polling-delay-passive = <1000>; /* milliseconds */ + polling-delay = <1000>; /* milliseconds */ + thermal-sensors = <&thermal 0>; + + trips { + threshold: trip-point0 { + temperature = <95000>; + hysteresis = <2000>; + type = "passive"; + }; + + target: trip-point1 { + temperature = <105000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpu_crit: cpu_crit0 { + temperature = <117000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + + cooling-maps { + map0 { + trip = <&target>; + cooling-device = + <&cpu0 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu1 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu2 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>, + <&cpu3 + THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + contribution = <100>; + }; + }; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = , + , + , + ; + }; +}; From patchwork Tue Nov 15 02:54:08 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20144 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484818wru; Mon, 14 Nov 2022 18:57:55 -0800 (PST) X-Google-Smtp-Source: AA0mqf6bTcTcpiCsj7eKVC7og5WGz5rm9GkK5SY1vQYci7TXD8jhzHhZTQpyOROaKzG4Rgsg9yXJ X-Received: by 2002:a17:906:4f12:b0:78d:502c:aeb5 with SMTP id t18-20020a1709064f1200b0078d502caeb5mr12372371eju.88.1668481075295; Mon, 14 Nov 2022 18:57:55 -0800 (PST) ARC-Seal: i=1; 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Signed-off-by: Fabien Parent Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/watchdog/mtk-wdt.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt index 762c62e428ef2..835af28b46de0 100644 --- a/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt +++ b/Documentation/devicetree/bindings/watchdog/mtk-wdt.txt @@ -20,6 +20,7 @@ Required properties: "mediatek,mt8516-wdt", "mediatek,mt6589-wdt": for MT8516 "mediatek,mt8192-wdt": for MT8192 "mediatek,mt8195-wdt", "mediatek,mt6589-wdt": for MT8195 + "mediatek,mt8365-wdt", "mediatek,mt6589-wdt": for MT8365 - reg : Specifies base physical address and size of the registers. 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Signed-off-by: Fabien Parent --- .../devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml index 7f79a06e76f59..ed582c6e7ea9c 100644 --- a/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml +++ b/Documentation/devicetree/bindings/iio/adc/mediatek,mt2701-auxadc.yaml @@ -38,6 +38,7 @@ properties: - mediatek,mt8188-auxadc - mediatek,mt8195-auxadc - mediatek,mt8516-auxadc + - mediatek,mt8365-auxadc - const: mediatek,mt8173-auxadc reg: From patchwork Tue Nov 15 02:54:10 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20135 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484491wru; Mon, 14 Nov 2022 18:56:32 -0800 (PST) X-Google-Smtp-Source: AA0mqf4U6BWNw0ytXYKTuSfzIC0c83PlkDJO+aspriHn2Hvi3CErAP127Hy3teR2UC8dplD/r8kh X-Received: by 2002:a50:ff14:0:b0:461:84de:7ac4 with SMTP id a20-20020a50ff14000000b0046184de7ac4mr13446615edu.206.1668480991905; Mon, 14 Nov 2022 18:56:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668480991; cv=none; d=google.com; s=arc-20160816; b=mTG0FEuz0ZI4zKb83TK9RfO80X2o0hlZpZ4q2ZYkQqfvxVqbVnu0RY3XmWfW0OTA1l 0+p54rjuM2YfX9x57N1aitMULD1fg4MmgOI+f8OFSuXEEG1TEYDrJaMnieRJ0nL5FTyH VavBk6KOt5jLuvPakK675/aXcCNkzaWvZEXsFnIND7fjB7sehZ0JihhngMaPVdCoFLxd 1yrvNtXFpCdjVPcFgoyY+D7EqyqX3MkI4TkAisUQeo1nfIaIV13AxlpJaV+B5gh6H0OH z/Mu4GZdPrp0UgSz+byKUD3O7SPNX9uVZGkBl68VN0gmrVycwzagbo5JR/YbQjMnRgCm w/bw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=qMx+8lnHYaoQJGJTnVIZj+JIYuaVktQaiA/S5krH6nY=; b=NLEA9Y8O2iJEh4W0VXky3AXMy4pFQwO0UwIMM+PHYMur24opGYGZ5dhOYTmKhnrHGC u6mdtEU3Y4PqmT2oJ3JXJrk9OywhhUTQO5YEb6mMUZZm2P9qJ9dFCmLmoFb6ovQQ6hP0 GfzRBs2iFW0lAm9CUieFdVl1EXdniIO8kxyhFmvuJUFw13tXW3eK/+DKgPViLhmcz1AM 5+3lTfSx0j+vMi3hxYtJcgrgXbyzYoUUr7MDG7Ee01puwrNznKRQhHd/mA8nyffWDywH b07HsPFobQAGzCpR6BUamJsrDmUNDeHTnycf9kE0S5spM40/oMuunIIMl+cxIyaPLq4H ZNSw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=nWwH779Y; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent Acked-by: Rob Herring --- Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 421563bf576cd..2cfed35bfd9e9 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -45,6 +45,10 @@ properties: - enum: - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c + - items: + - enum: + - mediatek,mt8365-i2c + - const: mediatek,mt8168-i2c reg: items: From patchwork Tue Nov 15 02:54:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20134 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484441wru; Mon, 14 Nov 2022 18:56:20 -0800 (PST) X-Google-Smtp-Source: AA0mqf45dnIlOJXhXYGXqtbhN3RwvFgWiCcYtxUyaVQ8G4eSWIkxAdU4ITGhCSi4c26EAztsaSMx X-Received: by 2002:a17:906:27cc:b0:7ad:f165:70c7 with SMTP id k12-20020a17090627cc00b007adf16570c7mr12145933ejc.503.1668480980163; Mon, 14 Nov 2022 18:56:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668480980; cv=none; d=google.com; s=arc-20160816; b=QAuzbKOegO8jQOJ16EJpCy6jUYxpH3en9lG2QW0RmXCLc7PPLksdvvOhY5HqpFqoAc qoZ9XuAElJTllOFVyxmb6jotoJKJ36we3pLWJE37Di0Sqcubl6E5zML859AkyadAX61J IFstnrzH1ExgbUcGEli7M5R1s2QFxThpKjkLKABit+9n6lGdsSey74YA/NwkMueFMgh7 7mDc5gcFkZFN0eFIndtEjtpe5Nzat+u3QJ5tzhMzRBNAdJPnXHEZuSHf2EhARIa0tbfm vPdwGm6vq90oyqGZFV+9Ey2arls7cOfryiXbxdwgdbO8ViRjwrM9UFj29vV620UjWrfM knBA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vmhZo5VNLi5fyIfm0Ikx5I/XDPVkL1i6Xe0lCAE5Xe4=; b=mbkrBKlVLBAUSfH9uhbapEgmbTbxsJQOo+zrnVC4k3bSsyxfMhilbQwXF1OlxKYBm2 K9TyrRuovv5BqAFDNIWHwzqY51RvSZMqEUsIOodfiApQN9byei6sMJc/lk8dQlgkH3RM ZcUYVt5LhQhFRZDO/FKym6NPLjG1zWaJ7lrOWY2ISgfU79t90xDFER7pngYJcTnR9X0z M8uz1rFzlLcSNVzj9SzUZq5wXsZmR11CHMc/gO9J9aI7UCHbL1OUPrZn04bP27jsWhdx XQxWv6rTxyCY11XbdN9APFPumfeTiCDAegJKSuAfZpKKuZss2wMd2icc4r/FCpkBKzP3 Uw5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=lt1TeCbl; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml index 80750b0f458a8..25934871a4d85 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtu3.yaml @@ -27,6 +27,7 @@ properties: - mediatek,mt8188-mtu3 - mediatek,mt8192-mtu3 - mediatek,mt8195-mtu3 + - mediatek,mt8365-mtu3 - const: mediatek,mtu3 reg: From patchwork Tue Nov 15 02:54:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20138 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484555wru; Mon, 14 Nov 2022 18:56:45 -0800 (PST) X-Google-Smtp-Source: AA0mqf7wNrobEnqAjWhsS0vltTIEQsg0+wQ/LeZr0h7JLXXg+F4WRA0nXTzjLc3HI34V7mT2+B5r X-Received: by 2002:a17:906:2f11:b0:78d:cc87:b1d7 with SMTP id v17-20020a1709062f1100b0078dcc87b1d7mr12499354eji.543.1668481005200; Mon, 14 Nov 2022 18:56:45 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481005; cv=none; d=google.com; s=arc-20160816; b=tqM5WsXgG3DzCR+X/wY3EWxVxWqOIKmn8YEEI6nd7RYgDIhcEJzqRJJYoNNsGU2a2K QMWbYvXC51aH391CARtghbClZW5hkspeSGiE6t234zdhL+keA6anJOlmIYVDfWfMdUqO Uq80yTRoxdn2ZbITRrs9szC4Q9tMHTdbbubogtmlDFubm6eBERHzNpmIU8mRplndId+i mqpFUktoOkm8MqkmR0ywlxm+o0VyEq5X3EjTU/2OdcJgf4c5llbuMrpcjhre+FOYHrth jX5/dEVNhBez45Aa9/M4H4h+XZIliFPL2FRJIe67gaF4G5wEH/VRPrttSFJDiZIinraB /T4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=wRYDzS6yAt4cpvGVye2SW5vgcMntnZG/i/Ggtx20GY8=; b=gtJqHiy77ElVNHLRHy1n/Cdrxg9p+Y7WqQjcKb3A1E99HkGKN7wpvmA166OFu5I4Tl KHbuhG9uP66hCp4HfG93hTHk/4Mgnf+4101x8iWRfxGUGSIL1GjFhe0yAOccFvMtLGdw JUNe+203c4bUpdSfhdRstA+8I3vvZ+oF1tBNGS3Lrqkm0EUyecDYnfCMqb0+gwGUOoez +Ck2tbcQrb9SzmjrzdJRber0B2Z5cxYi038pesziXyGbsDVK9m+5NHLS3i5hvrSCVmXF ku4HT+9Huyk4kHpNCLwg2qcWfcD7RO9I7R7eabh47Q9sHxD/s92vRfafuxl3vHxyJE5E UGPg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=EdE8bFuG; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml index 939623867a646..3b92725bbc99b 100644 --- a/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml +++ b/Documentation/devicetree/bindings/usb/mediatek,mtk-xhci.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8188-xhci - mediatek,mt8192-xhci - mediatek,mt8195-xhci + - mediatek,mt8365-xhci - const: mediatek,mtk-xhci reg: From patchwork Tue Nov 15 02:54:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20137 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484512wru; Mon, 14 Nov 2022 18:56:36 -0800 (PST) X-Google-Smtp-Source: AA0mqf5NkHsa0VKTJWvDBPQN/V3MlVI9u7fXk8xIhx642PoGk4sEDJY7rdO1+FO0PEw4p+h4qfZy X-Received: by 2002:a17:906:eb59:b0:7ae:c1b2:d928 with SMTP id mc25-20020a170906eb5900b007aec1b2d928mr12125148ejb.296.1668480996039; Mon, 14 Nov 2022 18:56:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668480996; cv=none; d=google.com; s=arc-20160816; b=cN33Pf8WQEqAdB8g9O2A+n9KAuABBcrxuDhhZvW+7zH85djwyDZclseY2GTpLJ+KK4 KInL6XFEc9CmSVolYy5mdEG/cBlUrGBdN0vp7amu45+T9K/+NMmGAWc/dQH1ZO0MfyGA jVzTuAH3Uy+mw8ju90RvoknqgdpYVnHiua3mPVwVBU2FF6e4B4/7SxVTKZosDhayjqTI HicEQVNNiaxwIpHCfURHPW1Z4pkvXzys0Zg9jG3fPHkbwOmBSHVN0jj7w33IGM634BsP uEnzu1u9IahY8m/uV3/KQeap2wLk+zu/z/ADnViWG4OP6nXxeq1iZLrjxmq5GsiR2h23 QZ7A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=vMatkpXRBfYZcOpwK4gKTH0eFwLe1XO/MVtN1h01A6s=; b=E7eg621vg8QSNjrZ0dq/oj9J5MOFw22MY4/Q127cwVXbi44Mx4XJtrTGeGPOJMBxc1 mSG7FWF98Ywdebi4Fgpk7BgrHDSIp7bsXHNCZeLBgGw6++STcO+P3rbMpfv5/XcYpMf+ P7zkqI1BnQwyIQGGHm4o8bX94WMYgjj5cIJNNE7AvALLB5G4AWQ3OgKdkH3/YPJwpoWy qN8pMBltQIj3rm0IKj43tstwhr7Tkq3JbnNQkepGTMKZvbikHzx6C5ah+bmbQpM8SrFB V9FArFdZoxzmAoJN4mPAedCik+aWIMn1bnQPqutSQPcfnOIPCbc3RC1NzDYFzX4nWCEP vk4A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=pRx3zIId; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml index 6f8ecb4788eb8..36f9fce8f4795 100644 --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml @@ -35,6 +35,9 @@ properties: - mediatek,mt8192-mmc - mediatek,mt8195-mmc - const: mediatek,mt8183-mmc + - items: + - const: mediatek,mt8365-mmc + - const: mediatek,mt8183-mmc reg: minItems: 1 From patchwork Tue Nov 15 02:54:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20141 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484627wru; Mon, 14 Nov 2022 18:57:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf7N3IS5JRo3LBUilWFrjxPQoShDU1S0Zn9heZw4MvKMKAA/dU6ogsjM2xmTiTCMkJzmUsiL X-Received: by 2002:a17:906:4dd6:b0:7ad:a030:487e with SMTP id f22-20020a1709064dd600b007ada030487emr12644801ejw.508.1668481025436; Mon, 14 Nov 2022 18:57:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481025; cv=none; d=google.com; s=arc-20160816; b=pyUrC6uG6LWbWgHAsD5fKxJ0nJw6asD+vGu6d6pipGxjzC0fp1TMA/EZOzfzwXJRMc djZQFjuPIkziImhMLqR0SpUD8XJc/LtzcqZ1HlmHHY8mtjNYo8rP/j6Qf6VuTzpvZGje 4narZSDymHQjQyylnzn6WOLNefPgTIB0pJDcUvTqiKNR7+plVdVeWor5hrX7W6l3nxlX X+Keik7NFDWxcVlwBBBatDbKEfQKV0u1f5EC+0B7wsqiBNbPw+9FRFrQ4knVc0LaSKbf u18z9C/nydRjOzQJz9R+yCBEklVtdG+qPEDCTGfXlyAtCONIP4kdw7cUVksD70Rxc0YC YyMg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=5dC+/yReVVtnmp1EFnfhA5gyiPu04TshQ+QR3r1EqXE=; b=I8mDz21bXEIG4jdVeKhQ9grqaJQSaiPeEGhcjo/BHfFf+dd2rLSmpX9MG8w0LGBGlI yeJW9jD6WV090rZ9zvBm9rp2Pp+ubKAAWcBKShlbFz5qzVVp/Q5DCycb50tfFG+uT7Ze S9N5sVllAnEtLg/2qNYjeI0CkD5+BYFAjhO7jnSWoRok9t/u3IK8tvzU8727nt+Y5gZd E/Z9fhPyKa6XIIW61Soi6bDDlvmlTOvLRXYwBaFQsFWdyAtaWQCBDtwCbiendpxjcFvm 8NA+YJQVIzIqFQQFmvAaU2me8YMR/5o5iE1yWYFjKn70VDqWSBR7FqOY5k/+urXpwRAi 7z2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=fdYDr7Yw; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Fabien Parent --- Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml index 75e0a516e59a2..6893f2a6ea225 100644 --- a/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml +++ b/Documentation/devicetree/bindings/nvmem/mediatek,efuse.yaml @@ -34,6 +34,7 @@ properties: - mediatek,mt8192-efuse - mediatek,mt8195-efuse - mediatek,mt8516-efuse + - mediatek,mt8365-efuse - const: mediatek,efuse - const: mediatek,mt8173-efuse deprecated: true From patchwork Tue Nov 15 02:54:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20139 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484570wru; Mon, 14 Nov 2022 18:56:48 -0800 (PST) X-Google-Smtp-Source: AA0mqf6f63vVKJ3Ljw8gQiH3D8pOMtLvNt3w/GUpo2E2WuIan+b0WFifCofeouwdxLRZTYtWvch9 X-Received: by 2002:a17:906:68d8:b0:78d:e786:e322 with SMTP id y24-20020a17090668d800b0078de786e322mr11925362ejr.308.1668481007987; Mon, 14 Nov 2022 18:56:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481007; cv=none; d=google.com; s=arc-20160816; b=EGnWbAYLTFTPCItCkTp7TfNq1Kz4BGMdPD3uUv98YtoVfVB0tL8VzlqSsTSx3wSLvz kn2I1bgcY1AU+9PFD7xveCnJKd2ftjAY6Tsm23/cudSclCTbsm6DZAcwNFtiGh5lfCMZ 2mW9l5LfQARvnW7E3qNLUUkBWFMrR8AFQ26GX2FNecVmbj3PtsPX6/ooS1vt0dgC/mIh WrSBHZKg5N6xNQfFGgeLHR3XFFGgr0WdnSIrWkuz6rd/1cL4JRpQty+2F8OtcaZ0B2WY 1NEDzcWccx2mcym8VLltdu/S+yHeFsjsipPz9hVq81Ubr86P127bhdiatXwNKasV60eE Gn2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=K3i5y3oyIwsgiFHEGgey14XqgO98FOVbhLAM8VvS1C4=; b=Gw6oWfoFqPXkNlfoshVsypJ9aKhxTF6HbuEuYCfWydCEX9+DXby1QlCQb2kGFyq0cy YMsP5BFuhKRSy+KD8r3TsNtgXq3z3Y5eNRfNh13ur0FH46FgW6iWjY28z7yhn6eMabCp nlLjIGKOwqjayQyHxCxqPvriEJFgASa2EvolvigERhr7143awJ5J0gvF3X5qc1yio7RD c7u2K9ferwupCxsYfeCJ8OqS2GtEfgdyFFTt+m5+hrClWn45YVc5deljjSegrPd12aWB 0ZWat794sdfMBkPF9aQKIwzwPhhWd1a9Z/Sr0JBspdafAk8SdgxyKr0H9nHSPNqZkO0+ mowQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=XAXlj7HV; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer --- Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 8bbb6e94508b2..c1f40aca2d48c 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -20,6 +20,7 @@ Required properties: * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) * "mediatek,mt8516-timer" for MT8516 compatible timers (GPT) + * "mediatek,mt8365-timer" for MT8365 compatible timers (GPT) * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) For those SoCs that use SYST From patchwork Tue Nov 15 02:54:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20140 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484609wru; Mon, 14 Nov 2022 18:56:59 -0800 (PST) X-Google-Smtp-Source: AA0mqf46Lc9v2NhN1aHTObLD9zPOkwyqlCGwOw6G83RWoedeB6eYNkxk5h3CLSLqsdLqwzbR8YfV X-Received: by 2002:a17:906:5e4b:b0:782:9b27:94aa with SMTP id b11-20020a1709065e4b00b007829b2794aamr11738587eju.542.1668481019080; Mon, 14 Nov 2022 18:56:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481019; cv=none; d=google.com; s=arc-20160816; b=r1I0ngrVzn9Q/+1a9yAPjwgQDzyZv2j0pd0WOZ6WHVMU9xT67lZ0KfzghCZwkpKlbi wQoxEV55BVtajgMbzk12/lmVzJQCzAnGpjWmfHoOS8E/EcQtyzCFNwPedpCygjNB8+s2 wRgD1NVTQrYx/XKiQ3D13CwteS/+FAZ221hwQxVjLx2M3rdZHzGakwR8OX/vdaqwn4OS ce4JKyaYgWcvRAD+pm9aUR12GXIWaUKIXRdB+z4xt1Z8DF3cm/idttPF6dm/ngrytQ+L /X6iCed2OOWbL7MQ30TXL5GnKyR7I0Km0LNDoVQzT+yhBbaE09Zs2VJl70aE8L4JjeEp 1g5g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=DpYq70iArNS2pxebGHEfValI4udhqvfJfL86oolgszo=; b=BcsSWKCgdCZw3HqQTJ3+6atNBhi0FJW7/mrZ4UdyiRHR6wPrSe6v/DVeV9Hr694PNt VbXc6ZnsyEgXWI5o8RdWCMWZCTUunKtOP6rKETKVpL06jdEbswJudSVurWzHoO4v3wPf k5Ef3ywZHf9Nxy+zB1p9fedg/lIavTibt7bE955E+0qALlUETUVLUj9/9EKuDAFcFwAG oZ9eH4XMdHno7sp5eggUimiXWgjIfxUAXXG7/a36EA4Blp1fpjKs9CDc2s9XOhwbT9WK JvH1lYptAR+ZZNKyr9hkTfbTEL3syKFKtPiYx//Cz9mVUKPjdjSs8LFLEnuHoAZO2MoF lo+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=jZpzIPCL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer --- .../pinctrl/mediatek,mt8365-pinctrl.yaml | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml new file mode 100644 index 0000000000000..bddff8c2fd382 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8365 Pin Controller + +maintainers: + - Bernhard Rosenkränzer + +description: |+ + The MediaTek's MT8365 Pin controller is used to control SoC pins. + +properties: + compatible: + const: mediatek,mt8365-pinctrl + + reg: + minItems: 1 + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + interrupt-controller: true + + interrupts: + maxItems: 1 + + "#interrupt-cells": + const: 2 + +allOf: + - $ref: "pinctrl.yaml#" + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + +additionalProperties: false + +examples: + - | + soc { + #address-cells = <2>; + #size-cells = <2>; + + pio: pinctrl@1000b000 { + compatible = "mediatek,mt8365-pinctrl"; + reg = <0 0x1000b000 0 0x1000>; + mediatek,pctl-regmap = <&syscfg_pctl>; + pins-are-numbered; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = ; + }; + }; From patchwork Tue Nov 15 02:54:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20142 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484714wru; Mon, 14 Nov 2022 18:57:25 -0800 (PST) X-Google-Smtp-Source: AA0mqf7NpmXNvKSTbRGF48K9Kr2PESgkgbM3kRAjSdRPrPaqJliMyHgJmWplmmRk1Rf73jh6PT0A X-Received: by 2002:a17:907:1308:b0:7af:bc9:5e8d with SMTP id vj8-20020a170907130800b007af0bc95e8dmr3768972ejb.3.1668481045203; Mon, 14 Nov 2022 18:57:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481045; cv=none; d=google.com; s=arc-20160816; b=STYcITno3gq0PhEU0EGA6CHxOCjoHSweUsKX1c+qI8KAZHBp1Dj31DN8rvxOCiR+sl f+b+BZrJi1LTvuLXJPZBd0eLHBI9UY4Krplsmz9EyfNTo+wsWhjNbMIk2Dam6XirLxKc FEGwmH2idWtgkMRADT03jKupW5ZTD3piKN26ct6iwDlsqqeI3xykY/NdllXjt+crEJTs ihIn1VYNjJS1Vsglcwgr0B3XqHlHZO4k8GAoK+MxaolxarE5Fhjknhrla1VuxXkU3z2B Heq6Mz4FvoB4yZpAbZE72Pn5NLfDJT6iuxB4JJkaO43VfoA+CdENORVCNj6/X3S52Mq9 OAxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Lfd5vFsn4ORTC9eQFrAgBokxgVjsUt5YFyR8S2MDEt4=; b=MtjYTl7evQLJCWo3XDP4kTKTP6nC7VZgm/jLidRBcAUeCNYVF8dg8xkxKpGghvmev0 ac4/sfJzXf5q9pAujfDCfsLzcktITWoeBVYeGK7tEtqbYT4yAKb4EjZw6UYiNNlCPUv+ 7ySjbIWo+hHwALcDyiKTkN3CfLlIpPXw+UVGkOvCMP2kkKO9ScECCKxn/KzgI9X7ueeL OoIac1KcA/kIYS66CGyzPztjsZdvWDP3xrJ0JyLE2nRpGzpI1MFDBUyawz9vFqtw2QPD JxBpGvh1AI7ygxiddHBn7GoRqgr7WJk2TAk/k8CkReqlwltkkPT1uqTVUTZS+9Y7RVLs 3LoQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=QKdeWglr; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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"mediatek,mt8188-pwrap", "mediatek,mt8195-pwrap" for MT8188 SoCs "mediatek,mt8195-pwrap" for MT8195 SoCs "mediatek,mt8516-pwrap" for MT8516 SoCs + "mediatek,mt8365-pwrap" for MT8365 SoCs - interrupts: IRQ for pwrap in SOC - reg-names: "pwrap" is required; "pwrap-bridge" is optional. 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Signed-off-by: Bernhard Rosenkränzer --- .../devicetree/bindings/interrupt-controller/mediatek,sysirq.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt index 84ced3f4179b9..3ffc60184e445 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt +++ b/Documentation/devicetree/bindings/interrupt-controller/mediatek,sysirq.txt @@ -25,6 +25,7 @@ Required properties: "mediatek,mt6577-sysirq": for MT6577 "mediatek,mt2712-sysirq", "mediatek,mt6577-sysirq": for MT2712 "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq": for MT2701 + "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq": for MT8365 - interrupt-controller : Identifies the node as an interrupt controller - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt. - reg: Physical base address of the intpol registers and length of memory From patchwork Tue Nov 15 02:54:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20151 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2485099wru; Mon, 14 Nov 2022 18:59:00 -0800 (PST) X-Google-Smtp-Source: AA0mqf41LLSMRTyfe/5y0lU5p1xc3nzlJEXXsp3z1d+pjxvj+Gdtzz+EotcuMFlJixpF9jcd6/aK X-Received: by 2002:a17:907:2b08:b0:78d:424c:fa2b with SMTP id gc8-20020a1709072b0800b0078d424cfa2bmr12377036ejc.546.1668481140203; Mon, 14 Nov 2022 18:59:00 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481140; cv=none; d=google.com; s=arc-20160816; b=i09DI7MntS7XGaAzIAp1wsxoUuE6KT22CkTS0w5IPHu7yCYLbmQB2R9Ob2sLP1mbrk 4OIe5Tpy43MPSiDwFH+tU3WJt/iQj8msgQn6XD4d1a8a22mtE6KWxCXeUo68o3m0e68J M00qmFcG7oi205yDlJwPDdVA/YG+vXOSFxevfr7yA18KrqiRIzrJSt8Nk6S52wOExCFA FmIZJl6g1x8VLHAzYZqkikrENSvKWVIsT6wrrjgGU3VEiuqEjrq5OAsUk6v+hGDx36n/ Hj9rkHhlRoR4CV3xI06/liudUnCfVzH42EAdwKpcqwUzZjqLFLgd53UIQHpl/m5goyMZ ZSOA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=tGFeLYCtw0pQ4Vg1WxSYyEWBzkxCWkgNacW8i2OpJuo=; b=cIhY/VqOyzPUEV9oVag02o88MhEuf5hYedejmcfUnspYrBh9SCfen3B1Cks4thy9Xd ytrNm7P20Dx0tnQ8jnORtAE8aT5z72458UWFcBO54jkBX1ldiO1gBmoqcA1r/ODH/7Fk TRM6lc2wroYHsjIv/D0+FbYsmR3LivzjcOrw6DGuH78mkZvGmOSHqWUnTZlsm9miqu6V E0RxU+VmewecJsmkwswLhWgLlZ08hZ7wy8wInlvfVIPtupc39A+MXaEiwDJIz/BMbC2k bnvGXZ8gZVZPIVTIDiofLVJW/7dWAWdPrgmgbZiYhw744p7DdRbc764gwKKaxW+mCf74 Q6RQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b=eFCGkMLv; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer --- Documentation/devicetree/bindings/thermal/mediatek-thermal.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt index 5c7e7bdd029ab..d1b30733dfce3 100644 --- a/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt +++ b/Documentation/devicetree/bindings/thermal/mediatek-thermal.txt @@ -15,6 +15,7 @@ Required properties: - "mediatek,mt7622-thermal" : For MT7622 SoC - "mediatek,mt8183-thermal" : For MT8183 family of SoCs - "mediatek,mt8516-thermal", "mediatek,mt2701-thermal : For MT8516 family of SoCs + - "mediatek,mt8365-thermal" : for MT8365 family of SoCs - reg: Address range of the thermal controller - interrupts: IRQ for the thermal controller - clocks, clock-names: Clocks needed for the thermal controller. required From patchwork Tue Nov 15 02:54:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Bernhard_Rosenkr=C3=A4nzer?= X-Patchwork-Id: 20143 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2484795wru; Mon, 14 Nov 2022 18:57:51 -0800 (PST) X-Google-Smtp-Source: AA0mqf4Sy8X8UnF1T5VSX+nR8TAUPsPkt/vlPrg7tds+cYk1Cl8ALHfYIayd8kZDVpLKVjZlcYzW X-Received: by 2002:a05:6402:1241:b0:461:e3e1:bc3b with SMTP id l1-20020a056402124100b00461e3e1bc3bmr13464097edw.145.1668481071042; Mon, 14 Nov 2022 18:57:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668481071; cv=none; d=google.com; s=arc-20160816; b=vHOHROh2dkhg2kFZAInLSuNNxNIv61ZwqYRQgu4YlcXPO8x4iLkR/hEYUw/732CXu6 mKbKftLT0DviokgDOpue5/1FhYM3O/SDbccAg33F1vojK/eoRerg2NiR55m3RaNM6/7I XrTC/ddNNaTiqnKFEmn6POBPl5DfO11v121N28EKiGPf+lNO8UCFZoIMCBkxmyNWVsHB FZph3+amcpOikmeJAQ+GQ+FfguIR2mvM8Vum9AgTWqCxw2mg/CQMb9/KzSqfNh9cBe1d CvdBudD+duy8p0n2ZTKAF9WXy7yDA0nZyDeYEUu119UoOfxfZceUTkhKlzBLPlsI9HM4 z4sw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=8QyPVEosZOT9SRw8683CVFBluZOEj+iHFopqFxbf8ZA=; b=oOMBOHPVHQBAy6DISDwtCS33nmJAHJY9mBc98VbjK6Xt6qtHtuZ2NBL1o9fUTa65bx rWbied+Jc6haw/gDwslIReruhonUa2D/AwisfIYZKXXjlOQyULySZJbRQh4c8i2yH8On E3zJiCD/1ZGNxkSiJjETxRajBw2JdN/wjWzEOn/OXOkoG1NwSZPX0E7edGTO2aTzyTk0 4/9//ovNxUpZNhEbfRxPGwbilVysPiBd84RCU9JWGYs0k3iEPgVWehA+z2kCUyqlF8Te r+MPCMmo6OCFyv5aXmkCFuHHC06b/aYdxN+xAItQd6Koli8mail+h8kGS2m9IQ5NVOZa Zm5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@baylibre-com.20210112.gappssmtp.com header.s=20210112 header.b="dFDH/NDC"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: from out1.vger.email (out1.vger.email. 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Signed-off-by: Bernhard Rosenkränzer --- Documentation/devicetree/bindings/arm/mediatek.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index d76ce4c3819db..6781fcdb9fe69 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -246,6 +246,10 @@ properties: - enum: - mediatek,mt8516-pumpkin - const: mediatek,mt8516 + - items: + - enum: + - mediatek,mt8365-evk + - const: mediatek, mt8365 additionalProperties: true