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[8.43.85.97]) by mx.google.com with ESMTPS id o10-20020a05622a008a00b0042a286a933asi3526919qtw.183.2024.01.27.05.12.34 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 27 Jan 2024 05:12:34 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) client-ip=8.43.85.97; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CB9033858C56 for ; Sat, 27 Jan 2024 13:12:33 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 46C6A3858D28 for ; Sat, 27 Jan 2024 13:12:19 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 46C6A3858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 46C6A3858D28 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706361145; cv=none; b=F6qmU29fxMfmUDQl6Pq3W9PLfAO3PCDuo19KE3sOhAqWQgCo0b1uI0WtSgeEefRovacAEvfpD1FE1wuEYqmXqSoi6d5MaKnobnFwf8ujyo+KzhCgiMXOQyKo1HEN1vupOffJScLLhWLzeY02UykI8/nqzWQp2qK0kE9B1z5zrv4= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706361145; c=relaxed/simple; bh=FoEhFR6BnddSmVnrq8OW60AQHPCFyD4XPCMrp59Nbe8=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=FtGBwOWcG5HBYfgELnumg3hBPFj/pePRapF2E4FqIPadXtt7UCAfdthKbXzXP+Xob8Hr9I+OIPqZNG6CkNfhs02E4ngQ6oviFXwguIgj799sFDGMWDtlfnpZToWB+aDpIew01YE330e6/oLkPEKBtDexxWtWQv5MZjk7qm/jkFY= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8Ax++guAbVl6AUHAA--.3589S3; Sat, 27 Jan 2024 21:12:14 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxRMwtAbVlVDAfAA--.55959S4; Sat, 27 Jan 2024 21:12:13 +0800 (CST) From: Lulu Cai To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, mengqinggang@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn, Lulu Cai Subject: [PATCH 1/2] LoongArch: Fix incorrect type transition under extreme cmodel Date: Sat, 27 Jan 2024 21:12:10 +0800 Message-Id: <20240127131211.795952-1-cailulu@loongson.cn> X-Mailer: git-send-email 2.39.3 MIME-Version: 1.0 X-CM-TRANSID: AQAAf8AxRMwtAbVlVDAfAA--.55959S4 X-CM-SenderInfo: xfdlz3tox6z05rqj20fqof0/1tbiAQAJB2WzbWEGcwAJsp X-Coremail-Antispam: 1Uk129KBj93XoW3Jw1kCFyfGr4UCw4fAr4xAFc_yoWfXrWxpr y3Zw43tr48CF17uryqqa45ZF4aqFWxWrWIqFyaqrZYkF4kXryrXFZxKF1kZayjg3WvgrsI vry0934UX3W8A3XCm3ZEXasCq-sJn29KB7ZKAUJUUUU5529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUkYb4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Jr0_Gr1l84ACjcxK6I8E87Iv67AKxVWxJVW8Jr1l84ACjcxK6I8E87Iv6xkF7I0E14v2 6r4j6r4UJwAS0I0E0xvYzxvE52x082IY62kv0487Mc804VCY07AIYIkI8VC2zVCFFI0UMc 02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAF wI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JMxAIw28IcxkI7V AKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCj r7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6x IIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAI w20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_Gr0_Cr1lIxAIcVC2z280aVCY1x 0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7IU8zwZ7UUUUU== X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789249353872491068 X-GMAIL-MSGID: 1789249353872491068 This patch mainly fixes the bug of tls type transition when -mcmodel=extreme. Because the first two instructions of normal and extreme use the same relocation, this will cause an incorrect type transition when -mcmodel=extreme, similar to: pcalau12i t0, %ie_pc_hi20(x) li.d t1, %ie_pc_lo12(x) lu32i.d t1, %ie64_pc_lo20(x) lu52i.d t1, t1, %ie64_pc_hi12(x) ldx.d t0, t0, t1 Transition to lu12i.w t0, %le_hi20(x) ori t1, t1, %le_lo12(x) lu32i.d t1, %ie64_pc_lo20(x) lu52i.d t1, t1, %ie64_pc_hi12(x) ldx.d t0, t0, t1 In order to avoid this situation, we only do type transition for normal, and each relocation that can be type transition will be accompanied by an R_LARCH_RELAX, and will not issue R_LARCH_RELAX for TLS instruction sequences of other code models. --- bfd/elfnn-loongarch.c | 67 +++++++++++++++++++++++---------------- gas/config/tc-loongarch.c | 19 +++++++++-- 2 files changed, 56 insertions(+), 30 deletions(-) diff --git a/bfd/elfnn-loongarch.c b/bfd/elfnn-loongarch.c index 1895699af06..d51841e7973 100644 --- a/bfd/elfnn-loongarch.c +++ b/bfd/elfnn-loongarch.c @@ -145,14 +145,12 @@ struct loongarch_elf_link_hash_table #define elf_backend_rela_normal 1 #define elf_backend_default_execstack 0 -#define IS_LOONGARCH_TLS_DESC_RELOC(R_TYPE) \ - ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ - || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ - || (R_TYPE) == R_LARCH_TLS_DESC_LD \ - || (R_TYPE) == R_LARCH_TLS_DESC_CALL) - -#define IS_LOONGARCH_TLS_IE_RELOC(R_TYPE) \ - ((R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ +#define IS_LOONGARCH_TLS_TRANS_RELOC(R_TYPE) \ + ((R_TYPE) == R_LARCH_TLS_DESC_PC_HI20 \ + || (R_TYPE) == R_LARCH_TLS_DESC_PC_LO12 \ + || (R_TYPE) == R_LARCH_TLS_DESC_LD \ + || (R_TYPE) == R_LARCH_TLS_DESC_CALL \ + || (R_TYPE) == R_LARCH_TLS_IE_PC_HI20 \ || (R_TYPE) == R_LARCH_TLS_IE_PC_LO12) /* Generate a PLT header. */ @@ -642,15 +640,20 @@ loongarch_reloc_got_type (unsigned int r_type) /* Return true if tls type transition can be performed. */ static bool -loongarch_can_relax_tls (struct bfd_link_info *info, unsigned int r_type, - struct elf_link_hash_entry *h, bfd *input_bfd, - unsigned long r_symndx) +loongarch_can_trans_tls (bfd *input_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + const Elf_Internal_Rela *rel, + unsigned int r_type) { char symbol_tls_type; unsigned int reloc_got_type; + unsigned int r_symndx = ELFNN_R_SYM (rel->r_info); - if (! (IS_LOONGARCH_TLS_DESC_RELOC (r_type) - || IS_LOONGARCH_TLS_IE_RELOC (r_type))) + /* Only TLS DESC/IE in normal code mode will perform type + transition. */ + if (! (IS_LOONGARCH_TLS_TRANS_RELOC (r_type) + && ELFNN_R_TYPE (rel[1].r_info) == R_LARCH_RELAX)) return false; symbol_tls_type = _bfd_loongarch_elf_tls_type (input_bfd, h, r_symndx); @@ -707,11 +710,13 @@ loongarch_tls_transition_without_check (struct bfd_link_info *info, } static unsigned int -loongarch_tls_transition (struct bfd_link_info *info, unsigned int r_type, - struct elf_link_hash_entry *h, bfd *input_bfd, - unsigned long r_symndx) +loongarch_tls_transition (bfd *input_bfd, + struct bfd_link_info *info, + struct elf_link_hash_entry *h, + const Elf_Internal_Rela *rel, + unsigned int r_type) { - if (! loongarch_can_relax_tls (info, r_type, h, input_bfd,r_symndx)) + if (! loongarch_can_trans_tls (input_bfd, info, h, rel, r_type)) return r_type; return loongarch_tls_transition_without_check (info, r_type, h); @@ -818,7 +823,10 @@ loongarch_elf_check_relocs (bfd *abfd, struct bfd_link_info *info, int need_dynreloc = 0; int only_need_pcrel = 0; - r_type = loongarch_tls_transition (info, r_type, h, abfd, r_symndx); + /* Type transitions are only possible with relocations accompanied + by R_LARCH_RELAX. */ + if (rel + 1 != relocs + sec->reloc_count) + r_type = loongarch_tls_transition (abfd, info, h, rel, r_type); switch (r_type) { case R_LARCH_GOT_PC_HI20: @@ -2536,7 +2544,7 @@ loongarch_reloc_is_fatal (struct bfd_link_info *info, /* Transition instruction sequence to relax instruction sequence. */ static bool -loongarch_tls_relax (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, +loongarch_tls_perform_trans (bfd *abfd, asection *sec, Elf_Internal_Rela *rel, int r_type, struct elf_link_hash_entry *h, struct bfd_link_info *info) { @@ -2657,7 +2665,7 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, const char *name; bfd_reloc_status_type r = bfd_reloc_ok; bool is_ie, is_desc, is_undefweak, unresolved_reloc, defined_local; - unsigned int relaxed_r_type; + unsigned int trans_r_type = r_type; bool resolved_local, resolved_dynly, resolved_to_const; char tls_type; bfd_vma relocation, off, ie_off, desc_off; @@ -2789,14 +2797,17 @@ loongarch_elf_relocate_section (bfd *output_bfd, struct bfd_link_info *info, BFD_ASSERT (!resolved_local || defined_local); - relaxed_r_type = loongarch_tls_transition (info, r_type, h, input_bfd, r_symndx); - if (relaxed_r_type != r_type) + if (rel + 1 != relend) + trans_r_type = loongarch_tls_transition (input_bfd, info, h, + rel, r_type); + if (trans_r_type != r_type) { - howto = loongarch_elf_rtype_to_howto (input_bfd, relaxed_r_type); + howto = loongarch_elf_rtype_to_howto (input_bfd, trans_r_type); BFD_ASSERT (howto != NULL); - if (loongarch_tls_relax (input_bfd, input_section, rel, r_type, h, info)) - r_type = relaxed_r_type; + if (loongarch_tls_perform_trans (input_bfd, input_section, + rel, r_type, h, info)) + r_type = trans_r_type; } is_desc = false; @@ -4551,7 +4562,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, || R_LARCH_TLS_GD_PC_HI20 == r_type || R_LARCH_TLS_DESC_PC_HI20 == r_type) { - if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) + if (i + 1 != sec->reloc_count + && loongarch_can_trans_tls (abfd, info, h, rel, r_type)) continue; else { @@ -4595,7 +4607,8 @@ loongarch_elf_relax_section (bfd *abfd, asection *sec, || R_LARCH_TLS_GD_PC_HI20 == r_type || R_LARCH_TLS_DESC_PC_HI20 == r_type) { - if (loongarch_can_relax_tls (info, r_type, h, abfd, r_symndx)) + if (i + 1 != sec->reloc_count + && loongarch_can_trans_tls (abfd, info, h, rel, r_type)) continue; else { diff --git a/gas/config/tc-loongarch.c b/gas/config/tc-loongarch.c index e0aff36bbbb..af4426bff94 100644 --- a/gas/config/tc-loongarch.c +++ b/gas/config/tc-loongarch.c @@ -724,8 +724,12 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, } /* Only one register macros (used in normal code model) - emit R_LARCH_RELAX. */ + emit R_LARCH_RELAX. + LARCH_opts.ase_labs and LARCH_opts.ase_gabs are used + to generate the code model of absolute addresses, and + we do not relax this code model. */ if (LARCH_opts.relax && (ip->expand_from_macro & 1) + && ! (LARCH_opts.ase_labs | LARCH_opts.ase_gabs) && (BFD_RELOC_LARCH_PCALA_HI20 == reloc_type || BFD_RELOC_LARCH_PCALA_LO12 == reloc_type || BFD_RELOC_LARCH_GOT_PC_HI20 == reloc_type @@ -733,7 +737,11 @@ loongarch_args_parser_can_match_arg_helper (char esc_ch1, char esc_ch2, || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_type || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_type - || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type)) + || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_type + || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_type + || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_type + || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_type + || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_type)) { ip->reloc_info[ip->reloc_num].type = BFD_RELOC_LARCH_RELAX; ip->reloc_info[ip->reloc_num].value = const_0; @@ -1088,7 +1096,12 @@ append_fixp_and_insn (struct loongarch_cl_insn *ip) || BFD_RELOC_LARCH_TLS_LE_ADD_R == reloc_info[0].type || BFD_RELOC_LARCH_TLS_LD_PC_HI20 == reloc_info[0].type || BFD_RELOC_LARCH_TLS_GD_PC_HI20 == reloc_info[0].type - || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type)) + || BFD_RELOC_LARCH_TLS_DESC_PC_HI20 == reloc_info[0].type + || BFD_RELOC_LARCH_TLS_DESC_PC_LO12 == reloc_info[0].type + || BFD_RELOC_LARCH_TLS_DESC_LD == reloc_info[0].type + || BFD_RELOC_LARCH_TLS_DESC_CALL == reloc_info[0].type + || BFD_RELOC_LARCH_TLS_IE_PC_HI20 == reloc_info[0].type + || BFD_RELOC_LARCH_TLS_IE_PC_LO12 == reloc_info[0].type)) { frag_wane (frag_now); frag_new (0); From patchwork Sat Jan 27 13:12:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cai X-Patchwork-Id: 193004 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2395:b0:106:343:edcb with SMTP id gw21csp479186dyb; Sat, 27 Jan 2024 05:12:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IHdqh6YZOkAOF2SzjJv7j26KkAiMCYkO3wjtGJjUJ+iCi/WJHfP5cBWH4a1N0I0WIuyQhD4 X-Received: by 2002:ad4:4246:0:b0:68c:4301:98fd with SMTP id l6-20020ad44246000000b0068c430198fdmr185909qvq.46.1706361160665; Sat, 27 Jan 2024 05:12:40 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706361160; cv=pass; d=google.com; s=arc-20160816; b=VZodlBEd8wQKXxDzxa87dW8rU6PBU7MhozVxEe226enHOgP25rKQkDsDi+TFJN2NYJ z0MCyXhNDrTW532dIaLDoAOB6JR1ZXFsagXA446pc0Y+hm9C8mpdhfj385hZVlE/weXq Wtz2CqZdw5SvFU3wxqVgQd6FSJdwHx/aL7c6Ap+WR0dd6EWLRuxorQYiaT6hi2neaLWO XJhgLXVXeu0o4GFFieraHCuH0rbFbr1HZwHs1Mjt2YaJvu+IY8ykAWVDEPasw4z95tCO MVDfA4sVZOql6EqJbrES8r4lPjJYfBMxUZtRLcAdCqUgS21SotVvUzcdvluYEQlvMCEQ T86A== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=/rTw8dpOGBbXg8FyAFkHNy/xex5hkZr3SQk/6dXs7Ok=; fh=FvlVQEmCpm5H8oBXQswexzCupeeQXnbssobXN+3R2Wg=; b=zsrdZttoQa0HggFYy3HZispnNoU1qMEGFs4ZoZ2js0KrOG4bNZbKRM8tamuuHLGKT1 YKUzK0erfyFl58ZN+yH7uPbjD4NbUAoVfD9u3vMcEU7b1kU8M7FSO9dH08Q6AZNPCfcJ gQC7nXNqVh5zzGrjBH7BsMEJVarEkrxCVqsfxmjv2LXeplsayQG46iQDQM+Rre+MejHV XDXJku1Tv/ABKKhnHQd/psMpuFKv1NJNLvdv33w2bqGhQdEzje8q1YCuD5WS1yUYiEgH RyjtBR3rRB+RrXA/y+qoKy9rwGBgogeFspbKNyzhTQsIJ6Mt2wnNyllesFC0L4ZSdyL9 bd7Q== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 8.43.85.97 as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (server2.sourceware.org. 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b=Uc76LaHlslcwKICJjonBkfMG1VzCJbGKhi46RjCuDwRsDsfAo7nwONMtVNgTPfoJ9Cc6MFJ790arnY+f3559L9/YRPqj/dxpZzeLkbxvNhl3KF3M0gle4fygaO1/n9KQDLJx0AiP1kSkI30LfIjE28jvqmRjUr3q4T3RjFzSRvQ= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from loongson.cn (unknown [10.2.6.5]) by gateway (Coremail) with SMTP id _____8Axeeg2AbVl_QUHAA--.3562S3; Sat, 27 Jan 2024 21:12:22 +0800 (CST) Received: from 5.5.5 (unknown [10.2.6.5]) by localhost.localdomain (Coremail) with SMTP id AQAAf8AxRMwtAbVlVDAfAA--.55959S5; Sat, 27 Jan 2024 21:12:21 +0800 (CST) From: Lulu Cai To: binutils@sourceware.org Cc: xuchenghua@loongson.cn, chenglulu@loongson.cn, liuzhensong@loongson.cn, mengqinggang@loongson.cn, xry111@xry111.site, i.swmail@xen0n.name, maskray@google.com, luweining@loongson.cn, wanglei@loongson.cn, hejinyang@loongson.cn, Lulu Cai Subject: [PATCH 2/2] LoongArch: update test cases about TLS Date: Sat, 27 Jan 2024 21:12:11 +0800 Message-Id: <20240127131211.795952-2-cailulu@loongson.cn> X-Mailer: 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1789249360045178814 X-GMAIL-MSGID: 1789249360045178814 --- gas/testsuite/gas/loongarch/macro_op.d | 2 ++ gas/testsuite/gas/loongarch/macro_op_32.d | 2 ++ .../gas/loongarch/macro_op_extreme_abs.d | 2 -- gas/testsuite/gas/loongarch/tlsdesc_32.d | 2 ++ gas/testsuite/gas/loongarch/tlsdesc_32.s | 2 +- gas/testsuite/gas/loongarch/tlsdesc_64.d | 2 ++ gas/testsuite/gas/loongarch/tlsdesc_64.s | 2 +- ld/testsuite/ld-loongarch-elf/desc-ie.d | 29 ++++++++++++++----- ld/testsuite/ld-loongarch-elf/desc-ie.s | 11 ++++--- ld/testsuite/ld-loongarch-elf/desc-le.d | 19 ++++++++---- ld/testsuite/ld-loongarch-elf/desc-le.s | 8 ++--- ld/testsuite/ld-loongarch-elf/ie-le.d | 13 ++++++--- ld/testsuite/ld-loongarch-elf/ie-le.s | 7 +++-- ld/testsuite/ld-loongarch-elf/macro_op.d | 2 ++ ld/testsuite/ld-loongarch-elf/macro_op_32.d | 2 ++ 15 files changed, 70 insertions(+), 35 deletions(-) diff --git a/gas/testsuite/gas/loongarch/macro_op.d b/gas/testsuite/gas/loongarch/macro_op.d index 47f8f45c663..9d696437a28 100644 --- a/gas/testsuite/gas/loongarch/macro_op.d +++ b/gas/testsuite/gas/loongarch/macro_op.d @@ -57,8 +57,10 @@ Disassembly of section .text: 4c: R_LARCH_TLS_LE_LO12 TLS1 50: 1a000004 pcalau12i \$a0, 0 50: R_LARCH_TLS_IE_PC_HI20 TLS1 + 50: R_LARCH_RELAX \*ABS\* 54: 28c00084 ld.d \$a0, \$a0, 0 54: R_LARCH_TLS_IE_PC_LO12 TLS1 + 54: R_LARCH_RELAX \*ABS\* 58: 1a000004 pcalau12i \$a0, 0 58: R_LARCH_TLS_LD_PC_HI20 TLS1 58: R_LARCH_RELAX \*ABS\* diff --git a/gas/testsuite/gas/loongarch/macro_op_32.d b/gas/testsuite/gas/loongarch/macro_op_32.d index a7349aa8dc0..f8aaacda345 100644 --- a/gas/testsuite/gas/loongarch/macro_op_32.d +++ b/gas/testsuite/gas/loongarch/macro_op_32.d @@ -53,8 +53,10 @@ Disassembly of section .text: 44: R_LARCH_TLS_LE_LO12 TLS1 48: 1a000004 pcalau12i \$a0, 0 48: R_LARCH_TLS_IE_PC_HI20 TLS1 + 48: R_LARCH_RELAX \*ABS\* 4c: 28800084 ld.w \$a0, \$a0, 0 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 + 4c: R_LARCH_RELAX \*ABS\* 50: 1a000004 pcalau12i \$a0, 0 50: R_LARCH_TLS_LD_PC_HI20 TLS1 50: R_LARCH_RELAX \*ABS\* diff --git a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d index 5c823ba0302..6a81e82e93e 100644 --- a/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d +++ b/gas/testsuite/gas/loongarch/macro_op_extreme_abs.d @@ -28,10 +28,8 @@ Disassembly of section .text: 1c: R_LARCH_ABS64_HI12 .L1 20: 1a000004 pcalau12i \$a0, 0 20: R_LARCH_PCALA_HI20 .L1 - 20: R_LARCH_RELAX \*ABS\* 24: 02c00084 addi.d \$a0, \$a0, 0 24: R_LARCH_PCALA_LO12 .L1 - 24: R_LARCH_RELAX \*ABS\* 28: 14000004 lu12i.w \$a0, 0 28: R_LARCH_GOT_HI20 .L1 2c: 03800084 ori \$a0, \$a0, 0x0 diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.d b/gas/testsuite/gas/loongarch/tlsdesc_32.d index eddcc5ed0e8..6c9558d7454 100644 --- a/gas/testsuite/gas/loongarch/tlsdesc_32.d +++ b/gas/testsuite/gas/loongarch/tlsdesc_32.d @@ -23,5 +23,7 @@ Disassembly of section .text: 14: R_LARCH_RELAX \*ABS\* 18: 28800081 ld.w \$ra, \$a0, 0 18: R_LARCH_TLS_DESC_LD var + 18: R_LARCH_RELAX \*ABS\* 1c: 4c000021 jirl \$ra, \$ra, 0 1c: R_LARCH_TLS_DESC_CALL var + 1c: R_LARCH_RELAX \*ABS\* diff --git a/gas/testsuite/gas/loongarch/tlsdesc_32.s b/gas/testsuite/gas/loongarch/tlsdesc_32.s index 2a139c041b1..2180146a41d 100644 --- a/gas/testsuite/gas/loongarch/tlsdesc_32.s +++ b/gas/testsuite/gas/loongarch/tlsdesc_32.s @@ -8,5 +8,5 @@ # R_LARCH_TLS_DESC_CALL var jirl $ra,$ra,%desc_call(var) - # test macro, pcalau12i + addi.w => pcaddi + # with R_LARCH_RELAX la.tls.desc $a0,var diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.d b/gas/testsuite/gas/loongarch/tlsdesc_64.d index 2a2829c9b44..8fc9e883a4a 100644 --- a/gas/testsuite/gas/loongarch/tlsdesc_64.d +++ b/gas/testsuite/gas/loongarch/tlsdesc_64.d @@ -24,5 +24,7 @@ Disassembly of section .text: 14: R_LARCH_RELAX \*ABS\* 18: 28c00081 ld.d \$ra, \$a0, 0 18: R_LARCH_TLS_DESC_LD var + 18: R_LARCH_RELAX \*ABS\* 1c: 4c000021 jirl \$ra, \$ra, 0 1c: R_LARCH_TLS_DESC_CALL var + 1c: R_LARCH_RELAX \*ABS\* diff --git a/gas/testsuite/gas/loongarch/tlsdesc_64.s b/gas/testsuite/gas/loongarch/tlsdesc_64.s index 9850940ef93..d63b17261db 100644 --- a/gas/testsuite/gas/loongarch/tlsdesc_64.s +++ b/gas/testsuite/gas/loongarch/tlsdesc_64.s @@ -8,5 +8,5 @@ # R_LARCH_TLS_DESC_CALL var jirl $ra,$ra,%desc_call(var) - # test macro, pcalau12i + addi.d => pcaddi + # with R_LARCH_RELAX la.tls.desc $a0,var diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.d b/ld/testsuite/ld-loongarch-elf/desc-ie.d index 32e350507db..8b184a6da38 100644 --- a/ld/testsuite/ld-loongarch-elf/desc-ie.d +++ b/ld/testsuite/ld-loongarch-elf/desc-ie.d @@ -1,16 +1,29 @@ #as: -#ld: -shared -z norelro -e 0x0 --hash-style=both +#ld: -shared -z norelro -e0 --hash-style=both #objdump: -dr #skip: loongarch32-*-* .*: file format .* + Disassembly of section .text: -0+230 : - 230: 1a000084 pcalau12i \$a0, 4 - 234: 28cd6084 ld.d \$a0, \$a0, 856 - 238: 03400000 nop.* - 23c: 03400000 nop.* - 240: 1a000084 pcalau12i \$a0, 4 - 244: 28cd6081 ld.d \$ra, \$a0, 856 +[0-9a-f]+ : + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 28ce2084 ld.d \$a0, \$a0, .* + +[0-9a-f]+: 03400000 nop + +[0-9a-f]+: 03400000 nop + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 28ce2084 ld.d \$a0, \$a0, .* + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 02ce2005 li.d \$a1, .* + +[0-9a-f]+: 16000005 lu32i.d \$a1, 0 + +[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .* + +[0-9a-f]+: 00109484 add.d \$a0, \$a0, \$a1 + +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 + +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 02ce2005 li.d \$a1, .* + +[0-9a-f]+: 16000005 lu32i.d \$a1, .* + +[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .* + +[0-9a-f]+: 380c1484 ldx.d \$a0, \$a0, \$a1 diff --git a/ld/testsuite/ld-loongarch-elf/desc-ie.s b/ld/testsuite/ld-loongarch-elf/desc-ie.s index 7f5772bcf23..e85a16d5fcb 100644 --- a/ld/testsuite/ld-loongarch-elf/desc-ie.s +++ b/ld/testsuite/ld-loongarch-elf/desc-ie.s @@ -9,10 +9,9 @@ fn1: # Use DESC and IE to access the same symbol, # DESC will relax to IE. - pcalau12i $a0,%desc_pc_hi20(var) - addi.d $a0,$a0,%desc_pc_lo12(var) - ld.d $ra,$a0,%desc_ld(var) - jirl $ra,$ra,%desc_call(var) + la.tls.desc $a0,var + la.tls.ie $a0,var - pcalau12i $a0,%ie_pc_hi20(var) - ld.d $ra,$a0,%ie_pc_lo12(var) + # extreme cmodel do not do transition. + la.tls.desc $a0,$a1,var + la.tls.ie $a0,$a1,var diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.d b/ld/testsuite/ld-loongarch-elf/desc-le.d index b4ca9f82eb3..688701f7fee 100644 --- a/ld/testsuite/ld-loongarch-elf/desc-le.d +++ b/ld/testsuite/ld-loongarch-elf/desc-le.d @@ -1,5 +1,5 @@ #as: -#ld: -z norelro -e 0x0 +#ld: -z norelro -e0 #objdump: -dr #skip: loongarch32-*-* @@ -8,8 +8,15 @@ Disassembly of section .text: -0+1200000e8 : - 1200000e8: 14000004 lu12i.w \$a0, 0 - 1200000ec: 03800084 ori \$a0, \$a0, 0x0 - 1200000f0: 03400000 nop.* - 1200000f4: 03400000 nop.* +[0-9a-f]+ : + +[0-9a-f]+: 14000004 lu12i.w \$a0, .* + +[0-9a-f]+: 03800084 ori \$a0, \$a0, .* + +[0-9a-f]+: 03400000 nop + +[0-9a-f]+: 03400000 nop + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 02c4e005 li.d \$a1, .* + +[0-9a-f]+: 16000005 lu32i.d \$a1, .* + +[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .* + +[0-9a-f]+: 00109484 add.d \$a0, \$a0, \$a1 + +[0-9a-f]+: 28c00081 ld.d \$ra, \$a0, 0 + +[0-9a-f]+: 4c000021 jirl \$ra, \$ra, 0 diff --git a/ld/testsuite/ld-loongarch-elf/desc-le.s b/ld/testsuite/ld-loongarch-elf/desc-le.s index 9ffaa2d668d..de6ab41f3eb 100644 --- a/ld/testsuite/ld-loongarch-elf/desc-le.s +++ b/ld/testsuite/ld-loongarch-elf/desc-le.s @@ -8,7 +8,7 @@ var: fn1: # DESC will relax to LE. - pcalau12i $a0,%desc_pc_hi20(var) - addi.d $a0,$a0,%desc_pc_lo12(var) - ld.d $ra,$a0,%desc_ld(var) - jirl $ra,$ra,%desc_call(var) + la.tls.desc $a0,var + + # extreme cmodel do not do transition. + la.tls.desc $a0,$a1,var diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.d b/ld/testsuite/ld-loongarch-elf/ie-le.d index 42694d7f9f0..28f3a660a2e 100644 --- a/ld/testsuite/ld-loongarch-elf/ie-le.d +++ b/ld/testsuite/ld-loongarch-elf/ie-le.d @@ -1,5 +1,5 @@ #as: -#ld: -z norelro -e 0x0 +#ld: -z norelro -e0 #objdump: -dr #skip: loongarch32-*-* @@ -8,6 +8,11 @@ Disassembly of section .text: -0+1200000e8 : - 1200000e8: 14000004 lu12i.w \$a0, 0 - 1200000ec: 03800084 ori \$a0, \$a0, 0x0 +[0-9a-f]+ : + +[0-9a-f]+: 14000004 lu12i.w \$a0, .* + +[0-9a-f]+: 03800084 ori \$a0, \$a0, .* + +[0-9a-f]+: 1a000084 pcalau12i \$a0, .* + +[0-9a-f]+: 02c44005 li.d \$a1, .* + +[0-9a-f]+: 16000005 lu32i.d \$a1, .* + +[0-9a-f]+: 030000a5 lu52i.d \$a1, \$a1, .* + +[0-9a-f]+: 380c1484 ldx.d \$a0, \$a0, \$a1 diff --git a/ld/testsuite/ld-loongarch-elf/ie-le.s b/ld/testsuite/ld-loongarch-elf/ie-le.s index 795c7ce49cf..e582a2de528 100644 --- a/ld/testsuite/ld-loongarch-elf/ie-le.s +++ b/ld/testsuite/ld-loongarch-elf/ie-le.s @@ -6,6 +6,7 @@ var: .global fn1 .type gn1,@function fn1: - # expect IE to relax LE. - pcalau12i $a0,%ie_pc_hi20(var) - ld.d $a0,$a0,%ie_pc_lo12(var) + # expect IE to relax LE in nomal cmodel. + la.tls.ie $a0,var + # extreme cmodel do not do transition. + la.tls.ie $a0,$a1,var diff --git a/ld/testsuite/ld-loongarch-elf/macro_op.d b/ld/testsuite/ld-loongarch-elf/macro_op.d index c9493918a93..46b849a9c33 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op.d @@ -144,8 +144,10 @@ Disassembly of section .text: [ ]+f8: R_LARCH_TLS_LE_LO12[ ]+TLS1 [ ]+fc:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 [ ]+fc: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 +[ ]+fc: R_LARCH_RELAX[ ]+\*ABS\* [ ]+100:[ ]+28c00084[ ]+ld.d[ ]+\$a0, \$a0, 0 [ ]+100: R_LARCH_TLS_IE_PC_LO12[ ]+TLS1 +[ ]+100: R_LARCH_RELAX[ ]+\*ABS\* [ ]+104:[ ]+1a000004[ ]+pcalau12i[ ]+\$a0, 0 [ ]+104: R_LARCH_TLS_IE_PC_HI20[ ]+TLS1 [ ]+108:[ ]+02c00005[ ]+li.d[ ]+\$a1, 0 diff --git a/ld/testsuite/ld-loongarch-elf/macro_op_32.d b/ld/testsuite/ld-loongarch-elf/macro_op_32.d index a7349aa8dc0..f8aaacda345 100644 --- a/ld/testsuite/ld-loongarch-elf/macro_op_32.d +++ b/ld/testsuite/ld-loongarch-elf/macro_op_32.d @@ -53,8 +53,10 @@ Disassembly of section .text: 44: R_LARCH_TLS_LE_LO12 TLS1 48: 1a000004 pcalau12i \$a0, 0 48: R_LARCH_TLS_IE_PC_HI20 TLS1 + 48: R_LARCH_RELAX \*ABS\* 4c: 28800084 ld.w \$a0, \$a0, 0 4c: R_LARCH_TLS_IE_PC_LO12 TLS1 + 4c: R_LARCH_RELAX \*ABS\* 50: 1a000004 pcalau12i \$a0, 0 50: R_LARCH_TLS_LD_PC_HI20 TLS1 50: R_LARCH_RELAX \*ABS\*