From patchwork Mon Nov 14 23:02:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20064 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2408125wru; Mon, 14 Nov 2022 15:04:14 -0800 (PST) X-Google-Smtp-Source: AA0mqf4eTmG0C4RAGJP+ZgQnzgtlM7UbRwwJXkWaY3D4HTnSZ1L6BYrTkgIVvE4vY/SFO9dFOw4+ X-Received: by 2002:a05:6402:4498:b0:461:b754:ac3c with SMTP id er24-20020a056402449800b00461b754ac3cmr12667508edb.241.1668467053855; Mon, 14 Nov 2022 15:04:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668467053; cv=none; d=google.com; s=arc-20160816; b=ciJsnujNDO3N8dvVyLS3597On8qLSge8TPRfF34RUrC4FPeaBXFhCP5Gb1/2/W6Eah ksI05AjSARkdIevKclvfb586tTO3q3+hto3CMnT1MDOdmOYoMrUui8qkxsB5+ZaYDMs0 vccQbIQZzaZKRiK+ym5q/AOiV3NA6Udfs0WtT9XxEdQezxP9TkVl218x2dSxThvwQ4EA tSHInbPmhWZOXuD7FboJLDPBMmrfO4OLhoU9zmohQtvmr/2HUqF/rAnKRwfgMUgOmhvX i//NZXUNg3Jym2q+uoD4F4o0DE/vW8gMa+SAla1cCaGoIzjMuR0LV7/kNeWFhi6j+34L Rscg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :message-id:date:subject:cc:to:from:dkim-signature; bh=6mcXBrJjHWQ+FSKX2vFQFOgZkoM6QEz9hkS/30YKtQc=; b=Lc8wd2/WOOS2EhF/sMZ93DSpZ2pzzhBbMQVyjvFhIsLI0U1XhFVHZH9NupCd40A8nN Q2gnvXL4au/YNftE8UkacgKrGwP1ogvP4s+2umHn5O0VHJZw8cEBoCrCUNv53eLrsEPw efNEXwSHuj8G0wv0x1c8RXuzQNGrMCz1r38/fw/LFP/j9INJLLqFmk8X4cMruR5f+bZK eJAJCDKQAzJS05kchxCuieGbSvpd37twb9Jv5UAaE3qiO4bYnaspvuuJGwkmGIxQdVwf IruQAU8yD0zJtfufnSUVGN5ROsyiAwv+I7JmRLdvTetD/iViddEHCZBmmp6K1SPUXGhe P6nw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kvaRqXhn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id gs6-20020a1709072d0600b007919f213511si11224047ejc.951.2022.11.14.15.03.46; Mon, 14 Nov 2022 15:04:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kvaRqXhn; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237135AbiKNXC0 (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:26 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51052 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236055AbiKNXCY (ORCPT ); Mon, 14 Nov 2022 18:02:24 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CE5F1A22B; Mon, 14 Nov 2022 15:02:23 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id CCA6961480; Mon, 14 Nov 2022 23:02:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 1F9DEC433C1; Mon, 14 Nov 2022 23:02:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466942; bh=Sl9o27hByjI3ej53FtoyhZf0M6+nUUScj+ybS1qbm94=; h=From:To:Cc:Subject:Date:From; b=kvaRqXhnMOXQESXOcsSVDo9Nk5CfbUfiap5x3pirS63xGR0VKoMJQe/8swsU6lR2/ nj0/iy8dsmsKjtbwzv6x6xJTAT6O40cOmknYtSNS7n84AlCJOmV2FV9pRh+JT3UZk9 XRY648tdsjZiO7KwY7cNjkJkO8CdJNNb9pE6Yo9AJ8kgED99oG+niLLf4dJNWLCD72 I3c61IWEQRHappsuGvNhQlQ0a3crDiBBAMWorFOU4UzcclHyLsoSvbynpHhWRH/H6u D2ba8ZgZn/Lr1SmljJkvnHBT6op43L9EF5olnIRnfbB8ITEMed1xGfVdvVHoKxMaSF Jl2bDWEFiAKBQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Date: Mon, 14 Nov 2022 17:02:12 -0600 Message-Id: <20221114230217.202634-1-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514509306687641?= X-GMAIL-MSGID: =?utf-8?q?1749514509306687641?= Document the optional "altr,sysmgr-syscon" binding that is used to access the System Manager register that controls the SDMMC clock phase. Signed-off-by: Dinh Nguyen Reviewed-by: Rob Herring --- v9: remove required for "altr,sysmgr-syscon" v8: remove "" around synopsys-dw-mshc-common.yaml# v7: and "not" for the required "altr,sysmgr-syscon" binding v6: make "altr,sysmgr-syscon" optional v5: document reg shift v4: add else statement v3: document that the "altr,sysmgr-syscon" binding is only applicable to "altr,socfpga-dw-mshc" v2: document "altr,sysmgr-syscon" in the MMC section --- .../bindings/mmc/synopsys-dw-mshc.yaml | 32 +++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml index ae6d6fca79e2..e1f5f26f3f1c 100644 --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Synopsys Designware Mobile Storage Host Controller Binding -allOf: - - $ref: "synopsys-dw-mshc-common.yaml#" - maintainers: - Ulf Hansson @@ -38,6 +35,35 @@ properties: - const: biu - const: ciu + altr,sysmgr-syscon: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to the sysmgr node + - description: register offset that controls the SDMMC clock phase + - description: register shift for the smplsel(drive in) setting + description: + This property is optional. Contains the phandle to System Manager block + that contains the SDMMC clock-phase control register. The first value is + the pointer to the sysmgr, the 2nd value is the register offset for the + SDMMC clock phase register, and the 3rd value is the bit shift for the + smplsel(drive in) setting. + +allOf: + - $ref: synopsys-dw-mshc-common.yaml# + + - if: + properties: + compatible: + contains: + const: altr,socfpga-dw-mshc + then: + properties: + altr,sysmgr-syscon: true + else: + properties: + altr,sysmgr-syscon: false + required: - compatible - reg From patchwork Mon Nov 14 23:02:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20061 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2407991wru; Mon, 14 Nov 2022 15:03:54 -0800 (PST) X-Google-Smtp-Source: AA0mqf4gTtcJ6+cEU2HGRJjIqWwZNaBXIKqRs+UmHL9GKR747LT5QEr7p91j3el1qZ6NkN1TN4wy X-Received: by 2002:a17:906:5f8b:b0:79a:101a:7e57 with SMTP id a11-20020a1709065f8b00b0079a101a7e57mr12079941eju.368.1668467034634; Mon, 14 Nov 2022 15:03:54 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668467034; cv=none; d=google.com; s=arc-20160816; b=JJM6/XF1SGEBLPOpaz/tLsXUU/JVPdKRKbQjrf05009yNXOJOPYZrjDm/wG7ld2/KH Od5Q/GcGwMKeNipaYcTS5XdP7o8KUvbzUm+pNgzpjLT3Zr3OQRkB2KA5c94i+v7t8u1n a1WtVCQjN2SVcKu3kgbWXxNsA657TwLVqn6o1zri6sRZWb/uCwJNCDAHJlbD6y+s1TSM co5DaU3ZOgQZ92FCeDQsi676J02IH/F6fZPlHqC0ImPznWqqSbnKXE5A5jILtDRLlJ5e bRuKaA1soTrRUcBWPGHjGcuLG4m0Aw+adybmn2ZNY334sbUTT5Zq9mh0mDqVf0ytJUE9 1Acg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=WzSfNfVJ5nmwlQPESNwDylJMk4kHvFYJ6ePxQrgx/ds=; b=NP4BgYcKruzSGXGYyisdL5MuaOV4kdD18ekzmq+QQFvlsSyWopnZJMx/uKwhLJnX/G 5GW7gJeMoTa1xUFU7BzoRk6jKN93jjsE3LiIlU2pacfSpCSKTB0uhHXJfuesjvcoyZgQ 9e2IdU5L3QW6EqFPLzt7RwAOcovRQJxvfWyRz4kak0HYbNucqleFOTbBdqlTorNCdH+v ao+kWAuZcph64W3YYkg0Dw2Cw5vygAVVr82yXcS03UsSQ9qhNaNjmK8435GkzFaWD5cD ufNp/LHTAhPSYYeOHmEc8NamXBlGIVxEqSNu/CbMfJP61UeISZeRb0rUNZlsSycw+4BN kCZA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IgjBC8Tc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id u29-20020a50c05d000000b0046198ab2c0bsi8612901edd.283.2022.11.14.15.03.28; Mon, 14 Nov 2022 15:03:54 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=IgjBC8Tc; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236214AbiKNXCa (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:30 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51064 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236858AbiKNXCZ (ORCPT ); Mon, 14 Nov 2022 18:02:25 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 981561AF04; Mon, 14 Nov 2022 15:02:24 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 3424F61497; Mon, 14 Nov 2022 23:02:24 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 88281C43147; Mon, 14 Nov 2022 23:02:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466943; bh=eQMQ4czfcU+mAwVPimded023jRz/vpbouvlqpqu+524=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=IgjBC8TcZyFTWldcCKQR1YgSobzfwySngWqMHITV0cF0AxAv4RS+d0sas/2e2GTtJ nj7SBubKP80dGzLrgbZ7Q1BzWxAsNjIOCXcog+U7tzXaJh8e/r5Y2YiiqjURtYGx2Y PSrd9UFCyveWUmiyY1GbjAp2K5TzKALGr7j+De4XSbvUgcsMvuT+uNjNMMFYOQ9JM7 cZKcKn6ACLK0IM/1kmh2fuO0Umm14eZ6xWaoPwLRbcz0sXrtWbFiuo/qKKoxxF+lEg oIAH59ruA6ZwuqhnQSrsthKE8a9SIJApleoOz4DSkTFYFaQIa4LEZeje3e8qpfK0kt 9kn8HhUNjP+MQ== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 2/6] arm64: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Mon, 14 Nov 2022 17:02:13 -0600 Message-Id: <20221114230217.202634-2-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114230217.202634-1-dinguyen@kernel.org> References: <20221114230217.202634-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514489470056848?= X-GMAIL-MSGID: =?utf-8?q?1749514489470056848?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v9: no changes v8: no changes v7: no changes v6: no changes v5: add back reg_shift v4: no change v3: removed unnecessary property in "altr,sysmgr-syscon" --- arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 1 + arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_agilex.dtsi | 1 + arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts | 1 + arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts | 1 + 5 files changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi index 14c220d87807..55c5e1fdddc7 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi @@ -309,6 +309,7 @@ mmc: mmc@ff808000 { <&clkmgr STRATIX10_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts index 48424e459f12..19e7284b4cd5 100644 --- a/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts +++ b/arch/arm64/boot/dts/altera/socfpga_stratix10_socdk.dts @@ -105,6 +105,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi index 7bbec8aafa62..849b46dd8098 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex.dtsi @@ -313,6 +313,7 @@ mmc: mmc@ff808000 { <&clkmgr AGILEX_SDMMC_CLK>; clock-names = "biu", "ciu"; iommus = <&smmu 5>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts index 26cd3c121757..07c3f8876613 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts @@ -83,6 +83,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts index 62c66e52b656..08c088571270 100644 --- a/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts +++ b/arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts @@ -74,6 +74,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { From patchwork Mon Nov 14 23:02:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20063 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2408119wru; Mon, 14 Nov 2022 15:04:13 -0800 (PST) X-Google-Smtp-Source: AA0mqf6mI5tA9F8AxMwNqE4nXDOxqZCNf23UbqgZAVHPtAsIPIfhD2lwMo6b6ES4p6GRDlJHVYYY X-Received: by 2002:a17:906:7c5:b0:78d:9f46:5b6 with SMTP id m5-20020a17090607c500b0078d9f4605b6mr11715543ejc.158.1668467053446; Mon, 14 Nov 2022 15:04:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668467053; cv=none; d=google.com; s=arc-20160816; b=VyJ3ZABL4ScBdy5RD11db/3+0dwy6ZFSBKDcOQBXUsqHX366BHQg/VL2nZ9f+jPCLI GM5sySSpivw69ABWuULp8ZGEaZw/iM8G1ntvQMj8WH/1azqnZz1qo01p2rGPLfl+2KdO rb8Rom36c7oLrUiRZOpV8m2Qo1psi8zIAjxwNtiMLQF/HXKLfw8bzE5Szh5HfAUHqXtC DWm/21oJcQqhSb4AUsGRE/RMM3KqY9WRmc9b3/4mcaiAvrkNv5EU+7GVVK1jUrkOL4Wx 5/VB9oIJuLSsgsUwWXkw/niiaAr5/yV806ybQDmblqKsxoCKIgTLhv51qEGl8iG63nTf oiWg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=f22AQgGSZ70cx7VbXW6rg2+G9G1cwXPmJAXT9WZhwkc=; b=xtuXmXmC4OZy3VdVRAyZU3KjT2Lz2WnGIna/PBFysBFKqvXTOLM0LNMaPi+6H5SP4R T3BsGF08419X25vjqyzlExrU2o15xLyLy9aC38WbB4xFJhvaUWRtAmrCt6aSRiI1NpL1 5GxYFJilKIRnO24ulto82fstRCuRrlgvAIH7ltiql8tS33MMtAK7EcrJe4QqH5J2Xm/t ve+p2k5n7Cs95htTVNXNx7dzyoyrqt1wRkSg8r26OWedTGjb9rHuR80cRX46lhdKTr/U ZO2F7oSdoCFV4g5ikZmMM51eLNdzWPYR1I5uyrj38JLBKvbUq9J6pXn9ncE1mJxgwH2V JXqQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QKHEJHuK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id y8-20020a056402270800b004675cf238cbsi8092232edd.322.2022.11.14.15.03.44; Mon, 14 Nov 2022 15:04:13 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QKHEJHuK; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237861AbiKNXCk (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:40 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51112 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237809AbiKNXC3 (ORCPT ); Mon, 14 Nov 2022 18:02:29 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D1C511B1E5; Mon, 14 Nov 2022 15:02:27 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 7B881B815BE; Mon, 14 Nov 2022 23:02:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D8BFEC4347C; Mon, 14 Nov 2022 23:02:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466945; bh=XKw+Y6QvQP4tCxCkEPcaR63DnAXcOW/zkfrjgLuBJts=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QKHEJHuKtZTfTGKo/7rQUVe1yQG4fBu/L6gZPU4I5K/+UX0jMDOiKcV26fWNaiHlb geiIQ4Xe/TuLB771zhutd+GLanAToJ9ikARie07bR9tARo7dju2G8oL0UqJHKVJ5jS I61+eVRdwo7t97CWzPLZl7fOVRz0wrbkxVDNZ1V41P4X9iTuIsTFadNfX/PdMCrab3 8MVVuo2cyNwXc0OPBzi+mCZK7+dT11rWirxaYTefT2Slw6jrom798s0Aj7McgO0Obu t7HGOUQnQUaV7Mkq+Ib4IWitYFfZtbxuV7KKejknKY1E4k62twtxazo+FjdiDAd1k2 09AhEUMWCCGIw== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 3/6] arm: dts: socfpga: Add clk-phase-sd-hs property to the sdmmc node Date: Mon, 14 Nov 2022 17:02:14 -0600 Message-Id: <20221114230217.202634-3-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114230217.202634-1-dinguyen@kernel.org> References: <20221114230217.202634-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514508999450792?= X-GMAIL-MSGID: =?utf-8?q?1749514508999450792?= The sdmmc controller's CIU(Card Interface Unit) clock's phase can be adjusted through the register in the system manager. Add the binding "altr,sysmgr-syscon" to the SDMMC node for the driver to access the system manager. Add the "clk-phase-sd-hs" property in the SDMMC node to designate the smpsel and drvsel properties for the CIU clock. Signed-off-by: Dinh Nguyen --- v9: no changes v8: no changes v7: no changes v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi | 1 + arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts | 1 + arch/arm/boot/dts/socfpga_arria5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5.dtsi | 1 + arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi | 1 + 7 files changed, 7 insertions(+) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 2459f3cd7dd9..604fc6e0c4ad 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -765,6 +765,7 @@ mmc: dwmmc0@ff704000 { clocks = <&l4_mp_clk>, <&sdmmc_clk_divided>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x108 3>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index 4370e3cbbb4b..b6ebe207e2bc 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -666,6 +666,7 @@ mmc: dwmmc0@ff808000 { clocks = <&l4_mp_clk>, <&sdmmc_clk>; clock-names = "biu", "ciu"; resets = <&rst SDMMC_RESET>; + altr,sysmgr-syscon = <&sysmgr 0x28 4>; status = "disabled"; }; diff --git a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi index ad7cd14de6b6..41f865c8c098 100644 --- a/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10_mercury_aa1.dtsi @@ -73,6 +73,7 @@ &mmc { cap-sd-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &osc1 { diff --git a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts index 64dc0799f3d7..d3969367f4b5 100644 --- a/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts +++ b/arch/arm/boot/dts/socfpga_arria10_socdk_sdmmc.dts @@ -12,6 +12,7 @@ &mmc { cap-mmc-highspeed; broken-cd; bus-width = <4>; + clk-phase-sd-hs = <0>, <135>; }; &eccmgr { diff --git a/arch/arm/boot/dts/socfpga_arria5.dtsi b/arch/arm/boot/dts/socfpga_arria5.dtsi index 22dbf07afcff..b531639ce7dc 100644 --- a/arch/arm/boot/dts/socfpga_arria5.dtsi +++ b/arch/arm/boot/dts/socfpga_arria5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index 319a71e41ea4..a9d1ba66f1ff 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -23,6 +23,7 @@ mmc0: dwmmc0@ff704000 { bus-width = <4>; cap-mmc-highspeed; cap-sd-highspeed; + clk-phase-sd-hs = <0>, <135>; }; sysmgr@ffd08000 { diff --git a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi index bd92806ffc12..3b9daddf91cd 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5_mcv.dtsi @@ -18,5 +18,6 @@ memory@0 { &mmc0 { /* On-SoM eMMC */ bus-width = <8>; + clk-phase-sd-hs = <0>, <135>; status = "okay"; }; From patchwork Mon Nov 14 23:02:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20075 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2408967wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id cy24-20020a0564021c9800b00458cdba7a90si9473930edb.471.2022.11.14.15.05.33; Mon, 14 Nov 2022 15:05:57 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=X88qJahL; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237901AbiKNXCo (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:44 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51136 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237841AbiKNXC3 (ORCPT ); Mon, 14 Nov 2022 18:02:29 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0C5091B7A2; Mon, 14 Nov 2022 15:02:29 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id BC52EB815BD; Mon, 14 Nov 2022 23:02:27 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6900CC43140; Mon, 14 Nov 2022 23:02:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466946; bh=mP1glOMgwwjtxxD/5YyQGpy9Kmwl+tbpsLXysXmem+0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=X88qJahLWjU6ipVHtqUEc2mvYoJbNkgZHmy3j0WyJZi4p5bH7nFWT70KpFbBbASgI ugMuU270WgpeAi6aXl/dD6joIQRx0iqTyi0MM/7nyDGifmXkPWlU0Rj7dlmqKH3Ov1 4HleICOIGJJ8Hk7FupQpyhxiTmtPhPYP+YPFG35w0cHMxJRBZ8anYsstT81Fz8iFGK vGEwboFb5YlYtTluHS+2s613TXX0shIu56wOoJm28pkjY79U9+gx4uRFjrieZUhoaB NEtV6mEQpB5NfwT8ep0gZ8p+j+BL83DsD3OY6+WreLqBbJuot7xRLIV10rRMbVUTVB Y+XHRn9Tp+1ng== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 4/6] mmc: dw_mmc-pltfm: socfpga: add method to configure clk-phase Date: Mon, 14 Nov 2022 17:02:15 -0600 Message-Id: <20221114230217.202634-4-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114230217.202634-1-dinguyen@kernel.org> References: <20221114230217.202634-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514618047942917?= X-GMAIL-MSGID: =?utf-8?q?1749514618047942917?= The clock-phase settings for the SDMMC controller in the SoCFPGA platforms reside in a register in the System Manager. Add a method to access that register through the syscon interface. Signed-off-by: Dinh Nguyen --- v9: no changes v8: no changes v7: use dev_warn if clk-phase-sd-hs is specified, but "altr,sysmgr-syscon" is not found v6: not getting the clk-phase-sd-hs is not a hard failure v5: change error handling from of_property_read_variable_u32_array() support arm32 by reading the reg_shift v4: no change v3: add space before &socfpga_drv_data v2: simplify clk-phase calculations --- drivers/mmc/host/dw_mmc-pltfm.c | 41 ++++++++++++++++++++++++++++++++- 1 file changed, 40 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c index 9901208be797..13e55cff8237 100644 --- a/drivers/mmc/host/dw_mmc-pltfm.c +++ b/drivers/mmc/host/dw_mmc-pltfm.c @@ -17,10 +17,16 @@ #include #include #include +#include +#include #include "dw_mmc.h" #include "dw_mmc-pltfm.h" +#define SOCFPGA_DW_MMC_CLK_PHASE_STEP 45 +#define SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel, reg_shift) \ + ((((smplsel) & 0x7) << reg_shift) | (((drvsel) & 0x7) << 0)) + int dw_mci_pltfm_register(struct platform_device *pdev, const struct dw_mci_drv_data *drv_data) { @@ -62,9 +68,42 @@ const struct dev_pm_ops dw_mci_pltfm_pmops = { }; EXPORT_SYMBOL_GPL(dw_mci_pltfm_pmops); +static int dw_mci_socfpga_priv_init(struct dw_mci *host) +{ + struct device_node *np = host->dev->of_node; + struct regmap *sys_mgr_base_addr; + u32 clk_phase[2] = {0}, reg_offset, reg_shift; + int i, rc, hs_timing; + + rc = of_property_read_variable_u32_array(np, "clk-phase-sd-hs", &clk_phase[0], 2, 0); + if (rc < 0) + return 0; + + sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon"); + if (IS_ERR(sys_mgr_base_addr)) { + dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n"); + return 0; + } + + of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset); + of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift); + + for (i = 0; i < ARRAY_SIZE(clk_phase); i++) + clk_phase[i] /= SOCFPGA_DW_MMC_CLK_PHASE_STEP; + + hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1], reg_shift); + regmap_write(sys_mgr_base_addr, reg_offset, hs_timing); + + return 0; +} + +static const struct dw_mci_drv_data socfpga_drv_data = { + .init = dw_mci_socfpga_priv_init, +}; + static const struct of_device_id dw_mci_pltfm_match[] = { { .compatible = "snps,dw-mshc", }, - { .compatible = "altr,socfpga-dw-mshc", }, + { .compatible = "altr,socfpga-dw-mshc", .data = &socfpga_drv_data, }, { .compatible = "img,pistachio-dw-mshc", }, {}, }; From patchwork Mon Nov 14 23:02:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20076 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2409035wru; Mon, 14 Nov 2022 15:06:05 -0800 (PST) X-Google-Smtp-Source: AA0mqf57/xhxJ97SPqJXhfpPsGDK9U9NF2yiQ+skVRMBVa1JuhdMVL1deB2nzqZpV2atWZdxpEQH X-Received: by 2002:a17:906:e0d4:b0:7ad:d1ab:2431 with SMTP id gl20-20020a170906e0d400b007add1ab2431mr11189700ejb.213.1668467165011; Mon, 14 Nov 2022 15:06:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668467165; cv=none; d=google.com; s=arc-20160816; b=YhJteS+j4K7GFb+NC7EK54KUKiNYjzJSyRku7wI1ShcwsfOPnw1QLxlZ4x7DBaUKx6 eM3e5IMBLtFNcFpl+38MCm0qp7PdZtHP2DK7YNd9c7sjhFIEZD7P7eYMoo2FBkRogJeY c5MxFv612VdESdpa1kTdhjtKKBvm+Y3BV9LVeU+xluUqRoSErM/Ecp6o5ZevhZfPvQBF s3LsomVhR84PD2qoiYOKCAjojxRMSOh4v/W0d7NBsVIE1AJ+rWFxX+1yKB8ezkymDv13 Il2lV5u9hL++wzsrPfZ+nmJMp5kDghth/G07XYvT0uOJlTn/7msKQKjfybaStHJ3ciEr Vfiw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=sFntJdOoL65M7DFCIN9cd15fZj4zG3AsFyNj0jjqrJM=; b=zNkKcPsw/TuKGp55IxiVmZzrUSKOOCT9oUt8h/gyJDMOAfesUKZjM/n8zjfbj+4++e 5dIQWf4GTVTyp/rJ2YYAotqZEA+U66WZZn6EvuNDM/MgGbikpeYaSZDpdNM988bPOHdV eiCOctUHUkzFw4N1ezCWlkhb1yWlGU5JMgmyNi30gXvhdclnnEq6yD9/8/fJ93P+dPLg 2h+C1zBkdLrikhkd07U9gDewEc8aIdpNmZdSNAGTKnEf7c/9p32AMzQ8iW7FcbT++Duk 7hzY36WLM1Lb7QRUoOe4F2T6MwAhWHeAvLPN4Zw8MAykirsdhQkj0FvSm3IyVjUdvspa qKrA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QErMp37R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id 6-20020a170906318600b007ae10525573si9228242ejy.671.2022.11.14.15.05.39; Mon, 14 Nov 2022 15:06:04 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=QErMp37R; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237916AbiKNXCr (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:47 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237837AbiKNXC3 (ORCPT ); Mon, 14 Nov 2022 18:02:29 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CBD6A1A22B; Mon, 14 Nov 2022 15:02:28 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5817461495; Mon, 14 Nov 2022 23:02:28 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id AE8F4C4314F; Mon, 14 Nov 2022 23:02:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466947; bh=ImluY7K1mzyE5Sw9HQCSxJdpuWkFURiyri1as01p1O0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=QErMp37RVXHvJ5igimaw2eIfWT+3ERYfIW4lS6++DJPA9j1K77rVk6kjHOVCr8CPs lWRrJApEGyiLyAdNxtypP/ONj/Q6/h2KvXNalddguqJmzbIydYehFeGFo2cHYruGcP zWy7jLNB8P4O9rceaSba2iwBiwlf8RAWYo9PvOYYAXA8ISDZMZ0HrFxOwz1DPIX3c9 Bem1xcmNmjgWT/g+4hpLqipy/iK0Bc5vikzvAwSIXNYrXgVu+5lX4y6+higkYKKH2A t+qbmdJheUxjvU+n4M8AFNLRNBXJJahjU992wJ2WP1td6M7ye6QZnztl7kmpqZQ3iV +DwY5wtubGJBA== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 5/6] clk: socfpga: remove the setting of clk-phase for sdmmc_clk Date: Mon, 14 Nov 2022 17:02:16 -0600 Message-Id: <20221114230217.202634-5-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114230217.202634-1-dinguyen@kernel.org> References: <20221114230217.202634-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514626137705021?= X-GMAIL-MSGID: =?utf-8?q?1749514626137705021?= Now that the SDMMC driver supports setting the clk-phase, we can remove the need to do it in the clock driver. Acked-by: Stephen Boyd Signed-off-by: Dinh Nguyen --- v9: no changes v8: no changes v7: add acked-by v6: remove unused clk_phase in clk-gate.c v5: new --- drivers/clk/socfpga/clk-gate-a10.c | 68 ------------------------------ drivers/clk/socfpga/clk-gate.c | 61 --------------------------- drivers/clk/socfpga/clk.h | 1 - 3 files changed, 130 deletions(-) diff --git a/drivers/clk/socfpga/clk-gate-a10.c b/drivers/clk/socfpga/clk-gate-a10.c index 738c53391e39..7cdf2f07c79b 100644 --- a/drivers/clk/socfpga/clk-gate-a10.c +++ b/drivers/clk/socfpga/clk-gate-a10.c @@ -35,59 +35,7 @@ static unsigned long socfpga_gate_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - for (i = 0; i < ARRAY_SIZE(clk_phase); i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - - hs_timing = SYSMGR_SDMMC_CTRL_SET_AS10(clk_phase[0], clk_phase[1]); - if (!IS_ERR(socfpgaclk->sys_mgr_base_addr)) - regmap_write(socfpgaclk->sys_mgr_base_addr, - SYSMGR_SDMMCGRP_CTRL_OFFSET, hs_timing); - else - pr_err("%s: cannot set clk_phase because sys_mgr_base_addr is not available!\n", - __func__); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_gate_clk_recalc_rate, }; @@ -96,7 +44,6 @@ static void __init __socfpga_gate_init(struct device_node *node, { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -136,21 +83,6 @@ static void __init __socfpga_gate_init(struct device_node *node, socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - - socfpga_clk->sys_mgr_base_addr = - syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(socfpga_clk->sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", - __func__); - kfree(socfpga_clk); - return; - } - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk-gate.c b/drivers/clk/socfpga/clk-gate.c index 53d6e3ec4309..3e347b9e9eff 100644 --- a/drivers/clk/socfpga/clk-gate.c +++ b/drivers/clk/socfpga/clk-gate.c @@ -108,61 +108,7 @@ static unsigned long socfpga_clk_recalc_rate(struct clk_hw *hwclk, return parent_rate / div; } -static int socfpga_clk_prepare(struct clk_hw *hwclk) -{ - struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk); - struct regmap *sys_mgr_base_addr; - int i; - u32 hs_timing; - u32 clk_phase[2]; - - if (socfpgaclk->clk_phase[0] || socfpgaclk->clk_phase[1]) { - sys_mgr_base_addr = syscon_regmap_lookup_by_compatible("altr,sys-mgr"); - if (IS_ERR(sys_mgr_base_addr)) { - pr_err("%s: failed to find altr,sys-mgr regmap!\n", __func__); - return -EINVAL; - } - - for (i = 0; i < 2; i++) { - switch (socfpgaclk->clk_phase[i]) { - case 0: - clk_phase[i] = 0; - break; - case 45: - clk_phase[i] = 1; - break; - case 90: - clk_phase[i] = 2; - break; - case 135: - clk_phase[i] = 3; - break; - case 180: - clk_phase[i] = 4; - break; - case 225: - clk_phase[i] = 5; - break; - case 270: - clk_phase[i] = 6; - break; - case 315: - clk_phase[i] = 7; - break; - default: - clk_phase[i] = 0; - break; - } - } - hs_timing = SYSMGR_SDMMC_CTRL_SET(clk_phase[0], clk_phase[1]); - regmap_write(sys_mgr_base_addr, SYSMGR_SDMMCGRP_CTRL_OFFSET, - hs_timing); - } - return 0; -} - static struct clk_ops gateclk_ops = { - .prepare = socfpga_clk_prepare, .recalc_rate = socfpga_clk_recalc_rate, .get_parent = socfpga_clk_get_parent, .set_parent = socfpga_clk_set_parent, @@ -172,7 +118,6 @@ void __init socfpga_gate_init(struct device_node *node) { u32 clk_gate[2]; u32 div_reg[3]; - u32 clk_phase[2]; u32 fixed_div; struct clk_hw *hw_clk; struct socfpga_gate_clk *socfpga_clk; @@ -218,12 +163,6 @@ void __init socfpga_gate_init(struct device_node *node) socfpga_clk->div_reg = NULL; } - rc = of_property_read_u32_array(node, "clk-phase", clk_phase, 2); - if (!rc) { - socfpga_clk->clk_phase[0] = clk_phase[0]; - socfpga_clk->clk_phase[1] = clk_phase[1]; - } - of_property_read_string(node, "clock-output-names", &clk_name); init.name = clk_name; diff --git a/drivers/clk/socfpga/clk.h b/drivers/clk/socfpga/clk.h index d80115fbdd6a..9a2fb2dde5b8 100644 --- a/drivers/clk/socfpga/clk.h +++ b/drivers/clk/socfpga/clk.h @@ -50,7 +50,6 @@ struct socfpga_gate_clk { u32 width; /* only valid if div_reg != 0 */ u32 shift; /* only valid if div_reg != 0 */ u32 bypass_shift; /* only valid if bypass_reg != 0 */ - u32 clk_phase[2]; }; struct socfpga_periph_clk { From patchwork Mon Nov 14 23:02:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dinh Nguyen X-Patchwork-Id: 20065 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2408233wru; 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[2620:137:e000::1:20]) by mx.google.com with ESMTP id a11-20020a056a001d0b00b0056e8a852e3esi9961226pfx.219.2022.11.14.15.04.12; Mon, 14 Nov 2022 15:04:27 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b="roEah/ZC"; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237928AbiKNXCx (ORCPT + 99 others); Mon, 14 Nov 2022 18:02:53 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237863AbiKNXCc (ORCPT ); Mon, 14 Nov 2022 18:02:32 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B75C11B7B2; Mon, 14 Nov 2022 15:02:31 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id 65E1AB815C9; Mon, 14 Nov 2022 23:02:30 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0453EC43146; Mon, 14 Nov 2022 23:02:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668466949; bh=SbGaxIgecXbcJ4YaHl7Qj9l6cKlCJwLyETRWGn6erYU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=roEah/ZCp8R7JeSAGqtvJ+Cw2npX1Pu0V9Eo0Hu7l9QWdnhknsm1kDi9oKzCdicf2 s58zGJxh1/p4tJbfq6c73cEvVKKI4dA9PjJ7JMowcDfhcAEmuv6lydMX8bgxgIqtyg Bq08irWXMl239opwZJDU3DMSabRNurvSX9q5sKThd+jT3IHSOHfngitAUW5nOl9T8+ WXfJ2/nn0uerVbtEGV5yYlv15ZRW7ybm2Sk2jtdD/pZfPZLCDpL5l/wxC4F46IwMio jIqZx4sDLfG3siak2Kt6ubJ6yf2zDf8ebYdNpTXGM6HQkVB4poepM+8w6L8NnlpE1y 7qnyq819sBLUA== From: Dinh Nguyen To: jh80.chung@samsung.com Cc: dinguyen@kernel.org, ulf.hansson@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCHv9 6/6] arm: dts: socfpga: remove "clk-phase" in sdmmc_clk Date: Mon, 14 Nov 2022 17:02:17 -0600 Message-Id: <20221114230217.202634-6-dinguyen@kernel.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20221114230217.202634-1-dinguyen@kernel.org> References: <20221114230217.202634-1-dinguyen@kernel.org> MIME-Version: 1.0 X-Spam-Status: No, score=-7.1 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,RCVD_IN_DNSWL_HI, SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749514523239603266?= X-GMAIL-MSGID: =?utf-8?q?1749514523239603266?= Now that the SDMMC driver can use the "clk-phase-sd-hs" binding, we don't need the clk-phase in the sdmmc_clk anymore. Signed-off-by: Dinh Nguyen --- v9: no changes v8: no changes v7: no changes v6: no changes v5: new --- arch/arm/boot/dts/socfpga.dtsi | 1 - arch/arm/boot/dts/socfpga_arria10.dtsi | 1 - 2 files changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/socfpga.dtsi b/arch/arm/boot/dts/socfpga.dtsi index 604fc6e0c4ad..a2419a5c6c26 100644 --- a/arch/arm/boot/dts/socfpga.dtsi +++ b/arch/arm/boot/dts/socfpga.dtsi @@ -453,7 +453,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-gate-clk"; clocks = <&f2s_periph_ref_clk>, <&main_nand_sdmmc_clk>, <&per_nand_mmc_clk>; clk-gate = <0xa0 8>; - clk-phase = <0 135>; }; sdmmc_clk_divided: sdmmc_clk_divided { diff --git a/arch/arm/boot/dts/socfpga_arria10.dtsi b/arch/arm/boot/dts/socfpga_arria10.dtsi index b6ebe207e2bc..eb528c103d70 100644 --- a/arch/arm/boot/dts/socfpga_arria10.dtsi +++ b/arch/arm/boot/dts/socfpga_arria10.dtsi @@ -365,7 +365,6 @@ sdmmc_clk: sdmmc_clk { compatible = "altr,socfpga-a10-gate-clk"; clocks = <&sdmmc_free_clk>; clk-gate = <0xC8 5>; - clk-phase = <0 135>; }; qspi_clk: qspi_clk {