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[PR113538] Date: Thu, 25 Jan 2024 21:03:05 +0800 Message-ID: <20240125130305.3177181-1-yanzhang.wang@intel.com> X-Mailer: git-send-email 2.42.1 In-Reply-To: <20240125073323.2111124-1-yanzhang.wang@intel.com> References: <20240125073323.2111124-1-yanzhang.wang@intel.com> MIME-Version: 1.0 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SCC_10_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789046912699328402 X-GMAIL-MSGID: 1789067639886180582 From: Yanzhang Wang Also adjust some of the tests for scan-assembly. The behavior is the same as --param=riscv-vector-abi before. gcc/ChangeLog: * config/riscv/riscv.cc (riscv_get_arg_info): Remove the flag. (riscv_fntype_abi): Ditto. * config/riscv/riscv.opt: Ditto. gcc/testsuite/ChangeLog: * gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c: Fix the asm check. * gcc.target/riscv/rvv/base/abi-call-args-1-run.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-1.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-2-run.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-2.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-3-run.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-3.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-4-run.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-args-4.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-error-1.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-return-run.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-return.c: Ditto. * gcc.target/riscv/rvv/base/abi-call-variant_cc.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-1.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c: Ditto. * gcc.target/riscv/rvv/base/abi-callee-saved-2.c: Ditto. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c: Ditto. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c: Ditto. * gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c: Ditto. * gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c: Ditto. * gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c: Ditto. * gcc.target/riscv/rvv/base/spill-10.c: Ditto. * gcc.target/riscv/rvv/base/spill-11.c: Ditto. * gcc.target/riscv/rvv/base/spill-9.c: Ditto. * gcc.target/riscv/rvv/base/tuple_vundefined.c: Ditto. * gcc.target/riscv/rvv/base/vcreate.c: Ditto. * gcc.target/riscv/rvv/base/vlmul_ext-1.c: Ditto. * gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c: Ditto. * gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c: Ditto. * lib/target-supports.exp: Remove the flag. Signed-off-by: Yanzhang Wang --- gcc/config/riscv/riscv.cc | 7 +++---- gcc/config/riscv/riscv.opt | 5 ----- .../vect/costmodel/riscv/rvv/dynamic-lmul1-7.c | 2 +- .../riscv/rvv/base/abi-call-args-1-run.c | 2 +- .../gcc.target/riscv/rvv/base/abi-call-args-1.c | 2 +- .../riscv/rvv/base/abi-call-args-2-run.c | 2 +- .../gcc.target/riscv/rvv/base/abi-call-args-2.c | 2 +- .../riscv/rvv/base/abi-call-args-3-run.c | 2 +- .../gcc.target/riscv/rvv/base/abi-call-args-3.c | 2 +- .../riscv/rvv/base/abi-call-args-4-run.c | 2 +- .../gcc.target/riscv/rvv/base/abi-call-args-4.c | 2 +- .../riscv/rvv/base/abi-call-error-1.c | 2 +- .../riscv/rvv/base/abi-call-return-run.c | 2 +- .../gcc.target/riscv/rvv/base/abi-call-return.c | 2 +- .../riscv/rvv/base/abi-call-variant_cc.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-fixed-1.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-fixed-2.c | 2 +- .../rvv/base/abi-callee-saved-1-save-restore.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1-zcmp.c | 2 +- .../riscv/rvv/base/abi-callee-saved-1.c | 2 +- .../rvv/base/abi-callee-saved-2-save-restore.c | 2 +- .../riscv/rvv/base/abi-callee-saved-2-zcmp.c | 2 +- .../riscv/rvv/base/abi-callee-saved-2.c | 2 +- .../riscv/rvv/base/float-point-dynamic-frm-69.c | 6 +++--- .../riscv/rvv/base/float-point-dynamic-frm-70.c | 6 +++--- .../riscv/rvv/base/float-point-dynamic-frm-71.c | 6 +++--- .../rvv/base/misc_vreinterpret_vbool_vint.c | 4 +--- .../riscv/rvv/base/overloaded_rv32_vadd.c | 2 -- .../riscv/rvv/base/overloaded_rv32_vfadd.c | 2 -- .../riscv/rvv/base/overloaded_rv32_vget_vset.c | 3 +-- .../rvv/base/overloaded_rv32_vloxseg2ei16.c | 1 - .../rvv/base/overloaded_rv32_vreinterpret.c | 6 +----- .../riscv/rvv/base/overloaded_rv64_vadd.c | 2 -- .../riscv/rvv/base/overloaded_rv64_vfadd.c | 2 -- .../riscv/rvv/base/overloaded_rv64_vget_vset.c | 3 +-- .../rvv/base/overloaded_rv64_vloxseg2ei16.c | 2 -- .../rvv/base/overloaded_rv64_vreinterpret.c | 6 +----- .../gcc.target/riscv/rvv/base/spill-10.c | 11 +++++++---- .../gcc.target/riscv/rvv/base/spill-11.c | 17 +++++++++-------- .../gcc.target/riscv/rvv/base/spill-9.c | 12 ++++++------ .../riscv/rvv/base/tuple_vundefined.c | 4 ++-- .../gcc.target/riscv/rvv/base/vcreate.c | 7 +++---- .../gcc.target/riscv/rvv/base/vlmul_ext-1.c | 3 ++- .../riscv/rvv/base/zvfh-over-zvfhmin.c | 12 +----------- .../riscv/rvv/base/zvfhmin-intrinsic.c | 13 +------------ gcc/testsuite/lib/target-supports.exp | 2 -- 46 files changed, 69 insertions(+), 117 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 3ba45ffaa74..ce5cf96a0a1 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -4999,7 +4999,7 @@ riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, /* When disable vector_abi or scalable vector argument is anonymous, this argument is passed by reference. */ - if (riscv_v_ext_mode_p (mode) && (!riscv_vector_abi || !named)) + if (riscv_v_ext_mode_p (mode) && !named) return NULL_RTX; if (named) @@ -5320,9 +5320,8 @@ riscv_fntype_abi (const_tree fntype) You can enable this feature via the `--param=riscv-vector-abi` compiler option. */ - if (riscv_vector_abi - && (riscv_return_value_is_vector_type_p (fntype) - || riscv_arguments_is_vector_type_p (fntype))) + if (riscv_return_value_is_vector_type_p (fntype) + || riscv_arguments_is_vector_type_p (fntype)) return riscv_v_abi (); return default_function_abi; diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 65c656204ca..ae7795614cd 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -543,11 +543,6 @@ Target RejectNegative Joined Enum(riscv_autovec_lmul) Var(riscv_autovec_lmul) In madjust-lmul-cost Target Var(TARGET_ADJUST_LMUL_COST) Init(0) --param=riscv-vector-abi -Target Undocumented Var(riscv_vector_abi) Init(0) -Enable the use of vector registers for function arguments and return value. -This is an experimental switch and may be subject to change in the future. - Enum Name(vsetvl_strategy) Type(enum vsetvl_strategy_enum) Valid arguments to -param=vsetvl-strategy=: diff --git a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c index 87b943cca4c..a8c98c40d6e 100644 --- a/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c +++ b/gcc/testsuite/gcc.dg/vect/costmodel/riscv/rvv/dynamic-lmul1-7.c @@ -41,7 +41,7 @@ foo (int32_t *__restrict a, int32_t *__restrict b, int32_t *__restrict c, } /* { dg-final { scan-assembler {e32,m1} } } */ -/* { dg-final { scan-assembler-not {csrr} } } */ +/* { dg-final { scan-assembler-not {csrr} { xfail "*-*-*" } } } */ /* { dg-final { scan-tree-dump-times "Preferring smaller LMUL loop because it has unexpected spills" 3 "vect" } } */ /* { dg-final { scan-tree-dump-times "Maximum lmul = 8" 1 "vect" } } */ /* { dg-final { scan-tree-dump-times "Maximum lmul = 4" 1 "vect" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c index 85f004422eb..3df7be2c63a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O1 --param=riscv-vector-abi" } */ +/* { dg-options "-O1" } */ /* { dg-additional-sources abi-call-args-1.c } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c index c4858a38a16..10aec5cee0b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c index 06d77035183..7daea1742bf 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O1 --param=riscv-vector-abi" } */ +/* { dg-options "-O1" } */ /* { dg-additional-sources abi-call-args-2.c } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c index 269fbeb104c..f800aea9d9b 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */ #include #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c index 9056d7539e1..5bfcdf8353a 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O1 --param=riscv-vector-abi" } */ +/* { dg-options "-O1" } */ /* { dg-additional-sources abi-call-args-3.c } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c index 8c774716fc9..d3dfec90f6d 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-3.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c index 21618b573cc..25898b69e07 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O1 --param=riscv-vector-abi" } */ +/* { dg-options "-O1" } */ /* { dg-additional-sources abi-call-args-4.c } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c index 2872ffc6d8c..98fdfc1d76c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-args-4.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv_zvfh -mabi=lp64 -O1" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c index 664b5145997..92cd8ebb8d0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-error-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d --param=riscv-vector-abi -Wno-implicit-function-declaration" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -Wno-implicit-function-declaration" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c index b5b3c5d9c2f..d6111710856 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return-run.c @@ -1,5 +1,5 @@ /* { dg-do run { target { riscv_v } } } */ -/* { dg-options "-O1 --param=riscv-vector-abi" } */ +/* { dg-options "-O1" } */ /* { dg-additional-sources abi-call-return.c } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c index ac19cc6bd18..00f2c2c9260 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-return.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c index 16c7687f03d..9b3faf8d2a8 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-call-variant_cc.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gcv -mabi=lp64d -O1 --param=riscv-vector-abi" } */ +/* { dg-options "-march=rv64gcv -mabi=lp64d -O1" } */ #include "riscv_vector.h" diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c index 06b3647e9d6..dc9a9bb8be9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O1 -march=rv64gczve32x -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c index 5a6ab81bbf9..552f9e77163 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-fixed-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-vector-abi --param=riscv-autovec-preference=fixed-vlmax" } */ +/* { dg-options "-O1 -march=rv64gcv_zvl4096b -mabi=lp64d --param=riscv-autovec-preference=fixed-vlmax" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c index c6aa5e13593..9ed72a6abe2 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-save-restore.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c index 386916a23ac..dedcef9b353 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1-zcmp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c index bc1f9ff60bb..13e33285781 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-1.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c index 96a3e717636..39c8c007d3f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-save-restore.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi -msave-restore" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d -msave-restore" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c index b3a8141a81c..14fb2c400a4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2-zcmp.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d --param=riscv-vector-abi -fno-shrink-wrap-separate" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh_zca_zcmp -mabi=lp64d -fno-shrink-wrap-separate" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c index 8b6537ba9de..a9f3855b413 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/abi-callee-saved-2.c @@ -1,5 +1,5 @@ /* { dg-do compile } */ -/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d --param=riscv-vector-abi" } */ +/* { dg-options "-O1 -march=rv64gcv_zfh -mabi=lp64d" } */ /* { dg-final { check-function-bodies "**" "" } } */ #include diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c index 5f07b893fb1..a971103c3ee 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-69.c @@ -24,8 +24,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, return result; } -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 1 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c index 44f985b767e..b1c51924567 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-70.c @@ -21,8 +21,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, return result; } -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 1 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c index 694f3aa2d96..c3170556d2f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/float-point-dynamic-frm-71.c @@ -21,8 +21,8 @@ test_float_point_dynamic_frm (vfloat32m1_t op1, vfloat32m1_t op2, return result; } -/* { dg-final { scan-assembler-times {vfadd\.v[vf]\s+v[0-9]+,\s*v[0-9]+,\s*[fav]+[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vfadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 3 } } */ /* { dg-final { scan-assembler-times {frrm\s+[axs][0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 1 } } */ -/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 2 } } */ +/* { dg-final { scan-assembler-times {fsrm\s+[axs][0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {fsrmi\s+[01234]} 3 } } */ /* { dg-final { scan-assembler-not {fsrmi\s+[axs][0-9]+,\s*[01234]} } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c index 9563c8d27fa..504d61d410e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/misc_vreinterpret_vbool_vint.c @@ -114,6 +114,4 @@ vuint64m1_t test_vreinterpret_v_b1_vuint64m1 (vbool1_t src) { return __riscv_vreinterpret_v_b1_u64m1 (src); } -/* { dg-final { scan-assembler-times {vlm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */ -/* { dg-final { scan-assembler-times {vsm\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 20 } } */ -/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 8 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 28 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c index 05e6e43b1e5..6cf1dfd78c6 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vadd.c @@ -4,9 +4,7 @@ #include "overloaded_vadd.h" /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma} 4 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 8 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 6 } } */ -/* { dg-final { scan-assembler-times {vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[ax][0-9]+} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c index dd183597a42..970b8d96dfa 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vfadd.c @@ -3,9 +3,7 @@ #include "overloaded_vfadd.h" -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma} 16 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*ma} 4 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 8 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c index 1bd091b7a5b..c42e38ec19f 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vget_vset.c @@ -3,5 +3,4 @@ #include "overloaded_vget_vset.h" -/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 14 } } */ -/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 13 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c index 3bec715a955..91eb1066447 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vloxseg2ei16.c @@ -4,7 +4,6 @@ #include "overloaded_vloxseg2ei16.h" /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*ma} 2 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*ma} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*mu} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c index d5d80c005a7..42ef5c33aae 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv32_vreinterpret.c @@ -3,8 +3,4 @@ #include "overloaded_vreinterpret.h" -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma} 2 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma} 1 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c index 390e2e525c9..382d8d2d181 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vadd.c @@ -3,9 +3,7 @@ #include "overloaded_vadd.h" /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*ma} 4 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m1,\s*ta,\s*ma} 8 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*ta,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e8,\s*m1,\s*tu,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vadd\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} 6 } } */ -/* { dg-final { scan-assembler-times {vadd\.vx\s+v[0-9]+,\s*v[0-9]+,\s*[ax][0-9]+} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c index bf540c68f17..cf59130f133 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vfadd.c @@ -2,9 +2,7 @@ #include "overloaded_vfadd.h" -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf4,\s*ta,\s*ma} 16 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*ma} 4 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf8,\s*ta,\s*ma} 8 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e16,\s*mf4,\s*ta,\s*mu} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c index a6a05c1688b..d4f573d659e 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vget_vset.c @@ -2,5 +2,4 @@ #include "overloaded_vget_vset.h" -/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 14 } } */ -/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([ax][0-9]+\)} 13 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c index d0b8be018b6..3261f72a2a4 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vloxseg2ei16.c @@ -3,8 +3,6 @@ #include "overloaded_vloxseg2ei16.h" /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*ma} 2 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 4 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*ma} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*tu,\s*mu} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[ax][0-9]+,\s*e64,\s*m4,\s*ta,\s*mu} 1 } } */ /* { dg-final { scan-assembler-times {vloxseg2ei16\.v\s+v[0-9]+,\s*\([ax][0-9]+\),\s*v[0-9]+} 6 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c index 57ec538c78a..06b0ab932f1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/overloaded_rv64_vreinterpret.c @@ -2,8 +2,4 @@ #include "overloaded_vreinterpret.h" -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m4,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*m2,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e8,\s*mf2,\s*ta,\s*ma} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e16,\s*mf2,\s*ta,\s*ma} 2 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[ax][0-9]+,\s*zero,\s*e32,\s*mf2,\s*ta,\s*ma} 1 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c index d37857e24ab..d5a839a2ce9 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-10.c @@ -11,13 +11,16 @@ void f (char*); ** addi\tsp,sp,-32 ** sw\tra,4\(sp\) ** sw\ts0,0\(sp\) -** addi\ts0,sp,8 +** addi\ts0,sp,8 ** csrr\tt0,vlenb ** sub\tsp,sp,t0 +** vs1r.v\tv1,0\(sp\) +** sub\tsp,sp,t0 +** vs1r.v\tv2,0\(sp\) ** ... -** addi\ta2,a2,15 -** andi\ta2,a2,-8 -** sub\tsp,sp,a2 +** addi\ta1,a1,15 +** andi\ta1,a1,-8 +** sub\tsp,sp,a1 ** ... ** lw\tra,4\(sp\) ** lw\ts0,0\(sp\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c index d9362ecd41b..cbfe9210514 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-11.c @@ -9,21 +9,22 @@ void fn3 (char*); /* ** stack_save_restore_2: -** call\tt0,__riscv_save_1 +** call\tt0,__riscv_save_0 ** csrr\tt0,vlenb -** slli\tt1,t0,1 -** sub\tsp,sp,t1 -** li\tt0,-8192 -** addi\tt0,t0,192 -** add\tsp,sp,t0 +** sub\tsp,sp,t0 +** vs1r.v\tv1,0\(sp\) ** ... ** csrr\tt0,vlenb -** slli\tt1,t0,1 +** slli\tt1,t0,2 +** sub\tt1,t1,t0 ** add\tsp,sp,t1 ** li\tt0,8192 ** addi\tt0,t0,-192 ** add\tsp,sp,t0 -** tail\t__riscv_restore_1 +** ... +** vl1re64.v\tv1,0\(sp\) +** add\tsp,sp,t0 +** tail\t__riscv_restore_0 */ int stack_save_restore_2 (float a1, float a2, float a3, float a4, float a5, float a6, float a7, float a8, diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c index ec673575b4b..7e5758b18d1 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/spill-9.c @@ -11,14 +11,14 @@ void f (char*); ** addi\tsp,sp,-48 ** sw\tra,12\(sp\) ** sw\ts0,8\(sp\) -** addi\ts0,sp,16 +** addi\ts0,sp,16 ** csrr\tt0,vlenb -** slli\tt1,t0,1 -** sub\tsp,sp,t1 +** sub\tsp,sp,t0 +** vs1r.v\tv1,0\(sp\) ** ... -** addi\ta2,a2,23 -** andi\ta2,a2,-16 -** sub\tsp,sp,a2 +** addi\ta0,sp,15 +** andi\ta0,a0,-16 +** call\tf ** ... ** lw\tra,12\(sp\) ** lw\ts0,8\(sp\) diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c index 893e5a3c6db..43d14972ed3 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/tuple_vundefined.c @@ -69,5 +69,5 @@ test_vundefined_u64m4x2 () return __riscv_vundefined_u64m4x2 (); } -/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 18 } } */ -/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 28 } } */ +/* { dg-final { scan-assembler-times {vse[0-9]+\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 0 } } */ +/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 0 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c index 79509903326..0fc8c3450f0 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vcreate.c @@ -254,7 +254,6 @@ test_vcreate_v_i64m2x4 (vint64m2_t v0, vint64m2_t v1, vint64m2_t v2, return __riscv_vcreate_v_i64m2x4 (v0, v1, v2, v3); } -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 7 } } */ -/* { dg-final { scan-assembler-times {v[ls]e16\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 70 } } */ -/* { dg-final { scan-assembler-times {vl[0-9]+re[0-9]+\.v\s+v[0-9]+,\s*0\([0-9a-x]+\)} 110 } } */ -/* { dg-final { scan-assembler-times {vs[0-9]+r\.v\s+v[0-9]+,\s*0\([a-x0-9]+\)} 81 } } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 24 } } */ +/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 12 } } */ +/* { dg-final { scan-assembler-times {vmv4r.v\s+v[0-9]+,\s*v[0-9]+} 16 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c index 501d98c5897..42537290d70 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vlmul_ext-1.c @@ -11,4 +11,5 @@ vint64m8_t test_vlmul_ext_v_i64m2_i64m8(vint64m2_t op1) { return __riscv_vlmul_ext_v_i64m2_i64m8(op1); } -/* { dg-final { scan-assembler-times {vs8r.v\s+[,\sa-x0-9()]+} 2} } */ +/* { dg-final { scan-assembler-times {vmv1r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ +/* { dg-final { scan-assembler-times {vmv2r.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c index 1d82cc8de2d..8402702a21c 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfh-over-zvfhmin.c @@ -72,17 +72,7 @@ vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) { /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 3 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 8 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 2 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 2 } } */ -/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 7 } } */ -/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */ -/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ -/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ -/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ -/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 1 } } */ -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 3 } } */ -/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([0-9ax]+\)} 2 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c index 193902d0e5f..4513815bacc 100644 --- a/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/zvfhmin-intrinsic.c @@ -187,20 +187,9 @@ vfloat16m4_t test_vget_v_f16m8_f16m4(vfloat16m8_t src, size_t index) { /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]} 2 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]} 1 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf4,\s*t[au],\s*m[au]} 18 } } */ -/* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*mf2,\s*t[au],\s*m[au]} 6 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m2,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m4,\s*t[au],\s*m[au]} 1 } } */ /* { dg-final { scan-assembler-times {vsetvli\s+[a-x0-9]+,\s*zero,\s*e16,\s*m8,\s*t[au],\s*m[au]} 5 } } */ /* { dg-final { scan-assembler-times {vfwcvt\.f\.f\.v\s+v[0-9]+,\s*v[0-9]+} 5 } } */ /* { dg-final { scan-assembler-times {vfncvt\.f\.f\.w\s+v[0-9]+,\s*v[0-9]+} 5 } } */ -/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ -/* { dg-final { scan-assembler-times {vse16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 15 } } */ -/* { dg-final { scan-assembler-times {vl1re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 7 } } */ -/* { dg-final { scan-assembler-times {vl2re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ -/* { dg-final { scan-assembler-times {vl8re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */ -/* { dg-final { scan-assembler-times {vl4re16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 6 } } */ -/* { dg-final { scan-assembler-times {vs1r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ -/* { dg-final { scan-assembler-times {vs2r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ -/* { dg-final { scan-assembler-times {vs4r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 5 } } */ -/* { dg-final { scan-assembler-times {vs8r\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 13 } } */ +/* { dg-final { scan-assembler-times {vle16\.v\s+v[0-9]+,\s*0\([a-x][0-9]+\)} 2 } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 73360cd3a0d..fcd89ecd0a1 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -11767,13 +11767,11 @@ proc check_vect_support_and_set_flags { } { set dg-do-what-default run } elseif [istarget riscv*-*-*] { if [check_effective_target_riscv_v] { - lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi" set dg-do-what-default run } else { foreach item [add_options_for_riscv_v ""] { lappend DEFAULT_VECTCFLAGS $item } - lappend DEFAULT_VECTCFLAGS "--param" "riscv-vector-abi" set dg-do-what-default compile } } elseif [istarget loongarch*-*-*] {