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Thu, 25 Jan 2024 04:05:15 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40PA5E0p005058; Thu, 25 Jan 2024 04:05:14 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v3 1/5] arm64: dts: ti: k3-j784s4-main: Fix mux-reg-masks in serdes_ln_ctrl Date: Thu, 25 Jan 2024 15:34:57 +0530 Message-ID: <20240125100501.4137977-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125100501.4137977-1-c-vankar@ti.com> References: <20240125100501.4137977-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789056534700357122 X-GMAIL-MSGID: 1789056534700357122 Change offset in mux-reg-masks property for serdes_ln_ctrl node since reg-mux property is used in compatible. Fixes: 2765149273f4 ("mux: mmio: use reg property when parent device is not a syscon") Signed-off-by: Chintan Vankar Acked-by: Andrew Davis --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index f2b720ed1e4f..56c8eaad6324 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -52,12 +52,12 @@ serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; reg = <0x00004080 0x30>; #mux-control-cells = <1>; - mux-reg-masks = <0x4080 0x3>, <0x4084 0x3>, /* SERDES0 lane0/1 select */ - <0x4088 0x3>, <0x408c 0x3>, /* SERDES0 lane2/3 select */ - <0x4090 0x3>, <0x4094 0x3>, /* SERDES1 lane0/1 select */ - <0x4098 0x3>, <0x409c 0x3>, /* SERDES1 lane2/3 select */ - <0x40a0 0x3>, <0x40a4 0x3>, /* SERDES2 lane0/1 select */ - <0x40a8 0x3>, <0x40ac 0x3>; /* SERDES2 lane2/3 select */ + mux-reg-masks = <0x0 0x3>, <0x4 0x3>, /* SERDES0 lane0/1 select */ + <0x8 0x3>, <0xc 0x3>, /* SERDES0 lane2/3 select */ + <0x10 0x3>, <0x14 0x3>, /* SERDES1 lane0/1 select */ + <0x18 0x3>, <0x1c 0x3>, /* SERDES1 lane2/3 select */ + <0x20 0x3>, <0x24 0x3>, /* SERDES2 lane0/1 select */ + <0x28 0x3>, <0x2c 0x3>; /* SERDES2 lane2/3 select */ idle-states = , , , From patchwork Thu Jan 25 10:04:58 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chintan Vankar X-Patchwork-Id: 191960 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1545161dyi; Thu, 25 Jan 2024 02:32:29 -0800 (PST) X-Google-Smtp-Source: AGHT+IHf2xov2hKeocNUE8xzy5kwZFH4NzFU8S15ziIPTKN+LbXQEwuxRxOmmVlwYxYeT/tf/zKf X-Received: by 2002:a17:90b:3743:b0:28c:7ca2:ee49 with SMTP id ne3-20020a17090b374300b0028c7ca2ee49mr477354pjb.54.1706178749427; Thu, 25 Jan 2024 02:32:29 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706178749; cv=pass; d=google.com; s=arc-20160816; b=m5MApA4LtN2kqfBFtdoWrvIwjhh9FFVeba7M8cT3Da5GILOCBg0tMAmjO9QxD42gsL d2aw9X/kcU8VFymFR7mvFWQ0Pq+17S3F6gpe1SrhMu5MCNEJBVBa2RYVirf4BCibvZ+D Hidih7LxwYsoPbJvP2G4raVVUMKUT0kmn5Jkd+T/616WU8DVjKzi3CJ3ZQqweNyUeEVr DwjtOB1FPYFhd9KguvscZe2TWJQl/0gFih7rIRC174Nqu99OJtDE0ogUeu5eQwVBRfjo BwQZyZI+GdlkP6V1c2v5eLu2N9tx8dZ9Pwy+EW26UK8yM66//3L0pO8buuH/REaNvQQR JhnQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=zSS6F8ZL7Y/5nL1xWFoL6nxBS7JhsnNIJXNGpKQAMg0=; fh=X4X6D3rd4uA675ozTYmPIgcx6qeLvqste3STz75rKhk=; b=ZgcfKx+O7xoXAPna3/I6tsbvI2hDo7OKhVgjK2pY32H0BjAN8857nwh4SBM5feriZu YVv20f9PRYOuyG1dHg6jcqXe2ApVn7k1c3vump/RXDJlxRhKfHAZYiFW0cbedprIGhGa F2ruJVD7OfQWaIrMrSOzt2lM/JXI7RruPnKNz3SVlaSOyL5ezODU1ESjOqSflU8VT4/4 fVEoq8xzOc/AYWR/OA1oYEfuLeJUyelBRG/8NC8OSSXUFxUJsuvOclpIUVTMXc2BwPPv XDMDKeiBQYC5LpWf1FVYH4FKGYWX9IAGwNi2R+661kGlx5DdkJxUOUnvYnDFNn4T86AG AYlA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=yRqAt+1U; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-38361-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-38361-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Thu, 25 Jan 2024 04:05:16 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40PA5FYo005082; Thu, 25 Jan 2024 04:05:16 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v3 2/5] arm64: dts: ti: k3-j784s4-main: Add CPSW2G and CPSW9G nodes Date: Thu, 25 Jan 2024 15:34:58 +0530 Message-ID: <20240125100501.4137977-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125100501.4137977-1-c-vankar@ti.com> References: <20240125100501.4137977-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789058087952854407 X-GMAIL-MSGID: 1789058087952854407 From: Siddharth Vadapalli J784S4 SoC has a 9 port Ethernet Switch instance with 8 external ports and 1 host port, referred to as CPSW9G. Add device-tree nodes for CPSW9G and disable it by default. Device-tree overlays will be used to enable it. Add device-tree nodes for Main CPSW2G nodes and disable it by default. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi | 182 +++++++++++++++++++++ 1 file changed, 182 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi index 56c8eaad6324..89578b449450 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j784s4-main.dtsi @@ -47,6 +47,19 @@ scm_conf: bus@100000 { #address-cells = <1>; #size-cells = <1>; ranges = <0x00 0x00 0x00100000 0x1c000>; + + cpsw1_phy_gmii_sel: phy@4034 { + compatible = "ti,am654-phy-gmii-sel"; + reg = <0x4034 0x4>; + #phy-cells = <1>; + }; + + cpsw0_phy_gmii_sel: phy@4044 { + compatible = "ti,j784s4-cpsw9g-phy-gmii-sel"; + ti,qsgmii-main-ports = <7>, <7>; + reg = <0x4044 0x20>; + #phy-cells = <1>; + }; serdes_ln_ctrl: mux-controller@4080 { compatible = "reg-mux"; @@ -1242,6 +1255,175 @@ cpts@310d0000 { }; }; + main_cpsw0: ethernet@c000000 { + compatible = "ti,j784s4-cpswxg-nuss"; + reg = <0x00 0xc000000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x00 0x00 0xc000000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + power-domains = <&k3_pds 64 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xca00>, + <&main_udmap 0xca01>, + <&main_udmap 0xca02>, + <&main_udmap 0xca03>, + <&main_udmap 0xca04>, + <&main_udmap 0xca05>, + <&main_udmap 0xca06>, + <&main_udmap 0xca07>, + <&main_udmap 0x4a00>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw0_port1: port@1 { + reg = <1>; + label = "port1"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port2: port@2 { + reg = <2>; + label = "port2"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port3: port@3 { + reg = <3>; + label = "port3"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port4: port@4 { + reg = <4>; + label = "port4"; + ti,mac-only; + status = "disabled"; + }; + + main_cpsw0_port5: port@5 { + reg = <5>; + label = "port5"; + status = "disabled"; + }; + + main_cpsw0_port6: port@6 { + reg = <6>; + label = "port6"; + status = "disabled"; + }; + + main_cpsw0_port7: port@7 { + reg = <7>; + label = "port7"; + status = "disabled"; + }; + + main_cpsw0_port8: port@8 { + reg = <8>; + label = "port8"; + status = "disabled"; + }; + }; + + main_cpsw0_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio","ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 64 0>; + clock-names = "fck"; + bus_freq = <1000000>; + status = "disabled"; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 64 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + + main_cpsw1: ethernet@c200000 { + compatible = "ti,j721e-cpsw-nuss"; + #address-cells = <2>; + #size-cells = <2>; + reg = <0x00 0xc200000 0x00 0x200000>; + reg-names = "cpsw_nuss"; + ranges = <0x00 0x00 0x00 0xc200000 0x00 0x200000>; + dma-coherent; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + power-domains = <&k3_pds 62 TI_SCI_PD_EXCLUSIVE>; + + dmas = <&main_udmap 0xc640>, + <&main_udmap 0xc641>, + <&main_udmap 0xc642>, + <&main_udmap 0xc643>, + <&main_udmap 0xc644>, + <&main_udmap 0xc645>, + <&main_udmap 0xc646>, + <&main_udmap 0xc647>, + <&main_udmap 0x4640>; + dma-names = "tx0", "tx1", "tx2", "tx3", + "tx4", "tx5", "tx6", "tx7", + "rx"; + + status = "disabled"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + main_cpsw1_port1: port@1 { + reg = <1>; + label = "port1"; + phys = <&cpsw1_phy_gmii_sel 1>; + ti,mac-only; + status = "disabled"; + }; + }; + + main_cpsw1_mdio: mdio@f00 { + compatible = "ti,cpsw-mdio", "ti,davinci_mdio"; + reg = <0x00 0xf00 0x00 0x100>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&k3_clks 62 0>; + clock-names = "fck"; + bus_freq = <1000000>; + }; + + cpts@3d000 { + compatible = "ti,am65-cpts"; + reg = <0x00 0x3d000 0x00 0x400>; + clocks = <&k3_clks 62 3>; + clock-names = "cpts"; + interrupts-extended = <&gic500 GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "cpts"; + ti,cpts-ext-ts-inputs = <4>; + ti,cpts-periodic-outputs = <2>; + }; + }; + main_mcan0: can@2701000 { compatible = "bosch,m_can"; reg = <0x00 0x02701000 0x00 0x200>, From patchwork Thu Jan 25 10:04:59 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chintan Vankar X-Patchwork-Id: 191939 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1534062dyi; Thu, 25 Jan 2024 02:06:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IHUNnQwjfslo//DfU9jmk+uqc3T0BJZ2necN1BRE7BVd71QM4xOXrIJl5EjGerHrjYeNhsR X-Received: by 2002:a05:620a:51d6:b0:781:d911:7869 with SMTP id cx22-20020a05620a51d600b00781d9117869mr802380qkb.111.1706177204554; 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Thu, 25 Jan 2024 04:05:18 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40PA5H4H005109; Thu, 25 Jan 2024 04:05:17 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Jayesh Choudhary , Chintan Vankar Subject: [PATCH v3 3/5] arm64: dts: ti: k3-j784s4: Add Main CPSW2G node Date: Thu, 25 Jan 2024 15:34:59 +0530 Message-ID: <20240125100501.4137977-4-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125100501.4137977-1-c-vankar@ti.com> References: <20240125100501.4137977-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789056468604976585 X-GMAIL-MSGID: 1789056468604976585 From: Siddharth Vadapalli Add the device-tree nodes for the Main CPSW2G instance and enable it. Signed-off-by: Siddharth Vadapalli Signed-off-by: Jayesh Choudhary Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 47 ++++++++++++++++++++++++ 1 file changed, 47 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index f34b92acc56d..826367ffa3f2 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -279,6 +279,29 @@ &wkup_gpio0 { &main_pmx0 { bootph-all; + main_cpsw2g_default_pins: main-cpsw2g-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ + J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ + J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ + J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ + J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ + J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ + J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ + J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ + J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ + J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ + J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ + J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ + >; + }; + + main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ + J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ + >; + }; main_uart8_pins_default: main-uart8-default-pins { bootph-all; pinctrl-single,pins = < @@ -808,6 +831,30 @@ &mcu_cpsw_port1 { phy-handle = <&mcu_phy0>; }; +&main_cpsw1 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_default_pins>; +}; + +&main_cpsw1_mdio { + pinctrl-names = "default"; + pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; + + main_cpsw1_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&main_cpsw1_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&main_cpsw1_phy0>; +}; + &mailbox0_cluster0 { status = "okay"; interrupts = <436>; From patchwork Thu Jan 25 10:05:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chintan Vankar X-Patchwork-Id: 191940 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1534245dyi; Thu, 25 Jan 2024 02:07:02 -0800 (PST) X-Google-Smtp-Source: AGHT+IGOnkdzENwP7KFFnRELn+sJ9TKUc+PQNPYb0EWNRMoSBnGc/bMV+fVFwv5opPYuSvCuyuF7 X-Received: by 2002:a05:6808:11ce:b0:3bd:62e3:b448 with SMTP id p14-20020a05680811ce00b003bd62e3b448mr521407oiv.18.1706177222337; Thu, 25 Jan 2024 02:07:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706177222; cv=pass; d=google.com; s=arc-20160816; b=RN1dcl1CsgDphsPItBHRIJ1qQ0KIjcBnlK2C4z+gc3rDDje6v3nO0Rmx37to6bexQX fELoyrVjy3ftKaNIbD6zoHcOLnKPmj4E9jGRe4vErBx3HXlFsg9o09qN2cJgFGhlRh1l wbYu2Gejk07Cgcf5qGzSkmMmy6jxt+txWOEQ1fSPg68eHsaMJGlDe82CEwdYyPa7f/QC ZV9RpWqSuUbIdoXmddQEInx8Zd4OI/XX34irGf8/Y7ffARfqUxdBceBo5DOeBT1BxZIr 8HP8ArUeiKtJgRgDRfgUHaUxGhQchllwhOGrGonbupwIjGcr30lyBrSICJoo7mmuxxYt TyFA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=w7WGS3z4ve7nKml2P632gkDGyPcQ4rkQklenWrI7xYk=; fh=X4X6D3rd4uA675ozTYmPIgcx6qeLvqste3STz75rKhk=; b=ft8tlumcDUVKrSTKADoh47Yp6C60aIrQRtkauMwaQDmFbY6HP3PxDhkUHBeY1xcWKk Ad4S+Wr1WLY7kEt8OxbRo962prb7459DI4TNyTMMvTxbRbg/NWw+2DtaCV5e8pctE+3J dvh7snWuBiIN2ugxbvX8PsueKuTx3VLc4z/43b54SfENaeng8JpZK7Ig93hbcaerQWd6 s+hatyunL/6CB5PsV7NVvCOmWDGrssAb353Rl9EeWaezCXCzPSJ5ItUx2CqsLnj3+7V7 sqy9mL9fQ6RZO2q/5MKe2Il0YRYnZa0kITdWpQo8NvFyMPryK9Ic0mb/n9DC8h/GwdUz OkzQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="l/XYg89P"; arc=pass (i=1 spf=pass spfdomain=ti.com dkim=pass dkdomain=ti.com dmarc=pass fromdomain=ti.com); spf=pass (google.com: domain of linux-kernel+bounces-38358-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-38358-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Thu, 25 Jan 2024 04:05:19 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40PA5IAM005132; Thu, 25 Jan 2024 04:05:19 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v3 4/5] arm64: dts: ti: k3-j784s4: Add overlay to enable QSGMII mode with CPSW9G Date: Thu, 25 Jan 2024 15:35:00 +0530 Message-ID: <20240125100501.4137977-5-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125100501.4137977-1-c-vankar@ti.com> References: <20240125100501.4137977-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789056487359025409 X-GMAIL-MSGID: 1789056487359025409 From: Siddharth Vadapalli The J7 Quad Port Add-On Ethernet Card for J784S4 EVM supports QSGMII mode. Use the overlay to configure CPSW9G ports in QSGMII mode with the Add-On Ethernet Card connected to the ENET Expansion 1 slot on the EVM. Add support to reset the PHY from kernel by using gpio-hog and gpio-reset. Add aliases for CPSW9G ports to enable kernel to fetch MAC Addresses directly from U-Boot. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 7 +- .../ti/k3-j784s4-evm-quad-port-eth-exp1.dtso | 146 ++++++++++++++++++ 2 files changed, 152 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 52c1dc910308..836bc197d932 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -81,6 +81,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo # Boards with J784s4 SoC dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ @@ -109,6 +110,8 @@ k3-j721e-evm-pcie0-ep-dtbs := k3-j721e-common-proc-board.dtb \ k3-j721e-evm-pcie0-ep.dtbo k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo +k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -121,7 +124,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-sdcard.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ - k3-j721s2-evm-pcie1-ep.dtb + k3-j721s2-evm-pcie1-ep.dtb \ + k3-j784s4-evm-quad-port-eth-exp1.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ @@ -132,3 +136,4 @@ DTC_FLAGS_k3-am642-tqma64xxl-mbax4xxl += -@ DTC_FLAGS_k3-am6548-iot2050-advanced-m2 += -@ DTC_FLAGS_k3-j721e-common-proc-board += -@ DTC_FLAGS_k3-j721s2-common-proc-board += -@ +DTC_FLAGS_k3-j784s4-evm += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso new file mode 100644 index 000000000000..60853adec9e3 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-quad-port-eth-exp1.dtso @@ -0,0 +1,146 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in QSGMII mode using J7 Quad Port ETH EXP Add-On Ethernet Card with + * J784S4 EVM. The Add-On Ethernet Card has to be connected to ENET Expansion 1 slot on the + * board. + * + * Product Datasheet: https://www.ti.com/lit/ug/spruj74/spruj74.pdf + * + * Link to QSGMII Daughtercard: https://www.ti.com/tool/J721EXENETXPANEVM + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-pinctrl.h" +#include "k3-serdes.h" + +&{/} { + aliases { + ethernet1 = "/bus@100000/ethernet@c000000/ethernet-ports/port@5"; + ethernet2 = "/bus@100000/ethernet@c000000/ethernet-ports/port@6"; + ethernet3 = "/bus@100000/ethernet@c000000/ethernet-ports/port@7"; + ethernet4 = "/bus@100000/ethernet@c000000/ethernet-ports/port@8"; + }; +}; + +&main_cpsw0 { + status = "okay"; +}; + +&main_cpsw0_port5 { + status = "okay"; + phy-handle = <&cpsw9g_phy1>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port6 { + status = "okay"; + phy-handle = <&cpsw9g_phy2>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 6>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port7 { + status = "okay"; + phy-handle = <&cpsw9g_phy0>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 7>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_port8 { + status = "okay"; + phy-handle = <&cpsw9g_phy3>; + phy-mode = "qsgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 8>, <&serdes2_qsgmii_link>; + phy-names = "mac", "serdes"; +}; + +&main_cpsw0_mdio { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mdio0_default_pins>; + bus_freq = <1000000>; + reset-gpios = <&exp2 17 GPIO_ACTIVE_LOW>; + reset-post-delay-us = <120000>; + #address-cells = <1>; + #size-cells = <0>; + + cpsw9g_phy0: ethernet-phy@16 { + reg = <16>; + }; + cpsw9g_phy1: ethernet-phy@17 { + reg = <17>; + }; + cpsw9g_phy2: ethernet-phy@18 { + reg = <18>; + }; + cpsw9g_phy3: ethernet-phy@19 { + reg = <19>; + }; +}; + +&exp2 { + /* Power-up ENET1 EXPANDER PHY. */ + qsgmii-line-hog { + gpio-hog; + gpios = <16 GPIO_ACTIVE_HIGH>; + output-low; + }; + + /* Toggle MUX2 for MDIO lines */ + mux-sel-hog { + gpio-hog; + gpios = <13 GPIO_ACTIVE_HIGH>, <14 GPIO_ACTIVE_HIGH>, <15 GPIO_ACTIVE_HIGH>; + output-high; + }; +}; + +&main_pmx0 { + mdio0_default_pins: mdio0-default-pins { + pinctrl-single,pins = < + J784S4_IOPAD(0x05c, PIN_INPUT, 4) /* (AC36) MCASP2_AXR0.MDIO1_MDIO */ + J784S4_IOPAD(0x058, PIN_INPUT, 4) /* (AE37) MCASP2_AFSX.MDIO1_MDC */ + >; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +}; + +&serdes_wiz2 { + status = "okay"; +}; + +&serdes2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + serdes2_qsgmii_link: phy@0 { + reg = <2>; + cdns,num-lanes = <1>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>; + }; +}; From patchwork Thu Jan 25 10:05:01 2024 Content-Type: text/plain; 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Thu, 25 Jan 2024 04:05:21 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 40PA5KZW056416; Thu, 25 Jan 2024 04:05:20 -0600 From: Chintan Vankar To: Andrew Davis , Peter Rosin , Greg Kroah-Hartman , Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , , , , Chintan Vankar Subject: [PATCH v3 5/5] arm64: dts: ti: k3-j784s4: Add overlay for dual port USXGMII mode Date: Thu, 25 Jan 2024 15:35:01 +0530 Message-ID: <20240125100501.4137977-6-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240125100501.4137977-1-c-vankar@ti.com> References: <20240125100501.4137977-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789056497845953223 X-GMAIL-MSGID: 1789056497845953223 From: Siddharth Vadapalli The CPSW9G instance of the CPSW Ethernet Switch supports USXGMII mode with MAC Ports 1 and 2 of the instance, which are connected to ENET Expansion 1 and ENET Expansion 2 slots on the EVM respectively, through the Serdes2 instance of the SERDES. Enable CPSW9G MAC Ports 1 and 2 in fixed-link configuration USXGMII mode at 5 Gbps each. Signed-off-by: Siddharth Vadapalli Signed-off-by: Chintan Vankar --- arch/arm64/boot/dts/ti/Makefile | 6 +- .../ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso | 73 +++++++++++++++++++ 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile index 836bc197d932..97be325235dc 100644 --- a/arch/arm64/boot/dts/ti/Makefile +++ b/arch/arm64/boot/dts/ti/Makefile @@ -82,6 +82,7 @@ dtb-$(CONFIG_ARCH_K3) += k3-j721s2-evm-pcie1-ep.dtbo dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm.dtb dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-quad-port-eth-exp1.dtbo +dtb-$(CONFIG_ARCH_K3) += k3-j784s4-evm-usxgmii-exp1-exp2.dtbo # Build time test only, enabled by CONFIG_OF_ALL_DTBS k3-am625-beagleplay-csi2-ov5640-dtbs := k3-am625-beagleplay.dtb \ @@ -112,6 +113,8 @@ k3-j721s2-evm-pcie1-ep-dtbs := k3-j721s2-common-proc-board.dtb \ k3-j721s2-evm-pcie1-ep.dtbo k3-j784s4-evm-quad-port-eth-exp1-dtbs := k3-j784s4-evm.dtb \ k3-j784s4-evm-quad-port-eth-exp1.dtbo +k3-j784s4-evm-usxgmii-exp1-exp2.dtbs := k3-j784s4-evm.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtbo dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am625-beagleplay-csi2-tevi-ov5640.dtb \ k3-am625-sk-csi2-imx219.dtb \ @@ -125,7 +128,8 @@ dtb- += k3-am625-beagleplay-csi2-ov5640.dtb \ k3-am642-tqma64xxl-mbax4xxl-wlan.dtb \ k3-j721e-evm-pcie0-ep.dtb \ k3-j721s2-evm-pcie1-ep.dtb \ - k3-j784s4-evm-quad-port-eth-exp1.dtb + k3-j784s4-evm-quad-port-eth-exp1.dtb \ + k3-j784s4-evm-usxgmii-exp1-exp2.dtb # Enable support for device-tree overlays DTC_FLAGS_k3-am625-beagleplay += -@ diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso new file mode 100644 index 000000000000..e51381f0a265 --- /dev/null +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm-usxgmii-exp1-exp2.dtso @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ +/** + * DT Overlay for CPSW9G in dual port fixed-link USXGMII mode using ENET-1 + * and ENET-2 Expansion slots of J784S4 EVM. + * + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ + */ + +/dts-v1/; +/plugin/; + +#include +#include +#include + +#include "k3-serdes.h" + +&main_cpsw0 { + status = "okay"; + pinctrl-names = "default"; +}; + +&main_cpsw0_port1 { + status = "okay"; + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 1>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&main_cpsw0_port2 { + status = "okay"; + phy-mode = "usxgmii"; + mac-address = [00 00 00 00 00 00]; + phys = <&cpsw0_phy_gmii_sel 2>, <&serdes2_usxgmii_link>; + phy-names = "mac", "serdes"; + fixed-link { + speed = <5000>; + full-duplex; + }; +}; + +&serdes_wiz2 { + status = "okay"; + assigned-clock-parents = <&k3_clks 406 9>; /* Use 156.25 MHz clock for USXGMII */ +}; + +&serdes2 { + status = "okay"; + #address-cells = <1>; + #size-cells = <0>; + + serdes2_usxgmii_link: phy@2 { + reg = <2>; + cdns,num-lanes = <2>; + #phy-cells = <0>; + cdns,phy-type = ; + resets = <&serdes_wiz2 3>, <&serdes_wiz2 4>; + }; +}; + +&serdes_ln_ctrl { + idle-states = , , + , , + , , + , , + , , + , ; +};