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Wed, 24 Jan 2024 12:30:30 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id r15-20020a05600c458f00b0040d62f89381sm174073wmo.35.2024.01.24.12.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 12:30:30 -0800 (PST) From: Alexey Charkov Date: Thu, 25 Jan 2024 00:30:04 +0400 Subject: [PATCH 1/4] arm64: dts: rockchip: add rfkill node for M.2 Key E WiFi on rock-5b Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-rk-dts-additions-v1-1-5879275db36f@gmail.com> References: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> In-Reply-To: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706128223; l=1054; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=WL2tRjg8ew8DqItHe5VMXx4XizhzUARbkSBb7xc+JjU=; b=zUPpF+OtMc0JFVxYHKKr0Q3E8J3khN2xHdZhW5GT1e0hcSNmOdPXmJJg0T/SqCHyAK1DRPw26 ni6pTFSKc+TBft41+kwwrqfotSizXxL3GtEJwgKSxcEx/hSWQEW6UsV X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789005171395042061 X-GMAIL-MSGID: 1789005171395042061 By default the GPIO pin that connects to the WiFi enable signal inside the M.2 Key E slot is driven low, resulting in impossibility to connect to any network. Add a DT node to expose it as an RFKILL device, which lets the WiFi driver or userspace toggle it as required. Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index a0e303c3a1dc..9b7bf6cec8bd 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -58,6 +58,13 @@ fan: pwm-fan { #cooling-cells = <2>; }; + rfkill { + compatible = "rfkill-gpio"; + label = "rfkill-pcie-wlan"; + radio-type = "wlan"; + shutdown-gpios = <&gpio4 RK_PA2 GPIO_ACTIVE_HIGH>; + }; + vcc3v3_pcie2x1l0: vcc3v3-pcie2x1l0-regulator { compatible = "regulator-fixed"; enable-active-high; From patchwork Wed Jan 24 20:30:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 191753 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1239169dyi; Wed, 24 Jan 2024 12:31:43 -0800 (PST) X-Google-Smtp-Source: AGHT+IH3B/EeqRo36Hr/35/ZFLe61CNIx8mN07mZOWChKZIXfBSK/pwlvuwk/oG0t2gMCH2kaRlR X-Received: by 2002:a17:906:aaca:b0:a28:7dd0:adb4 with SMTP id kt10-20020a170906aaca00b00a287dd0adb4mr1160774ejb.83.1706128302888; Wed, 24 Jan 2024 12:31:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706128302; cv=pass; d=google.com; s=arc-20160816; b=xMlTRwgcwqQb0kS5yDwswrAZPPTLgPM1jwtoAdYdyvEBjWMFJtacHiqCm4F4szTCfz RTqo7xpgVlUPo0HKuwOvH8RYBbtOtRFmfp9CnzMBPkG9mqj39tNtZfOHJCsn3j8imooR r4fn5xO8bj/DdnVRVjkBdWmLYUWNNuJKA0ZSkU4yYdC6EUExv+fpMz1cTy+wuyo3PndM 3AJrH68LiJMHdx1BEhjQGv+321nWdlPVaBKnRrd9EyUpDXtxJnX83odZHLtB+8ytftlT lTspzRzIQSXoWDzhrDcu/ZDUYgUkaJMlxBY2XfgmAxSXDsEC1qD8i/oYdo8UiPXjNEJB RKjA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=Z3ca0jnd9j+2aNrco01AKV5rkL7ji04a+DuuunuBda4=; fh=e+eZh3cxOiCzk/JVMGKSAEtWws2dQPVeQjAasHSdJOE=; b=yjK9PhNSUZq1NQY9l7EyKTNNm8+omlD53FWwm7/X13sIo7q3a06CeoV9YyBcGgKp79 3W3dOpMFzgDy0io7gqTDENUVWk/ZotHPs70/eO3VwywHaXlyNirN3fX3hdPHSz/MGT6l TCaVib4TWjUydkT/kIrdvjlsKHR+zedLcqOStEuQ7CmJXFcERKEh9F2ziOfonHbzsxH1 KMg4I5hWDIczAKnGQPZxGM7Utc007U/ZCL1ioqp5MH0ryoPpeSGu4qq0iVALebdsEScN Snvx0teID8j74953WIxZCRkQLAs8izlsfUzw1SsUd5LHxdVWQ82b9q+Z16sEvKHM+OEa k+XA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=Dc0cSr1P; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-37650-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-37650-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Wed, 24 Jan 2024 12:30:35 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id r15-20020a05600c458f00b0040d62f89381sm174073wmo.35.2024.01.24.12.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 12:30:35 -0800 (PST) From: Alexey Charkov Date: Thu, 25 Jan 2024 00:30:05 +0400 Subject: [PATCH 2/4] arm64: dts: rockchip: enable built-in thermal monitoring on rk3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-rk-dts-additions-v1-2-5879275db36f@gmail.com> References: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> In-Reply-To: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706128223; l=4885; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=bZ/Ku33h3h7tLZHhbK7X7TnJBS+ojPkPkQBizuVj/J8=; b=i07iNxqPSC1JCmuGjfx9B7DczeuyAJWfhY5fMC/Swk//raeORACzzOzr3C99W4a6z0SHHPHWC 60hFkjtkxMqCao/u1EZTx/FEHcYsXXW7YAUKAi+j7FF3aAH9XTAw6jt X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789005191444058567 X-GMAIL-MSGID: 1789005191444058567 Include thermal zones information in device tree for rk3588 variants Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 165 ++++++++++++++++++++++++++++++ 1 file changed, 165 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 36b1b7acfe6a..131b9eb21398 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "rockchip,rk3588"; @@ -2228,6 +2229,170 @@ tsadc: tsadc@fec00000 { status = "disabled"; }; + thermal_zones: thermal-zones { + /* sensor near the center of the whole chip */ + package_thermal: package-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 0>; + + trips { + package_crit: package-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + /* sensor between A76 cores 0 and 1 */ + bigcore0_thermal: bigcore0-thermal { + polling-delay-passive = <20>; + polling-delay = <0>; + thermal-sensors = <&tsadc 1>; + + trips { + bigcore0_alert0: bigcore0-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore0_alert1: bigcore0-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore0_crit: bigcore0-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map0 { + trip = <&bigcore0_alert1>; + cooling-device = + <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + /* sensor between A76 cores 2 and 3 */ + bigcore2_thermal: bigcore2-thermal { + polling-delay-passive = <20>; + polling-delay = <0>; + thermal-sensors = <&tsadc 2>; + + trips { + bigcore2_alert0: bigcore2-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore2_alert1: bigcore2-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + bigcore2_crit: bigcore2-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map1 { + trip = <&bigcore2_alert1>; + cooling-device = + <&cpu_b2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_b3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + /* sensor between the four A55 cores */ + little_core_thermal: littlecore-thermal { + polling-delay-passive = <20>; + polling-delay = <0>; + thermal-sensors = <&tsadc 3>; + + trips { + littlecore_alert0: littlecore-alert0 { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + littlecore_alert1: littlecore-alert1 { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + littlecore_crit: littlecore-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + cooling-maps { + map2 { + trip = <&littlecore_alert1>; + cooling-device = + <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + contribution = <1024>; + }; + }; + }; + + /* sensor near the PD_CENTER power domain */ + center_thermal: center-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 4>; + + trips { + center_crit: center-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + gpu_thermal: gpu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 5>; + + trips { + gpu_crit: gpu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + + npu_thermal: npu-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsadc 6>; + + trips { + npu_crit: npu-crit { + temperature = <115000>; + hysteresis = <0>; + type = "critical"; + }; + }; + }; + }; + saradc: adc@fec10000 { compatible = "rockchip,rk3588-saradc"; reg = <0x0 0xfec10000 0x0 0x10000>; From patchwork Wed Jan 24 20:30:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 191754 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1239311dyi; Wed, 24 Jan 2024 12:32:00 -0800 (PST) X-Google-Smtp-Source: AGHT+IEABcqao7k0+ZaYNWCv6J7giW5c1TmVNGjlWcgk6Drj7f05I5FzUEKkZFp3lex7q9ItTuJB X-Received: by 2002:aa7:d816:0:b0:559:f2ad:ae4b with SMTP id v22-20020aa7d816000000b00559f2adae4bmr6369edq.35.1706128320041; Wed, 24 Jan 2024 12:32:00 -0800 (PST) ARC-Seal: i=2; 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Wed, 24 Jan 2024 12:30:40 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id r15-20020a05600c458f00b0040d62f89381sm174073wmo.35.2024.01.24.12.30.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 12:30:39 -0800 (PST) From: Alexey Charkov Date: Thu, 25 Jan 2024 00:30:06 +0400 Subject: [PATCH 3/4] arm64: dts: rockchip: enable temperature driven fan control on Rock 5B Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-rk-dts-additions-v1-3-5879275db36f@gmail.com> References: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> In-Reply-To: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706128223; l=1551; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=u4l0RsRj4668NcOaxKO+LZ3qtMcTAwoAKZZ3yHzWIOk=; b=K97GzVwWsCS1pD9bcfThrRGqutRbFk4tSHd9NZbQ0Ca+7A4u8xqC6RR67X2kmk1+K9HW1Hdqk tHPNbAcztwbCANcKaBcaZPMlrOCQljO+X12q73wj75Tqwx/+f/IIn/3 X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789005209661476952 X-GMAIL-MSGID: 1789005209661476952 This enables thermal monitoring on Radxa Rock 5B and links the PWM fan as an active cooling device managed automatically by the thermal subsystem, with a target SoC temperature of 55C Signed-off-by: Alexey Charkov Acked-by: Daniel Lezcano --- arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts | 25 ++++++++++++++++++++++++- 1 file changed, 24 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts index 9b7bf6cec8bd..c4c94e0b6163 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-rock-5b.dts @@ -52,7 +52,7 @@ led_rgb_b { fan: pwm-fan { compatible = "pwm-fan"; - cooling-levels = <0 95 145 195 255>; + cooling-levels = <0 120 150 180 210 240 255>; fan-supply = <&vcc5v0_sys>; pwms = <&pwm1 0 50000 0>; #cooling-cells = <2>; @@ -180,6 +180,25 @@ &cpu_l3 { cpu-supply = <&vdd_cpu_lit_s0>; }; +&package_thermal { + polling-delay = <1000>; + + trips { + package_fan: package-fan { + temperature = <55000>; + hysteresis = <2000>; + type = "active"; + }; + }; + + cooling-maps { + map-fan { + trip = <&package_fan>; + cooling-device = <&fan THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; +}; + &i2c0 { pinctrl-names = "default"; pinctrl-0 = <&i2c0m2_xfer>; @@ -738,6 +757,10 @@ regulator-state-mem { }; }; +&tsadc { + status = "okay"; +}; + &uart2 { pinctrl-0 = <&uart2m0_xfer>; status = "okay"; From patchwork Wed Jan 24 20:30:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alexey Charkov X-Patchwork-Id: 191756 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1242468dyi; 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Wed, 24 Jan 2024 12:30:43 -0800 (PST) Received: from [172.30.32.188] ([2001:8f8:183b:50fb::d35]) by smtp.gmail.com with ESMTPSA id r15-20020a05600c458f00b0040d62f89381sm174073wmo.35.2024.01.24.12.30.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 12:30:43 -0800 (PST) From: Alexey Charkov Date: Thu, 25 Jan 2024 00:30:07 +0400 Subject: [PATCH 4/4] arm64: dts: rockchip: Add OPP data for CPU cores on RK3588 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240125-rk-dts-additions-v1-4-5879275db36f@gmail.com> References: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> In-Reply-To: <20240125-rk-dts-additions-v1-0-5879275db36f@gmail.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner Cc: Daniel Lezcano , Dragan Simic , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Alexey Charkov X-Mailer: b4 0.12.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1706128223; l=8740; i=alchark@gmail.com; s=20240125; h=from:subject:message-id; bh=JJqT9UTpf85L5Gq2NC1bIoVV2fXmQ+hsdNDZBhO5wms=; b=pSX8bHCbBcvrohGdJ2VDdnz7u/QyP80+XkWJHVuTXKnzmrrPyZTvqljNk1DpRKs6L+oFZO5ib 7pimpVJ6J4vCfqmrujOdGgkN1nB9lw2jdqA6la6B0IeTyCtyF4mraKq X-Developer-Key: i=alchark@gmail.com; a=ed25519; pk=xRO8VeD3J5jhwe0za0aHt2LDumQr8cm0Ls7Jz3YGimk= X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1789005655801993367 X-GMAIL-MSGID: 1789005655801993367 By default the CPUs on RK3588 start up in a conservative performance mode. Add frequency and voltage mappings to the device tree to enable dynamic scaling via cpufreq Signed-off-by: Alexey Charkov --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 209 ++++++++++++++++++++++++++++++ 1 file changed, 209 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index 131b9eb21398..e605be531a0f 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -97,6 +97,7 @@ cpu_l0: cpu@0 { clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUL>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -116,6 +117,7 @@ cpu_l1: cpu@100 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -135,6 +137,7 @@ cpu_l2: cpu@200 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -154,6 +157,7 @@ cpu_l3: cpu@300 { enable-method = "psci"; capacity-dmips-mhz = <530>; clocks = <&scmi_clk SCMI_CLK_CPUL>; + operating-points-v2 = <&cluster0_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <32768>; i-cache-line-size = <64>; @@ -175,6 +179,7 @@ cpu_b0: cpu@400 { clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB01>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -194,6 +199,7 @@ cpu_b1: cpu@500 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB01>; + operating-points-v2 = <&cluster1_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -215,6 +221,7 @@ cpu_b2: cpu@600 { clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clocks = <&scmi_clk SCMI_CLK_CPUB23>; assigned-clock-rates = <816000000>; + operating-points-v2 = <&cluster2_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -234,6 +241,7 @@ cpu_b3: cpu@700 { enable-method = "psci"; capacity-dmips-mhz = <1024>; clocks = <&scmi_clk SCMI_CLK_CPUB23>; + operating-points-v2 = <&cluster2_opp_table>; cpu-idle-states = <&CPU_SLEEP>; i-cache-size = <65536>; i-cache-line-size = <64>; @@ -348,6 +356,207 @@ l3_cache: l3-cache { }; }; + cluster0_opp_table: opp-table-cluster0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 950000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <712500 712500 950000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <762500 762500 950000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <850000 850000 950000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <950000 950000 950000>; + clock-latency-ns = <40000>; + }; + }; + + cluster1_opp_table: opp-table-cluster1 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + + cluster2_opp_table: opp-table-cluster2 { + compatible = "operating-points-v2"; + opp-shared; + + opp-408000000 { + opp-hz = /bits/ 64 <408000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + opp-suspend; + }; + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-816000000 { + opp-hz = /bits/ 64 <816000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1008000000 { + opp-hz = /bits/ 64 <1008000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1200000000 { + opp-hz = /bits/ 64 <1200000000>; + opp-microvolt = <675000 675000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1416000000 { + opp-hz = /bits/ 64 <1416000000>; + opp-microvolt = <725000 725000 1000000>; + clock-latency-ns = <40000>; + }; + opp-1608000000 { + opp-hz = /bits/ 64 <1608000000>; + opp-microvolt = <762500 762500 1000000>; + clock-latency-ns = <40000>; + }; + opp-1800000000 { + opp-hz = /bits/ 64 <1800000000>; + opp-microvolt = <850000 850000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2016000000 { + opp-hz = /bits/ 64 <2016000000>; + opp-microvolt = <925000 925000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + opp-microvolt = <987500 987500 1000000>; + clock-latency-ns = <40000>; + }; + opp-2256000000 { + opp-hz = /bits/ 64 <2256000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2304000000 { + opp-hz = /bits/ 64 <2304000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2352000000 { + opp-hz = /bits/ 64 <2352000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + opp-2400000000 { + opp-hz = /bits/ 64 <2400000000>; + opp-microvolt = <1000000 1000000 1000000>; + clock-latency-ns = <40000>; + }; + }; + firmware { optee: optee { compatible = "linaro,optee-tz";