From patchwork Mon Nov 14 20:06:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 20022 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2342776wru; Mon, 14 Nov 2022 12:13:07 -0800 (PST) X-Google-Smtp-Source: AA0mqf70UiYY6xEN6aQoHTCOaqEOWFZTLlLQL4qGXKRi/BiDNJpEzLNZCNg8GHKeWJzz019JMfWW X-Received: by 2002:aa7:d7c7:0:b0:462:3340:757b with SMTP id e7-20020aa7d7c7000000b004623340757bmr12259941eds.308.1668456787334; Mon, 14 Nov 2022 12:13:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668456787; cv=none; d=google.com; s=arc-20160816; b=A5m0WS/O1g0V6oDEkQQfs4mMTysHair5dobXsORuQ8u2J+fJeLyf0HrFpKKDrQQNNz dNKw/Yu0H7UIixXN4WP2HdOExMv7Q7TfnpiTb6+VmE1TqMkABWvXi90EZX1EWr9WHLT8 UwzEaudj9ZlrYi/lBnVt+BI7j326iEMcebtGmANJQ1Eg13zqh4fbmnRO5XkkAMhIhq/g IgmeZiU9rpdvupo345QGa2TW1J6RFnodDK5KBUYsec2nUhhRlc8Iyxat7BO2O5SgtBQD vmeqOb0sxyuS3MLewkIlB22DMDHOAlcnmJq1L1d1/FzhpRUVuNmuSxCApvVO9bkjaM4t pbdg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=Ai+y2C+8FY85QYrIshFzPOa7btzfVx4F7ryDUKrVHVk=; b=GGy3x61emrC9ENNLqF1mN4AyOEmP5R/fgaUTGzy0Y8XwDBWBeJtC5uAch0qtlmCaSG xI+oMacRUmMWqfTKBSEr0I000CdP+3yIlraSon3b/aixIJgH+eHIcwaDP3reblOkbZuk PIRP+53H3Vs9UVOFVW5gTs3S2ztCku6OwYfV+vwpCGOVq7Ykp/66PoO5StAh3cddhZrI Ay9A0fpzg8IYyy4+fFYE+P462IzHBIGw4U1v4p8mpfap7KBF0NyJUjCkjaOMbSgLAual H5oO2tnlMwSHwoAr+qEeJv0IMr36auY8EIThS/Mi0EMihlieX7pQ8jLHz22W5xilgfJQ R64w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U7E1D+2t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. [2620:137:e000::1:20]) by mx.google.com with ESMTP id v18-20020a056402349200b00462a87b0546si10893044edc.607.2022.11.14.12.12.42; Mon, 14 Nov 2022 12:13:07 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) client-ip=2620:137:e000::1:20; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=U7E1D+2t; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237410AbiKNUGc (ORCPT + 99 others); Mon, 14 Nov 2022 15:06:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236438AbiKNUGY (ORCPT ); Mon, 14 Nov 2022 15:06:24 -0500 Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A32ACEA4; Mon, 14 Nov 2022 12:06:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1668456383; x=1699992383; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E6Fr5EqSLsNUebM1iEN8hkFtHJmRiv4orK6AmUjJIB0=; b=U7E1D+2tcfMlvcnqf11wUH3nRsprsN+UpWhzby9FLTInSS9YErYZe+Dx tB4Vn4QLHZMg5pH7iuwcFNSaUi/YlwpWMflMegkYVJzMMFyqAtjQOC0TF t65v2uzL8Mwnrdvk9F0MIfndEy5yVaLoCE8LaVYa4LB9ANnYz5LLH+9Mr PvdsLLZh7gRCmzla+jg778J2qeRLgonQTh7Ys3Gwy/2HFXJH0NvYI2smB yNup7SiKUEHKw3KXcvETUrqcf+joLTpVZZ3bgGeBdNrc+Zi25Pefp1eiT UpqK9jMuYdW7s1SsdksBvAsfLoAwS9rUwac9knFiHxzCutSQ57IkObB3v g==; X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="310779575" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="310779575" Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga104.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 12:06:22 -0800 X-IronPort-AV: E=McAfee;i="6500,9779,10531"; a="589508116" X-IronPort-AV: E=Sophos;i="5.96,164,1665471600"; d="scan'208";a="589508116" Received: from parandri-mobl.amr.corp.intel.com (HELO guptapa-desk.intel.com) ([10.209.117.50]) by orsmga003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Nov 2022 12:06:22 -0800 From: Pawan Gupta To: "H. Peter Anvin" , Thomas Gleixner , David.Kaplan@amd.com, thomas.lendacky@amd.com, Borislav Petkov , x86@kernel.org, hdegoede@redhat.com, Dave Hansen , Andrew Cooper , Pavel Machek , Ingo Molnar , "Rafael J. Wysocki" Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com Subject: [PATCH v2 1/2] x86/tsx: Add feature bit for TSX control MSR support Date: Mon, 14 Nov 2022 12:06:15 -0800 Message-Id: <80961915d70eb31d564f9ddeaab809e5c895f3cc.1668455932.git.pawan.kumar.gupta@linux.intel.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749503744238552046?= X-GMAIL-MSGID: =?utf-8?q?1749503744238552046?= Support for TSX control MSR is enumerated in MSR_IA32_ARCH_CAPABILITIES. This is different from how other CPU features are enumerated i.e. via CPUID. Currently a call to tsx_ctrl_is_supported() is required for enumerating the feature. In the absence of feature bit for TSX control, any code that relies on checking feature bits directly will not work. In preparation for adding a feature bit check in MSR save/restore during suspend/resume, set a new feature bit X86_FEATURE_TSX_CTRL when MSR_IA32_TSX_CTRL is present. Also make tsx_ctrl_is_supported() use the new feature bit to avoid any overhead of reading the MSR. Suggested-by: Andrew Cooper Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/tsx.c | 30 +++++++++++++++--------------- 2 files changed, 16 insertions(+), 15 deletions(-) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index b71f4f2ecdd5..3cda06ebe046 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -304,6 +304,7 @@ #define X86_FEATURE_UNRET (11*32+15) /* "" AMD BTB untrain return */ #define X86_FEATURE_USE_IBPB_FW (11*32+16) /* "" Use IBPB during runtime firmware calls */ #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */ +#define X86_FEATURE_MSR_TSX_CTRL (11*32+18) /* "" MSR IA32_TSX_CTRL (Intel) implemented */ /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */ #define X86_FEATURE_AVX_VNNI (12*32+ 4) /* AVX VNNI instructions */ diff --git a/arch/x86/kernel/cpu/tsx.c b/arch/x86/kernel/cpu/tsx.c index ec7bbac3a9f2..9fe488dbed15 100644 --- a/arch/x86/kernel/cpu/tsx.c +++ b/arch/x86/kernel/cpu/tsx.c @@ -60,20 +60,7 @@ static void tsx_enable(void) static bool tsx_ctrl_is_supported(void) { - u64 ia32_cap = x86_read_arch_cap_msr(); - - /* - * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this - * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES. - * - * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a - * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES - * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get - * MSR_IA32_TSX_CTRL support even after a microcode update. Thus, - * tsx= cmdline requests will do nothing on CPUs without - * MSR_IA32_TSX_CTRL support. - */ - return !!(ia32_cap & ARCH_CAP_TSX_CTRL_MSR); + return cpu_feature_enabled(X86_FEATURE_MSR_TSX_CTRL); } static enum tsx_ctrl_states x86_get_tsx_auto_mode(void) @@ -191,7 +178,20 @@ void __init tsx_init(void) return; } - if (!tsx_ctrl_is_supported()) { + /* + * TSX is controlled via MSR_IA32_TSX_CTRL. However, support for this + * MSR is enumerated by ARCH_CAP_TSX_MSR bit in MSR_IA32_ARCH_CAPABILITIES. + * + * TSX control (aka MSR_IA32_TSX_CTRL) is only available after a + * microcode update on CPUs that have their MSR_IA32_ARCH_CAPABILITIES + * bit MDS_NO=1. CPUs with MDS_NO=0 are not planned to get + * MSR_IA32_TSX_CTRL support even after a microcode update. Thus, + * tsx= cmdline requests will do nothing on CPUs without + * MSR_IA32_TSX_CTRL support. + */ + if (x86_read_arch_cap_msr() & ARCH_CAP_TSX_CTRL_MSR) { + setup_force_cpu_cap(X86_FEATURE_MSR_TSX_CTRL); + } else { tsx_ctrl_state = TSX_CTRL_NOT_SUPPORTED; return; } From patchwork Mon Nov 14 20:06:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Pawan Gupta X-Patchwork-Id: 20023 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a5d:6687:0:0:0:0:0 with SMTP id l7csp2342794wru; Mon, 14 Nov 2022 12:13:08 -0800 (PST) X-Google-Smtp-Source: AA0mqf59PRWqpE4zP8AwY5Zfh7cVEeAdFdXui67eK5LLuNq9vh+6vjDK9o5YAbPns2umlb9AxQQd X-Received: by 2002:a17:907:1398:b0:78b:a8d:e76a with SMTP id vs24-20020a170907139800b0078b0a8de76amr11530120ejb.725.1668456788708; Mon, 14 Nov 2022 12:13:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1668456788; cv=none; d=google.com; s=arc-20160816; b=vUq7jQIAOL2GZjgJRL4gpwA+UVeyMtNYWyL9c8uDazt+Ibq1gQXwYHQdbOKcDtv2b9 dJm5q+UF4WoSUAI7Xampzy3lLIvgCkLLLTF0PRhtKJZ00daTuw+dUGwgY1sOu4Q2Vcjy phE2hbY/9fw+Eim8EnmFIZli5/9UAt2FHcbjZxFoxHAz7Zy2zID7QUFdtIJ8cKK/qmRb +BowmIWPop0kizBkM9zXuweZAOSgFnrgxn3x2G1xxe+fuJN+7Dmf9m+XLMcHQOG2ssKZ QUKxPX93cPWAL91juJtW96aQrpleXYoMc+ARwRBM0cazouCkoWyd1kkfblA3yFIeI0ow CXzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=gqNBLDPgN++x2M0iVi7XngvsnPrceik6A9WsU0KdAuY=; b=ZIEaf9DCS2OoeqoRk8vS6vSR1IwmU/kWFQ6kKVoCvG+juD62440YQ3+QG6w++q3nJk 7ai8muvtoWs625csTUVFozLptUFjzOE2DUpLq6BgHhwGhUlna23KTFxV6AXfjQ2yma4H FKvXRtWabreBTlQLejmxEogfjj0mhjH+VHZgLs22kko32T7nGtm0RwPhBWL2pMuiyPly B+XYDD44ECViIQcvuY+djsT84xwdtGsHeqhF0JAk0qsy1QhwcEFq686rA7rxxHnmkyND UWARe1iHIHG3NOXe4Zxy5RDP3cXOOgkdDpSYcsIeb7/hF4rvqt9QjfyXpDiRHciFPLVV Wf9w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=bHTj4Ll0; spf=pass (google.com: domain of linux-kernel-owner@vger.kernel.org designates 2620:137:e000::1:20 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from out1.vger.email (out1.vger.email. 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Peter Anvin" , Thomas Gleixner , David.Kaplan@amd.com, thomas.lendacky@amd.com, Borislav Petkov , x86@kernel.org, hdegoede@redhat.com, Dave Hansen , Andrew Cooper , Pavel Machek , Ingo Molnar , "Rafael J. Wysocki" Cc: linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, Daniel Sneddon , antonio.gomez.iglesias@linux.intel.com Subject: [PATCH v2 2/2] x86/pm: Add enumeration check before spec MSRs save/restore setup Date: Mon, 14 Nov 2022 12:06:16 -0800 Message-Id: X-Mailer: git-send-email 2.37.3 In-Reply-To: References: MIME-Version: 1.0 X-Spam-Status: No, score=-4.3 required=5.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_EF,RCVD_IN_DNSWL_MED,SPF_HELO_NONE, SPF_NONE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on lindbergh.monkeyblade.net Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org X-getmail-retrieved-from-mailbox: =?utf-8?q?INBOX?= X-GMAIL-THRID: =?utf-8?q?1749503745566839275?= X-GMAIL-MSGID: =?utf-8?q?1749503745566839275?= pm_save_spec_msr() keeps a list of all the MSRs which _might_ need to be saved and restored at hibernate?? and resume??. However, it has zero awareness of CPU support for these MSRs. It mostly works by unconditionally attempting to manipulate these MSRs and relying on rdmsrl_safe() being able to handle a #GP on CPUs where the support is unavailable. However, it's possible for reads (RDMSR) to be supported for a given MSR while writes (WRMSR) are not. In this case, msr_build_context() sees a successful read (RDMSR) and marks the MSR as 'valid'. Then, later, a write (WRMSR) fails, producing a nasty (but harmless) error message. This causes restore_processor_state() to try and restore it, but writing this MSR is not allowed on the Intel Atom N2600 leading to: unchecked MSR access error: WRMSR to 0x122 (tried to write 0x0000000000000002) \ at rIP: 0xffffffff8b07a574 (native_write_msr+0x4/0x20) Call Trace: restore_processor_state x86_acpi_suspend_lowlevel acpi_suspend_enter suspend_devices_and_enter pm_suspend.cold state_store kernfs_fop_write_iter vfs_write ksys_write do_syscall_64 ? do_syscall_64 ? up_read ? lock_is_held_type ? asm_exc_page_fault ? lockdep_hardirqs_on entry_SYSCALL_64_after_hwframe To fix this, add the corresponding X86_FEATURE bit for each MSR. Avoid trying to manipulate the MSR when the feature bit is clear. This required adding a X86_FEATURE bit for MSRs that do not have one already, but it's a small price to pay. Fixes: 73924ec4d560 ("x86/pm: Save the MSR validity status at context setup") Reported-by: Hans de Goede Signed-off-by: Pawan Gupta --- arch/x86/power/cpu.c | 23 ++++++++++++++++------- 1 file changed, 16 insertions(+), 7 deletions(-) diff --git a/arch/x86/power/cpu.c b/arch/x86/power/cpu.c index bb176c72891c..0d97c25551f0 100644 --- a/arch/x86/power/cpu.c +++ b/arch/x86/power/cpu.c @@ -511,17 +511,26 @@ static int pm_cpu_check(const struct x86_cpu_id *c) return ret; } +struct msr_enumeration { + u32 msr_no; + u32 feature; +}; + static void pm_save_spec_msr(void) { - u32 spec_msr_id[] = { - MSR_IA32_SPEC_CTRL, - MSR_IA32_TSX_CTRL, - MSR_TSX_FORCE_ABORT, - MSR_IA32_MCU_OPT_CTRL, - MSR_AMD64_LS_CFG, + struct msr_enumeration msr_enum[] = { + {MSR_IA32_SPEC_CTRL, X86_FEATURE_MSR_SPEC_CTRL}, + {MSR_IA32_TSX_CTRL, X86_FEATURE_MSR_TSX_CTRL}, + {MSR_TSX_FORCE_ABORT, X86_FEATURE_TSX_FORCE_ABORT}, + {MSR_IA32_MCU_OPT_CTRL, X86_FEATURE_SRBDS_CTRL}, + {MSR_AMD64_LS_CFG, X86_FEATURE_LS_CFG_SSBD}, }; + int i; - msr_build_context(spec_msr_id, ARRAY_SIZE(spec_msr_id)); + for (i = 0; i < ARRAY_SIZE(msr_enum); i++) { + if (boot_cpu_has(msr_enum[i].feature)) + msr_build_context(&msr_enum[i].msr_no, 1); + } } static int pm_check_save_msr(void)