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Wed, 24 Jan 2024 07:01:47 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id o10-20020a5d62ca000000b00337d4ce6ab4sm15999360wrv.20.2024.01.24.07.01.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 07:01:46 -0800 (PST) Date: Wed, 24 Jan 2024 18:01:42 +0300 From: Dan Carpenter To: Niklas Cassel Cc: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v4 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Message-ID: <888c23ff-1ee4-4795-8c24-7631c6c37da6@moroto.mountain> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788984749093336519 X-GMAIL-MSGID: 1788984749093336519 The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does: msg_addr &= ~aligned_offset; it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do the alignment instead. Cc: stable@vger.kernel.org Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") Signed-off-by: Dan Carpenter Reviewed-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- v4: Add stable and r-b from Niklas v3: Use ALIGN_DOWN() v2: fix typo in commit message drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b..51679c6702cf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } aligned_offset = msg_addr & (epc->mem->window.page_size - 1); - msg_addr &= ~aligned_offset; + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) From patchwork Wed Jan 24 15:03:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dan Carpenter X-Patchwork-Id: 191606 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp1048633dyi; Wed, 24 Jan 2024 07:07:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbcLnRGBZ7iuplFG/xku8HJzhVdySFT93Ztnb8qG3Mprdy5J6H+qPMy2JJoYoqr10mVxFf X-Received: by 2002:a17:902:dacc:b0:1d7:37cf:6c71 with SMTP id q12-20020a170902dacc00b001d737cf6c71mr1033333plx.38.1706108824208; Wed, 24 Jan 2024 07:07:04 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706108824; cv=pass; d=google.com; s=arc-20160816; b=xcWsPyBjPkY1APwQApdJvwd/3lsOhtDyOzf1O3s/kOmPvOhRux+X+nNwFJqO5XT2i6 /NZ1oniIH2qpsaayGVM5As3pFtQwg53hjMp7zXZrLSsSMVEO0yyuGuNFZMOFcHQY5ZCb rxaN5tm7gsbiV6h0cb0jwrs821M4O2cYgGsNw3dGosDPXBIRZW8JhYiWKU08qkMIq9dh GqY2saM/lxbskb8SFZ/npiWrDWTrR4T8wHyNQLYffk/0w8mN21kOrayRjNqainvGg3Fj 2IQiuBLFRq7Cd7ZDGXRUwUqNrua8FIwZ7wjxDoTD7w4AX13PgJOof9TQGhJJm8Vm5is8 TrkQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:subject:cc:to:from :date:dkim-signature; bh=VlaR5UjpyG5Q22l5wBG4NSdMskPDkfH7d0hZ/q3K1b0=; fh=eXzY3uCod0uoUhoSFH26hwNyKgz3imtHgoKrWTV58bE=; b=rCnwFxcqyTnMSELCQgIzT8tEu4295O3xOkFVRNipK8D6b25YanHKlCdJPwwkwGy6bz v/G37oJsz3tQKvsKKdXorkMFp2NZEOgA6kOT5yx7RNfbB8PlMTYG8Mnm9iLkFkvRhvVT ZrkxBW89KkT1Eymh1iyC2l7c81Go56r8UYSa5cUXk1HQpRSxPJkyuG+B6b6fGcIIitGm ggNotZy6sXculfJfcVi5beG1Guq17SL+UzPB2KtabHZKwbXdR9L0lao/VK75afq8cqB0 enuMuvTBTyOkTUt657h9W0qH58RsI3OTA9D5hjO26TkgxpE2WBmg4hS/OqUhZYZweWKW q+og== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Pf6e+/lA"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-37218-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-37218-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Wed, 24 Jan 2024 07:03:54 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id f7-20020adff8c7000000b0033921c383b2sm13626449wrq.67.2024.01.24.07.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 07:03:54 -0800 (PST) Date: Wed, 24 Jan 2024 18:03:51 +0300 From: Dan Carpenter To: Jingoo Han Cc: Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v4 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Message-ID: <64ef42f0-5618-40fd-b715-0d412121045c@moroto.mountain> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <888c23ff-1ee4-4795-8c24-7631c6c37da6@moroto.mountain> X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788984766496219514 X-GMAIL-MSGID: 1788984766496219514 I recently changed the alignment code in dw_pcie_ep_raise_msix_irq(). The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match as well, just for consistency. (No effect on runtime, just a cleanup). Signed-off-by: Dan Carpenter Reviewed-by: Ilpo Järvinen Reviewed-by: Niklas Cassel Reviewed-by: Manivannan Sadhasivam --- v4: style improvements v3: use ALIGN_DOWN() v2: new patch drivers/pci/controller/dwc/pcie-designware-ep.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 51679c6702cf..d2de41f02a77 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -482,9 +482,10 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, reg = ep_func->msi_cap + PCI_MSI_DATA_32; msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); } - aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); - msg_addr = ((u64)msg_addr_upper) << 32 | - (msg_addr_lower & ~aligned_offset); + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; + + aligned_offset = msg_addr & (epc->mem->window.page_size - 1); + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret)