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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id j3-20020a056a00130300b006d9c216a9e6sm13597173pfu.56.2024.01.24.04.54.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 04:54:06 -0800 (PST) From: Monk Chiang To: gcc-patches@gcc.gnu.org, rguenther@suse.de, jeffreyalaw@gmail.com, kito.cheng@sifive.com Cc: Monk Chiang Subject: [PATCH v3] RISC-V: Add split pattern to generate SFB instructions. [PR113095] Date: Wed, 24 Jan 2024 20:54:00 +0800 Message-Id: <20240124125400.111160-1-monk.chiang@sifive.com> X-Mailer: git-send-email 2.40.1 MIME-Version: 1.0 X-Spam-Status: No, score=-13.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+ouuuleilei=gmail.com@gcc.gnu.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788770009017909708 X-GMAIL-MSGID: 1788976457531681240 Since the match.pd transforms (zero_one == 0) ? y : z y, into ((typeof(y))zero_one * z) y. Add splitters to recongize this expression to generate SFB instructions. gcc/ChangeLog: PR target/113095 * config/riscv/sfb.md: New splitters to rewrite single bit sign extension as the condition to SFB instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/sfb.c: New test. * gcc.target/riscv/pr113095.c: New test. --- gcc/config/riscv/sfb.md | 32 +++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/pr113095.c | 21 +++++++++++++++ gcc/testsuite/gcc.target/riscv/sfb.c | 24 +++++++++++++++++ 3 files changed, 77 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/pr113095.c create mode 100644 gcc/testsuite/gcc.target/riscv/sfb.c diff --git a/gcc/config/riscv/sfb.md b/gcc/config/riscv/sfb.md index 52af4b17d46..5a510fe9f09 100644 --- a/gcc/config/riscv/sfb.md +++ b/gcc/config/riscv/sfb.md @@ -35,3 +35,35 @@ [(set_attr "length" "8") (set_attr "type" "sfb_alu") (set_attr "mode" "")]) + +;; Combine creates this form ((typeof(y))zero_one * z) y +;; for SiFive short forward branches. + +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_SFB_ALU" + [(set (match_dup 4) (zero_extract:X (match_dup 1) (const_int 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0)) + (match_dup 3) + (const_int 0)))]) + +(define_split + [(set (match_operand:X 0 "register_operand") + (and:X (sign_extract:X (match_operand:X 1 "register_operand") + (const_int 1) + (match_operand 2 "immediate_operand")) + (match_operand:X 3 "register_operand"))) + (clobber (match_operand:X 4 "register_operand"))] + "TARGET_SFB_ALU && (UINTVAL (operands[2]) < 11)" + [(set (match_dup 4) (and:X (match_dup 1) (match_dup 2))) + (set (match_dup 0) (if_then_else:X (ne (match_dup 4) (const_int 0)) + (match_dup 3) + (const_int 0)))] +{ + operands[2] = GEN_INT (1 << UINTVAL(operands[2])); +}) diff --git a/gcc/testsuite/gcc.target/riscv/pr113095.c b/gcc/testsuite/gcc.target/riscv/pr113095.c new file mode 100644 index 00000000000..04321b58dc7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr113095.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" { target { rv32 } } } */ +/* { dg-options "-O2 -march=rv64gc -mabi=lp64d -mtune=sifive-7-series" {target { rv64 } } } */ + +extern void abort (void); +extern void exit (int); + +unsigned short __attribute__ ((noinline, noclone)) +foo (unsigned short x) { + if (x == 1) + x ^= 0x4002; + + return x; +} + +int main () { + if (foo(1) != 0x4003) + abort (); + + exit(0); +} diff --git a/gcc/testsuite/gcc.target/riscv/sfb.c b/gcc/testsuite/gcc.target/riscv/sfb.c new file mode 100644 index 00000000000..22f164051f4 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/sfb.c @@ -0,0 +1,24 @@ +//* { dg-do compile } */ +/* { dg-options "-O2 -march=rv32gc -mabi=ilp32d -mtune=sifive-7-series" } */ + +int f1(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) == 0) ? y : z ^ y; +} + +int f2(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) != 0) ? z ^ y : y; +} + +int f3(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) == 0) ? y : z | y; +} + +int f4(unsigned int x, unsigned int y, unsigned int z) +{ + return ((x & 1) != 0) ? z | y : y; +} +/* { dg-final { scan-assembler-times "bne" 4 } } */ +/* { dg-final { scan-assembler-times "movcc" 4 } } */