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[2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id i4-20020ae9ee04000000b0078318da9939si9591139qkg.132.2024.01.24.01.40.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 01:40:15 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 498CF3858425 for ; Wed, 24 Jan 2024 09:40:15 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id CDE0E3858D37 for ; Wed, 24 Jan 2024 09:38:14 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org CDE0E3858D37 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org CDE0E3858D37 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706089103; cv=none; b=f8l1WSTh10dm2QTPntRwdSV5KA++XVdIATxt47cyEb5bX867zfgiYjCQld6sAAwJ3PFhgx0HEdOzN0skDdub/wqJdRnAkrSp9jUkrGwOx23ZUAezpZIPb1IlDzXUP3hK4hf2ll3atw10ELvoE4BEKFYnOdhi6bvfjEDBAqPrMTE= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706089103; c=relaxed/simple; bh=daJAAnw4eHVJj3tK0T9hybKZZnlhU4eu8dPuperV+nY=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=g3FHZha75fstcBDGV591BYOsgnq6p2tWfyJqnEUbIXT4uXraupLFjOPTBmsGqwVE6DiknMzzh7MZd1gmGeF+yKu4fxA2qDDBHoHc7Z3VBUVgIEl06bmqKzOHILCBUOK8cFswW4ssl7UT8cwXDwVrlqxysQlmzIh/LXoIveORJho= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-03 (Coremail) with SMTP id rQCowACnrjZ42rBlWy5ICQ--.19636S2; Wed, 24 Jan 2024 17:38:01 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, research_trasio@irq.a4lg.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, nandni.jamnadas@embecosm.com, mary.bennett@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, sinan.lin@linux.alibaba.com, gaofei@eswincomputing.com, fujin.zhao@foxmail.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH v4 1/2] RISC-V: Support Zcmp push/pop instructions. Date: Wed, 24 Jan 2024 17:37:24 +0800 Message-Id: <20240124093725.567220-1-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 X-CM-TRANSID: rQCowACnrjZ42rBlWy5ICQ--.19636S2 X-Coremail-Antispam: 1UD129KBjvAXoWfur1fKrW5XryrAF4fCw45Wrg_yoW5tw18Zo WxXa1rKFs0g3W2krn5tr1fGa1kua4rGr93Xwn8uw1DAFWDC3yxGryYqa1xu34UKr4fWryD Za4kWrW8XF4vqr47n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUY-7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l8cAvFVAK0II2c7xJM28CjxkF64kEwVA0rcxSw2 x7M28EF7xvwVC0I7IYx2IY67AKxVW8JVW5JwA2z4x0Y4vE2Ix0cI8IcVCY1x0267AKxVWx JVW8Jr1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26r xl6s0DM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj 6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr 0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E 8cxan2IY04v7MxkIecxEwVAFjwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJV W8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF 1VAFwI0_GFv_WrylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6x IIjxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvE x4A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvj DU0xZFpf9x0JUbeOJUUUUU= X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQ8GAGWwzOY4oAAAsn X-Spam-Status: No, score=-9.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SCC_10_SHORT_WORD_LINES, SCC_20_SHORT_WORD_LINES, SCC_5_SHORT_WORD_LINES, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788964205353244056 X-GMAIL-MSGID: 1788964205353244056 Support zcmp extension push/pop/popret and popret zero instructions. `reg_list` is a list containing 1 to 13 registers, we can use: "{ra}, {ra, s0}, {ra, s0-s1}, {ra, s0-s2}, …, {ra, s0-sN}" to present this feature. `stack_adj` is the total size of the stack frame, use `riscv_get_sp_base` function to calculate it. Most work was finished by Sinan Lin. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi Version log: Fixes format issues, rename 'rlist' to 'reg_list', 'SP_ALIGNMENT'to 'ZCMP_SP_ALIGNMENT', use 'strtok' in reglist parser, adds conflict check with 'Zcd' extension. bfd/ChangeLog: * elfxx-riscv.c (riscv_parse_check_conflicts): New function. (riscv_multi_subset_supports): New extension. (riscv_multi_subset_supports_ext): Ditto. * elfxx-riscv.h (ZCMP_SP_ALIGNMENT): New macro. gas/ChangeLog: * config/tc-riscv.c (regno_to_reg_list): New function. (reglist_lookup): Ditto. (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-push-pop-fail.d: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.l: New test. * testsuite/gas/riscv/zcmp-push-pop-fail.s: New test. * testsuite/gas/riscv/zcmp-push-pop.d: New test. * testsuite/gas/riscv/zcmp-push-pop.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_PUSH): New opcode. (MASK_CM_PUSH): New mask. (MATCH_CM_POP): New opcode. (MASK_CM_POP): New mask. (MATCH_CM_POPRET): New opcode. (MASK_CM_POPRET): New mask. (MATCH_CM_POPRETZ): New opcode. (MASK_CM_POPRETZ): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (EXTRACT_ZCMP_SPIMM): New inline function. (ENCODE_ZCMP_SPIMM): Ditto. (VALID_ZCMP_SPIMM): Ditto. (OP_MASK_REG_LIST): New mask. (OP_SH_REG_LIST): New operand code. (ZCMP_SP_ALIGNMENT): New argument. (X_S0): New reg number. (X_S1): Ditto. (X_S2): Ditto. (X_S10): Ditto. (X_S11): Ditto. (enum riscv_insn_class): New extension class. (riscv_get_sp_base): New function. opcodes/ChangeLog: * riscv-dis.c (set_default_riscv_dis_options): (parse_riscv_dis_option_without_args): (print_reg_list): (riscv_get_spimm): (print_insn_args): * riscv-opc.c: --- bfd/elfxx-riscv.c | 13 ++ bfd/elfxx-riscv.h | 1 + gas/config/tc-riscv.c | 148 +++++++++++++++++ gas/testsuite/gas/riscv/zcmp-push-pop-fail.d | 3 + gas/testsuite/gas/riscv/zcmp-push-pop-fail.l | 9 ++ gas/testsuite/gas/riscv/zcmp-push-pop-fail.s | 13 ++ gas/testsuite/gas/riscv/zcmp-push-pop.d | 154 ++++++++++++++++++ gas/testsuite/gas/riscv/zcmp-push-pop.s | 162 +++++++++++++++++++ include/opcode/riscv-opc.h | 14 ++ include/opcode/riscv.h | 29 ++++ opcodes/riscv-dis.c | 57 +++++++ opcodes/riscv-opc.c | 6 + 12 files changed, 609 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.d create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.l create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop-fail.s create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop.d create mode 100644 gas/testsuite/gas/riscv/zcmp-push-pop.s diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 9a121b47121..2ad4682f19f 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c @@ -1193,6 +1193,7 @@ static struct riscv_implicit_subset riscv_implicit_subsets[] = {"zcf", "zca", check_implicit_always}, {"zcd", "zca", check_implicit_always}, {"zcb", "zca", check_implicit_always}, + {"zcmp", "zca", check_implicit_always}, {"smaia", "ssaia", check_implicit_always}, {"smcntrpmf", "zicsr", check_implicit_always}, {"smstateen", "ssstateen", check_implicit_always}, @@ -1340,6 +1341,7 @@ static struct riscv_supported_ext riscv_supported_std_z_ext[] = {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1981,6 +1983,13 @@ riscv_parse_check_conflicts (riscv_parse_subset_t *rps) rps->error_handler (_("rv%d does not support the `q' extension"), xlen); no_conflict = false; } + if (riscv_subset_supports (rps, "zcmp") + && riscv_subset_supports (rps, "zcd")) + { + rps->error_handler + (_("zcmp' is incompatible with `d/zcd' extension")); + no_conflict = false; + } if (riscv_lookup_subset (rps->subset_list, "zcf", &subset) && xlen > 32) { @@ -2568,6 +2577,8 @@ riscv_multi_subset_supports (riscv_parse_subset_t *rps, case INSN_CLASS_ZCB_AND_ZMMUL: return (riscv_subset_supports (rps, "zcb") && riscv_subset_supports (rps, "zmmul")); + case INSN_CLASS_ZCMP: + return riscv_subset_supports (rps, "zcmp"); case INSN_CLASS_SVINVAL: return riscv_subset_supports (rps, "svinval"); case INSN_CLASS_H: @@ -2820,6 +2831,8 @@ riscv_multi_subset_supports_ext (riscv_parse_subset_t *rps, return _("zcb' and `zbb"); case INSN_CLASS_ZCB_AND_ZMMUL: return _("zcb' and `zmmul', or `zcb' and `m"); + case INSN_CLASS_ZCMP: + return "zcmp"; case INSN_CLASS_SVINVAL: return "svinval"; case INSN_CLASS_H: diff --git a/bfd/elfxx-riscv.h b/bfd/elfxx-riscv.h index ae4cbee7bc3..e60a40f63bb 100644 --- a/bfd/elfxx-riscv.h +++ b/bfd/elfxx-riscv.h @@ -26,6 +26,7 @@ #include "cpu-riscv.h" #define RISCV_UNKNOWN_VERSION -1 +#define ZCMP_SP_ALIGNMENT 16 struct riscv_elf_params { diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a4161420128..a9f0b90af71 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1253,6 +1253,125 @@ flt_lookup (float f, const float *array, size_t size, unsigned *regnop) return false; } +/* Map ra and s-register to [4,15], so that we can check if the + reg2 in register list reg1-reg2 or single reg2 is valid or not, + and obtain the corresponding reg_list value. + + ra - 4 + s0 - 5 + s1 - 6 + .... + s10 - 0 (invalid) + s11 - 15. */ + +static int +regno_to_reg_list (unsigned regno) +{ + if (regno == X_RA) + return 4; + else if (regno == X_S0 || regno == X_S1) + return 5 + regno - X_S0; + else if (regno >= X_S2 && regno < X_S10) + return 7 + regno - X_S2; + else if (regno == X_S11) + return 15; + + return 0; /* invalid symbol */ +} + +/* Parse register list, and the parsed reg_list value is stored in reg_list + argument. + + If ABI register names are used (e.g. ra and s0), the register + list could be "{ra}", "{ra, s0}", "{ra, s0-sN}", where 0 < N < 10 or + N == 11. + + If numeric register names are used (e.g. x1 and x8), the register list + could be "{x1}", "{x1,x8}", "{x1,x8-x9}", "{x1,x8-x9,x18}" and + "{x1,x8-x9,x18-xN}", where 19 < N < 25 or N == 27. + + It will fail if numeric register names and ABI register names are used + at the same time. +*/ + +static bool +reglist_lookup (char **s, unsigned *reg_list) +{ + unsigned regno = 0; + unsigned regnum = 0; + char *reglist = strdup (*s); + char *regname[3]; + + if (reglist == NULL) + return false; + + reglist = strtok (reglist, "}"); + for(reglist = strtok (reglist, ",");reglist;reglist = strtok(NULL, ",")){ + regname[regnum] = reglist; + regnum++; + } + + /* Use to check if the register format is xreg. */ + bool use_xreg = **s == 'x'; + + /* The first register in the register list should be ra. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*reg_list = regno_to_reg_list (regno)) /* update reg_list */ + || regno != X_RA) + return false; + + if (regnum == 1) + return true; + + /* Do not use numeric and abi names at the same time. */ + if ((*++*s != 'x') && use_xreg) + return false; + /* Reg1 should be s0 or its numeric names x8. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*reg_list = regno_to_reg_list (regno)) + || regno != X_S0) + return false; + + if (strlen (regname[1]) == 2) + return true; + + if ((*++*s != 'x') && use_xreg) + return false; + /* Reg2 is x9 if the numeric name is used, otherwise, + it could be any other sN register, where N > 0. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*reg_list = regno_to_reg_list (regno)) + || regno <= X_S0 + || (use_xreg && regno != X_S1)) + return false; + + if (regnum == 2) + return true; + + if (regnum == 3 && use_xreg) { + if ((*++*s != 'x') && use_xreg) + return false; + /* Reg3 should be s2. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*reg_list = regno_to_reg_list (regno)) + || regno != X_S2) + return false; + if(strlen(regname[2]) == 3) + return true; + if ((*++*s != 'x') && use_xreg) + return false; + /* Reg4 could be any other sN register, where N > 1. */ + if (!reg_lookup (s, RCLASS_GPR, ®no) + || !(*reg_list = regno_to_reg_list (regno)) + || regno <= X_S2) + return false; + return true; + } + + free (reglist); + return false; +} + #define USE_BITS(mask,shift) (used_bits |= ((insn_t)(mask) << (shift))) #define USE_IMM(n, s) \ (used_bits |= ((insn_t)((1ull<': USE_BITS (OP_MASK_SHAMT, OP_SH_SHAMT); break; case 'A': break; /* Macro operand, must be symbol. */ @@ -1449,6 +1570,10 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; /* halfword immediate operators, load/store halfword insns. */ case 'b': used_bits |= ENCODE_ZCB_BYTE_UIMM (-1U); break; + /* immediate offset operand for cm.push and cm.pop. */ + case 'p': used_bits |= ENCODE_ZCMP_SPIMM (-1U); break; + /* register list operand for cm.push and cm.pop. */ + case 'r': USE_BITS (OP_MASK_REG_LIST, OP_SH_REG_LIST); break; case 'f': break; default: goto unknown_validate_operand; @@ -3201,6 +3326,8 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, case ')': case '[': case ']': + case '{': + case '}': if (*asarg++ == *oparg) continue; break; @@ -3656,6 +3783,27 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, break; ip->insn_opcode |= ENCODE_ZCB_BYTE_UIMM (imm_expr->X_add_number); goto rvc_imm_done; + case 'r': + /* we use regno to store reglist value here. */ + if (!reglist_lookup (&asarg, ®no)) + break; + INSERT_OPERAND (REG_LIST, *ip, regno); + continue; + case 'p': + if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) + || imm_expr->X_op != O_constant) + break; + /* convert stack adjust of cm.push to a positive offset. */ + if (ip->insn_mo->match == MATCH_CM_PUSH) + imm_expr->X_add_number *= -1; + /* subtract base stack adjust and get spimm. */ + imm_expr->X_add_number -= + riscv_get_sp_base (ip->insn_opcode, *riscv_rps_as.xlen); + if (!VALID_ZCMP_SPIMM (imm_expr->X_add_number)) + break; + ip->insn_opcode |= + ENCODE_ZCMP_SPIMM (imm_expr->X_add_number); + goto rvc_imm_done; case 'f': /* Operand for matching immediate 255. */ if (my_getSmallExpression (imm_expr, imm_reloc, asarg, p) || imm_expr->X_op != O_constant diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d new file mode 100644 index 00000000000..84ecf263c54 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.d @@ -0,0 +1,3 @@ +#as: -march=rv64i_zcmp +#source: zcmp-push-pop-fail.s +#error_output: zcmp-push-pop-fail.l diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l new file mode 100644 index 00000000000..955e495d5bb --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.l @@ -0,0 +1,9 @@ +.*: Assembler messages: +.*: Error: illegal operands `cm.push \{a0\},-64' +.*: Error: illegal operands `cm.pop \{ra,s1\},-64' +.*: Error: illegal operands `cm.popret \{ra,s2-s3\},-64' +.*: Error: illegal operands `cm.popretz \{ra,s0-s10\},-112' +.*: Error: illegal operands `cm.push \{ra\},0' +.*: Error: illegal operands `cm.pop \{ra,s0\},-80' +.*: Error: illegal operands `cm.popret \{ra,s0-s1\},-15' +.*: Error: illegal operands `cm.popretz \{ra,s0-s11\},-165' diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s new file mode 100644 index 00000000000..0e8df5800dd --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop-fail.s @@ -0,0 +1,13 @@ +target: + + # reg_list + cm.push {a0}, -64 + cm.pop {ra, s1}, -64 + cm.popret {ra, s2-s3}, -64 + cm.popretz {ra, s0-s10}, -112 + + # spimm + cm.push {ra}, 0 + cm.pop {ra, s0}, -80 + cm.popret {ra, s0-s1}, -15 + cm.popretz {ra, s0-s11}, -165 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.d b/gas/testsuite/gas/riscv/zcmp-push-pop.d new file mode 100644 index 00000000000..e21295051ec --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.d @@ -0,0 +1,154 @@ +#as: -march=rv64i_zcmp +#source: zcmp-push-pop.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b85e[ ]+cm.push[ ]+\{ra,s0\},-64 +[ ]*[0-9a-f]+:[ ]+b86a[ ]+cm.push[ ]+\{ra,s0-s1\},-64 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b8da[ ]+cm.push[ ]+\{ra,s0-s8\},-112 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11},-112 +[ ]*[0-9a-f]+:[ ]+b842[ ]+cm.push[ ]+\{ra\},-16 +[ ]*[0-9a-f]+:[ ]+b846[ ]+cm.push[ ]+\{ra\},-32 +[ ]*[0-9a-f]+:[ ]+b84e[ ]+cm.push[ ]+\{ra\},-64 +[ ]*[0-9a-f]+:[ ]+b872[ ]+cm.push[ ]+\{ra,s0-s2\},-32 +[ ]*[0-9a-f]+:[ ]+b87a[ ]+cm.push[ ]+\{ra,s0-s2\},-64 +[ ]*[0-9a-f]+:[ ]+b87e[ ]+cm.push[ ]+\{ra,s0-s2\},-80 +[ ]*[0-9a-f]+:[ ]+b882[ ]+cm.push[ ]+\{ra,s0-s3\},-48 +[ ]*[0-9a-f]+:[ ]+b886[ ]+cm.push[ ]+\{ra,s0-s3\},-64 +[ ]*[0-9a-f]+:[ ]+b88e[ ]+cm.push[ ]+\{ra,s0-s3\},-96 +[ ]*[0-9a-f]+:[ ]+b8b2[ ]+cm.push[ ]+\{ra,s0-s6\},-64 +[ ]*[0-9a-f]+:[ ]+b8b6[ ]+cm.push[ ]+\{ra,s0-s6\},-80 +[ ]*[0-9a-f]+:[ ]+b8be[ ]+cm.push[ ]+\{ra,s0-s6\},-112 +[ ]*[0-9a-f]+:[ ]+b8c2[ ]+cm.push[ ]+\{ra,s0-s7\},-80 +[ ]*[0-9a-f]+:[ ]+b8c6[ ]+cm.push[ ]+\{ra,s0-s7\},-96 +[ ]*[0-9a-f]+:[ ]+b8ce[ ]+cm.push[ ]+\{ra,s0-s7\},-128 +[ ]*[0-9a-f]+:[ ]+b8e2[ ]+cm.push[ ]+\{ra,s0-s9\},-96 +[ ]*[0-9a-f]+:[ ]+b8e6[ ]+cm.push[ ]+\{ra,s0-s9\},-112 +[ ]*[0-9a-f]+:[ ]+b8ee[ ]+cm.push[ ]+\{ra,s0-s9\},-144 +[ ]*[0-9a-f]+:[ ]+b8f2[ ]+cm.push[ ]+\{ra,s0-s11\},-112 +[ ]*[0-9a-f]+:[ ]+b8f6[ ]+cm.push[ ]+\{ra,s0-s11\},-128 +[ ]*[0-9a-f]+:[ ]+b8fa[ ]+cm.push[ ]+\{ra,s0-s11\},-144 +[ ]*[0-9a-f]+:[ ]+b8fe[ ]+cm.push[ ]+\{ra,s0-s11\},-160 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba5e[ ]+cm.pop[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+ba6a[ ]+cm.pop[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bada[ ]+cm.pop[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+ba42[ ]+cm.pop[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+ba46[ ]+cm.pop[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+ba4e[ ]+cm.pop[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+ba72[ ]+cm.pop[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+ba7a[ ]+cm.pop[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+ba7e[ ]+cm.pop[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+ba82[ ]+cm.pop[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+ba86[ ]+cm.pop[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+ba8e[ ]+cm.pop[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bab2[ ]+cm.pop[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bab6[ ]+cm.pop[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+babe[ ]+cm.pop[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bac2[ ]+cm.pop[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bac6[ ]+cm.pop[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bace[ ]+cm.pop[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bae2[ ]+cm.pop[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bae6[ ]+cm.pop[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+baee[ ]+cm.pop[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+baf2[ ]+cm.pop[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+baf6[ ]+cm.pop[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bafa[ ]+cm.pop[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bafe[ ]+cm.pop[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be5e[ ]+cm.popret[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+be6a[ ]+cm.popret[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+beda[ ]+cm.popret[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+be42[ ]+cm.popret[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+be46[ ]+cm.popret[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+be4e[ ]+cm.popret[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+be72[ ]+cm.popret[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+be7a[ ]+cm.popret[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+be7e[ ]+cm.popret[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+be82[ ]+cm.popret[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+be86[ ]+cm.popret[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+be8e[ ]+cm.popret[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+beb2[ ]+cm.popret[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+beb6[ ]+cm.popret[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bebe[ ]+cm.popret[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bec2[ ]+cm.popret[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bec6[ ]+cm.popret[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bece[ ]+cm.popret[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bee2[ ]+cm.popret[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bee6[ ]+cm.popret[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+beee[ ]+cm.popret[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bef2[ ]+cm.popret[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bef6[ ]+cm.popret[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+befa[ ]+cm.popret[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+befe[ ]+cm.popret[ ]+\{ra,s0-s11\},160 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc5e[ ]+cm.popretz[ ]+\{ra,s0\},64 +[ ]*[0-9a-f]+:[ ]+bc6a[ ]+cm.popretz[ ]+\{ra,s0-s1\},64 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bcda[ ]+cm.popretz[ ]+\{ra,s0-s8\},112 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11},112 +[ ]*[0-9a-f]+:[ ]+bc42[ ]+cm.popretz[ ]+\{ra\},16 +[ ]*[0-9a-f]+:[ ]+bc46[ ]+cm.popretz[ ]+\{ra\},32 +[ ]*[0-9a-f]+:[ ]+bc4e[ ]+cm.popretz[ ]+\{ra\},64 +[ ]*[0-9a-f]+:[ ]+bc72[ ]+cm.popretz[ ]+\{ra,s0-s2\},32 +[ ]*[0-9a-f]+:[ ]+bc7a[ ]+cm.popretz[ ]+\{ra,s0-s2\},64 +[ ]*[0-9a-f]+:[ ]+bc7e[ ]+cm.popretz[ ]+\{ra,s0-s2\},80 +[ ]*[0-9a-f]+:[ ]+bc82[ ]+cm.popretz[ ]+\{ra,s0-s3\},48 +[ ]*[0-9a-f]+:[ ]+bc86[ ]+cm.popretz[ ]+\{ra,s0-s3\},64 +[ ]*[0-9a-f]+:[ ]+bc8e[ ]+cm.popretz[ ]+\{ra,s0-s3\},96 +[ ]*[0-9a-f]+:[ ]+bcb2[ ]+cm.popretz[ ]+\{ra,s0-s6\},64 +[ ]*[0-9a-f]+:[ ]+bcb6[ ]+cm.popretz[ ]+\{ra,s0-s6\},80 +[ ]*[0-9a-f]+:[ ]+bcbe[ ]+cm.popretz[ ]+\{ra,s0-s6\},112 +[ ]*[0-9a-f]+:[ ]+bcc2[ ]+cm.popretz[ ]+\{ra,s0-s7\},80 +[ ]*[0-9a-f]+:[ ]+bcc6[ ]+cm.popretz[ ]+\{ra,s0-s7\},96 +[ ]*[0-9a-f]+:[ ]+bcce[ ]+cm.popretz[ ]+\{ra,s0-s7\},128 +[ ]*[0-9a-f]+:[ ]+bce2[ ]+cm.popretz[ ]+\{ra,s0-s9\},96 +[ ]*[0-9a-f]+:[ ]+bce6[ ]+cm.popretz[ ]+\{ra,s0-s9\},112 +[ ]*[0-9a-f]+:[ ]+bcee[ ]+cm.popretz[ ]+\{ra,s0-s9\},144 +[ ]*[0-9a-f]+:[ ]+bcf2[ ]+cm.popretz[ ]+\{ra,s0-s11\},112 +[ ]*[0-9a-f]+:[ ]+bcf6[ ]+cm.popretz[ ]+\{ra,s0-s11\},128 +[ ]*[0-9a-f]+:[ ]+bcfa[ ]+cm.popretz[ ]+\{ra,s0-s11\},144 +[ ]*[0-9a-f]+:[ ]+bcfe[ ]+cm.popretz[ ]+\{ra,s0-s11\},160 diff --git a/gas/testsuite/gas/riscv/zcmp-push-pop.s b/gas/testsuite/gas/riscv/zcmp-push-pop.s new file mode 100644 index 00000000000..dc441bc2776 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-push-pop.s @@ -0,0 +1,162 @@ +target: + + # push + # abi names + cm.push {ra}, -64 + cm.push {ra, s0}, -64 + cm.push {ra, s0-s1}, -64 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s8}, -112 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s11}, -112 + # numeric names + cm.push {x1}, -64 + cm.push {x1, x8}, -64 + cm.push {x1, x8-x9}, -64 + cm.push {x1, x8-x9, x18}, -64 + cm.push {x1, x8-x9, x18-x24}, -112 + cm.push {x1, x8-x9, x18-x25}, -112 + cm.push {x1, x8-x9, x18-x27}, -112 + # spimm + cm.push {ra}, -16 + cm.push {ra}, -32 + cm.push {ra}, -64 + cm.push {ra, s0-s2}, -32 + cm.push {ra, s0-s2}, -64 + cm.push {ra, s0-s2}, -80 + cm.push {ra, s0-s3}, -48 + cm.push {ra, s0-s3}, -64 + cm.push {ra, s0-s3}, -96 + cm.push {ra, s0-s6}, -64 + cm.push {ra, s0-s6}, -80 + cm.push {ra, s0-s6}, -112 + cm.push {ra, s0-s7}, -80 + cm.push {ra, s0-s7}, -96 + cm.push {ra, s0-s7}, -128 + cm.push {ra, s0-s9}, -96 + cm.push {ra, s0-s9}, -112 + cm.push {ra, s0-s9}, -144 + cm.push {ra, s0-s11}, -112 + cm.push {ra, s0-s11}, -128 + cm.push {ra, s0-s11}, -144 + cm.push {ra, s0-s11}, -160 + # pop + # abi names + cm.pop {ra}, 64 + cm.pop {ra, s0}, 64 + cm.pop {ra, s0-s1}, 64 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s8}, 112 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s11}, 112 + # numeric names + cm.pop {x1}, 64 + cm.pop {x1, x8}, 64 + cm.pop {x1, x8-x9}, 64 + cm.pop {x1, x8-x9, x18}, 64 + cm.pop {x1, x8-x9, x18-x24}, 112 + cm.pop {x1, x8-x9, x18-x25}, 112 + cm.pop {x1, x8-x9, x18-x27}, 112 + # spimm + cm.pop {ra}, 16 + cm.pop {ra}, 32 + cm.pop {ra}, 64 + cm.pop {ra, s0-s2}, 32 + cm.pop {ra, s0-s2}, 64 + cm.pop {ra, s0-s2}, 80 + cm.pop {ra, s0-s3}, 48 + cm.pop {ra, s0-s3}, 64 + cm.pop {ra, s0-s3}, 96 + cm.pop {ra, s0-s6}, 64 + cm.pop {ra, s0-s6}, 80 + cm.pop {ra, s0-s6}, 112 + cm.pop {ra, s0-s7}, 80 + cm.pop {ra, s0-s7}, 96 + cm.pop {ra, s0-s7}, 128 + cm.pop {ra, s0-s9}, 96 + cm.pop {ra, s0-s9}, 112 + cm.pop {ra, s0-s9}, 144 + cm.pop {ra, s0-s11}, 112 + cm.pop {ra, s0-s11}, 128 + cm.pop {ra, s0-s11}, 144 + cm.pop {ra, s0-s11}, 160 + # popret + # abi names + cm.popret {ra}, 64 + cm.popret {ra, s0}, 64 + cm.popret {ra, s0-s1}, 64 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s8}, 112 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s11}, 112 + # numeric names + cm.popret {x1}, 64 + cm.popret {x1, x8}, 64 + cm.popret {x1, x8-x9}, 64 + cm.popret {x1, x8-x9, x18}, 64 + cm.popret {x1, x8-x9, x18-x24}, 112 + cm.popret {x1, x8-x9, x18-x25}, 112 + cm.popret {x1, x8-x9, x18-x27}, 112 + # spimm + cm.popret {ra}, 16 + cm.popret {ra}, 32 + cm.popret {ra}, 64 + cm.popret {ra, s0-s2}, 32 + cm.popret {ra, s0-s2}, 64 + cm.popret {ra, s0-s2}, 80 + cm.popret {ra, s0-s3}, 48 + cm.popret {ra, s0-s3}, 64 + cm.popret {ra, s0-s3}, 96 + cm.popret {ra, s0-s6}, 64 + cm.popret {ra, s0-s6}, 80 + cm.popret {ra, s0-s6}, 112 + cm.popret {ra, s0-s7}, 80 + cm.popret {ra, s0-s7}, 96 + cm.popret {ra, s0-s7}, 128 + cm.popret {ra, s0-s9}, 96 + cm.popret {ra, s0-s9}, 112 + cm.popret {ra, s0-s9}, 144 + cm.popret {ra, s0-s11}, 112 + cm.popret {ra, s0-s11}, 128 + cm.popret {ra, s0-s11}, 144 + cm.popret {ra, s0-s11}, 160 + # popretz + # abi names + cm.popretz {ra}, 64 + cm.popretz {ra, s0}, 64 + cm.popretz {ra, s0-s1}, 64 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s8}, 112 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s11}, 112 + # numeric names + cm.popretz {x1}, 64 + cm.popretz {x1, x8}, 64 + cm.popretz {x1, x8-x9}, 64 + cm.popretz {x1, x8-x9, x18}, 64 + cm.popretz {x1, x8-x9, x18-x24}, 112 + cm.popretz {x1, x8-x9, x18-x25}, 112 + cm.popretz {x1, x8-x9, x18-x27}, 112 + # spimm + cm.popretz {ra}, 16 + cm.popretz {ra}, 32 + cm.popretz {ra}, 64 + cm.popretz {ra, s0-s2}, 32 + cm.popretz {ra, s0-s2}, 64 + cm.popretz {ra, s0-s2}, 80 + cm.popretz {ra, s0-s3}, 48 + cm.popretz {ra, s0-s3}, 64 + cm.popretz {ra, s0-s3}, 96 + cm.popretz {ra, s0-s6}, 64 + cm.popretz {ra, s0-s6}, 80 + cm.popretz {ra, s0-s6}, 112 + cm.popretz {ra, s0-s7}, 80 + cm.popretz {ra, s0-s7}, 96 + cm.popretz {ra, s0-s7}, 128 + cm.popretz {ra, s0-s9}, 96 + cm.popretz {ra, s0-s9}, 112 + cm.popretz {ra, s0-s9}, 144 + cm.popretz {ra, s0-s11}, 112 + cm.popretz {ra, s0-s11}, 128 + cm.popretz {ra, s0-s11}, 144 + cm.popretz {ra, s0-s11}, 160 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index e77b49a6298..d0f93b11f01 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2235,6 +2235,15 @@ #define MASK_C_NOT 0xfc7f #define MATCH_C_MUL 0x9c41 #define MASK_C_MUL 0xfc63 +/* Zcmp instructions. */ +#define MATCH_CM_PUSH 0xb802 +#define MASK_CM_PUSH 0xff03 +#define MATCH_CM_POP 0xba02 +#define MASK_CM_POP 0xff03 +#define MATCH_CM_POPRET 0xbe02 +#define MASK_CM_POPRET 0xff03 +#define MATCH_CM_POPRETZ 0xbc02 +#define MASK_CM_POPRETZ 0xff03 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3916,6 +3925,11 @@ DECLARE_INSN(c_lhu, MATCH_C_LHU, MASK_C_LHU) DECLARE_INSN(c_lh, MATCH_C_LH, MASK_C_LH) DECLARE_INSN(c_sb, MATCH_C_SB, MASK_C_SB) DECLARE_INSN(c_sh, MATCH_C_SH, MASK_C_SH) +/* Zcmp instructions. */ +DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) +DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) +DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) +DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index adea7dbc794..630c9cf13ff 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -112,6 +112,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1)) #define EXTRACT_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 5, 1) << 1) +#define EXTRACT_ZCMP_SPIMM(x) \ + (RV_X(x, 2, 2) << 4) /* Vendor-specific (CORE-V) extract macros. */ #define EXTRACT_CV_IS2_UIMM5(x) \ (RV_X(x, 20, 5)) @@ -168,6 +170,8 @@ static inline unsigned int riscv_insn_length (insn_t insn) ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5)) #define ENCODE_ZCB_HALFWORD_UIMM(x) \ (RV_X(x, 1, 1) << 5) +#define ENCODE_ZCMP_SPIMM(x) \ + (RV_X(x, 4, 2) << 2) /* Vendor-specific (CORE-V) encode macros. */ #define ENCODE_CV_IS2_UIMM5(x) \ (RV_X(x, 0, 5) << 20) @@ -200,6 +204,7 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x)) #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x)) #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x)) +#define VALID_ZCMP_SPIMM(x) (EXTRACT_ZCMP_SPIMM(ENCODE_ZCMP_SPIMM(x)) == (x)) #define RISCV_RTYPE(insn, rd, rs1, rs2) \ ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2)) @@ -337,6 +342,11 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_XTHEADVTYPE_RES 0xf #define OP_SH_XTHEADVTYPE_RES 7 +/* Zc fields. */ +#define OP_MASK_REG_LIST 0xf +#define OP_SH_REG_LIST 4 +#define ZCMP_SP_ALIGNMENT 16 + #define NVECR 32 #define NVECM 1 @@ -355,6 +365,11 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define X_T0 5 #define X_T1 6 #define X_T2 7 +#define X_S0 8 +#define X_S1 9 +#define X_S2 18 +#define X_S10 26 +#define X_S11 27 #define X_T3 28 #define NGPR 32 @@ -464,6 +479,7 @@ enum riscv_insn_class INSN_CLASS_ZCB_AND_ZBA, INSN_CLASS_ZCB_AND_ZBB, INSN_CLASS_ZCB_AND_ZMMUL, + INSN_CLASS_ZCMP, INSN_CLASS_SVINVAL, INSN_CLASS_ZICBOM, INSN_CLASS_ZICBOP, @@ -582,6 +598,19 @@ enum M_NUM_MACROS }; +/* get sp base adjustment */ + +static inline unsigned int +riscv_get_sp_base (insn_t opcode, unsigned int xlen) +{ + unsigned reg_size = xlen / 8; + unsigned reg_list = EXTRACT_BITS (opcode, OP_MASK_REG_LIST, OP_SH_REG_LIST); + + unsigned min_sp_adj = (reg_list - 3) * reg_size + (reg_list == 15 ? reg_size : 0); + return ((min_sp_adj / ZCMP_SP_ALIGNMENT) + (min_sp_adj % ZCMP_SP_ALIGNMENT != 0)) + * ZCMP_SP_ALIGNMENT; +} + /* The mapping symbol states. */ enum riscv_seg_mstate { diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index 3019b9a5130..f1a7c975038 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -75,6 +75,8 @@ static const char (*riscv_fpr_names)[NRC]; /* If set, disassemble as most general instruction. */ static bool no_aliases = false; +/* If set, disassemble numeric register names instead of ABI names. */ +static int numeric = false; /* Set default RISC-V disassembler options. */ @@ -84,6 +86,7 @@ set_default_riscv_dis_options (void) riscv_gpr_names = riscv_gpr_names_abi; riscv_fpr_names = riscv_fpr_names_abi; no_aliases = false; + numeric = false; } /* Parse RISC-V disassembler option (without arguments). */ @@ -97,6 +100,7 @@ parse_riscv_dis_option_without_args (const char *option) { riscv_gpr_names = riscv_gpr_names_numeric; riscv_fpr_names = riscv_fpr_names_numeric; + numeric = true; } else return false; @@ -215,6 +219,50 @@ maybe_print_address (struct riscv_private_data *pd, int base_reg, int offset, pd->print_addr = (bfd_vma)(uint32_t)pd->print_addr; } +/* Get Zcmp reg_list field. */ + +static void +print_reg_list (disassemble_info *info, insn_t l) +{ + unsigned reg_list = (int)EXTRACT_OPERAND (REG_LIST, l); + unsigned r_start = numeric ? X_S2 : X_S0; + info->fprintf_func (info->stream, "%s", riscv_gpr_names[X_RA]); + + if (reg_list == 5) + info->fprintf_func (info->stream, ",%s", riscv_gpr_names[X_S0]); + else if (reg_list == 6 || (numeric && reg_list > 6)) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[X_S0], + riscv_gpr_names[X_S1]); + + if (reg_list == 15) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[X_S11]); + else if (reg_list == 7 && numeric) + info->fprintf_func (info->stream, ",%s", + riscv_gpr_names[X_S2]); + else if (reg_list > 6) + info->fprintf_func (info->stream, ",%s-%s", + riscv_gpr_names[r_start], + riscv_gpr_names[reg_list + 11]); +} + +/* Get Zcmp sp adjustment immediate. */ + +static int +riscv_get_spimm (insn_t l) +{ + int spimm = riscv_get_sp_base(l, *riscv_rps_dis.xlen); + + spimm += EXTRACT_ZCMP_SPIMM (l); + + if (((l ^ MATCH_CM_PUSH) & MASK_CM_PUSH) == 0) + spimm *= -1; + + return spimm; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -420,6 +468,8 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case ')': case '[': case ']': + case '{': + case '}': print (info->stream, dis_style_text, "%c", *oparg); break; @@ -634,6 +684,13 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_HALFWORD_UIMM (l)); break; + case 'r': + print_reg_list (info, l); + break; + case 'p': + print (info->stream, dis_style_immediate, "%d", + riscv_get_spimm (l)); + break; default: goto undefined_modifier; } diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index fdd05ac75dc..3da75db6db1 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -1993,6 +1993,12 @@ const struct riscv_opcode riscv_opcodes[] = {"c.zext.b", 0, INSN_CLASS_ZCB, "Cs", MATCH_C_ZEXT_B, MASK_C_ZEXT_B, match_opcode, 0 }, {"c.sext.w", 64, INSN_CLASS_ZCB, "d", MATCH_C_ADDIW, MASK_C_ADDIW|MASK_RVC_IMM, match_rd_nonzero, INSN_ALIAS }, +/* Zcmp instructions. */ +{"cm.push", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_PUSH, MASK_CM_PUSH, match_opcode, 0 }, +{"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, +{"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, +{"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, + /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS }, {"csrwi", 0, INSN_CLASS_ZICSR, "E,Z", MATCH_CSRRWI, MASK_CSRRWI|MASK_RD, match_opcode, INSN_ALIAS }, From patchwork Wed Jan 24 09:37:25 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 191447 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp876191dyi; Wed, 24 Jan 2024 01:38:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IEfQLrjnmpbY0tFYH3WQuBTJbMwCtkeMy2JOMI0K7sf6HkmBRqD2bJfiK61eJiYnPbVwifi X-Received: by 2002:a05:620a:2f5:b0:783:699b:7ff7 with SMTP id a21-20020a05620a02f500b00783699b7ff7mr7103616qko.34.1706089116643; Wed, 24 Jan 2024 01:38:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706089116; cv=pass; d=google.com; s=arc-20160816; b=bsSbGoVv/e7UzrojvCg1Nr9JhuHqhLudkQiOQOkgM7zsBevtGsQwcgsLcG7nIQd54/ uVVW96YgzM792vKPDmoPnoWi6uF/pn2b7jaBoXteqFyiGrlD4P4SwCGTtufwj/joDrEA kYaW1nR36WiAuWqRgNWV2OL0FqHJ8iFskztT+ZE6pNz2VFbrEacyqZ43c3Ch7xsRHFDT ugZVRMZItja5wb01KMlbG6Ou/8ZgZI4sVERfhiNZwAJQ4vUXUQ0Yd8m7Qelipk/hhR0/ sYcg8nKhZW5LphetgiSi5d4TiYNW8GMqaRfsBAOeEdSBa/p/8mwk4YFbHMZXQzlMf2rN wL7Q== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:arc-filter:dmarc-filter:delivered-to; bh=hLzlwJC9HSlHyRtRUfnmiz2BOvFZcrmOlON58zaXuCY=; fh=lBAoCEpqDOXG/zBsuf22J7h1PVF94nsYbMZP1Xcckc8=; b=Nuor9UzaGvZdxTBJI5VP0xdGfZclhZK4uTser1L8gbpZ4LtYzeRuzwSa9517emwW5u LqJZnfCGFfvUAXT6hCy4ZMeyqkhriOQygcC1+3W7vEiQdBbyCLY1xd1NIjTLe60Lc5ND PiaVIBkzDXlSHlwYgFq8YU351pFyeUyKF9DSncUSiNumfDi0tagSZUMnROi8wEGQWuOf egYbHV/GRfx8n9hBsHO9wJS6ipEfGDts7n2g7/XFGNik+MHDd+IyC6vBfptUDGMan2L8 VXqbjqNDW5rRv6IG9nTqCGm7Xf1OEG0wCMVYjSJEUO4g7rP9GLxU0Dh++TtMLuVwhL1z CZcw== ARC-Authentication-Results: i=2; mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (server2.sourceware.org. [2620:52:3:1:0:246e:9693:128c]) by mx.google.com with ESMTPS id qr12-20020a05620a390c00b007832016a729si10561895qkn.411.2024.01.24.01.38.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 24 Jan 2024 01:38:36 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) client-ip=2620:52:3:1:0:246e:9693:128c; Authentication-Results: mx.google.com; arc=pass (i=1); spf=pass (google.com: domain of binutils-bounces+ouuuleilei=gmail.com@sourceware.org designates 2620:52:3:1:0:246e:9693:128c as permitted sender) smtp.mailfrom="binutils-bounces+ouuuleilei=gmail.com@sourceware.org" Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 492D238582A6 for ; Wed, 24 Jan 2024 09:38:36 +0000 (GMT) X-Original-To: binutils@sourceware.org Delivered-To: binutils@sourceware.org Received: from cstnet.cn (smtp81.cstnet.cn [159.226.251.81]) by sourceware.org (Postfix) with ESMTPS id 7205C3858410 for ; Wed, 24 Jan 2024 09:38:17 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7205C3858410 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 7205C3858410 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=159.226.251.81 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706089100; cv=none; b=jgiFxokW6+jDvJN4fTvA5AUxXwr5u0u9v835cbvNaXjQd9b4MIQM0e1vUnECGuZEq/jOc+P7Qu2F5stOBD6oIrBpIRAmc6tcmQeIk+GzjLSkIygQrt/Zxz4auvqMjH9srtyKizq8fWCgGj8bL9ea+mX/G7R2mQkVPaopGHOjUGI= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1706089100; c=relaxed/simple; bh=9lbZBFKytN7tQxEfibItMHWhWPCj8AILaXkEUi/4JKo=; h=From:To:Subject:Date:Message-Id:MIME-Version; b=SBSz0hwaN3XRxw7ULUa6mGY4eCvsnR0hMoMfBQZ+wiwC3YIit8jQW9nvSNblOKYxSv1kSYFG2PmY8+PiA9VuqD7dDErRfWhVMivJU8fxRjKXFUKCKZl3OHewnATej6VAR/UATw5MZdssmoubxIo2qVI7ARdyRb3BpLYXih67z1I= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from localhost.localdomain (unknown [47.113.87.88]) by APP-03 (Coremail) with SMTP id rQCowACnrjZ42rBlWy5ICQ--.19636S3; Wed, 24 Jan 2024 17:38:02 +0800 (CST) From: Jiawei To: binutils@sourceware.org Cc: nelson@rivosinc.com, kito.cheng@sifive.com, palmer@dabbelt.com, jbeulich@suse.com, research_trasio@irq.a4lg.com, christoph.muellner@vrull.eu, jeremy.bennett@embecosm.com, nandni.jamnadas@embecosm.com, mary.bennett@embecosm.com, charlie.keaney@embecosm.com, simon.cook@embecosm.com, sinan.lin@linux.alibaba.com, gaofei@eswincomputing.com, fujin.zhao@foxmail.com, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn, shiyulong@iscas.ac.cn, chenyixuan@iscas.ac.cn, Jiawei Subject: [PATCH v4 2/2] RISC-V: Support Zcmp cm.mv instructions. Date: Wed, 24 Jan 2024 17:37:25 +0800 Message-Id: <20240124093725.567220-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240124093725.567220-1-jiawei@iscas.ac.cn> References: <20240124093725.567220-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: rQCowACnrjZ42rBlWy5ICQ--.19636S3 X-Coremail-Antispam: 1UD129KBjvJXoW3Xry8AFW3Ww1xGF4UZw48tFb_yoWDJry5pF 45Cr4Y9an5JFZ7Gr4SgFyUur43J397G34Yyw42ga17Z34xXrWfXa95tw13tFZ5WFWa9r13 uw4Yvr1093WUJFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F4UJw A2z4x0Y4vEx4A2jsIE14v26F4UJVW0owA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_GcCE3s1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lc2xSY4AK67A8MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I 3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxV W8ZVWrXwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8I cVCY1x0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZE Xa7sREVyxtUUUUU== X-Originating-IP: [47.113.87.88] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiDAYGAGWw1wMOzQAAsO X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: binutils@sourceware.org X-Mailman-Version: 2.1.30 Precedence: list List-Id: Binutils mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: binutils-bounces+ouuuleilei=gmail.com@sourceware.org X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788964101583965900 X-GMAIL-MSGID: 1788964101583965900 This patch supports Zcmp instruction 'cm.mva01s' and 'cm.mvsa01'. All disassemble instructions use the sreg format. Co-Authored by: Charlie Keaney Co-Authored by: Mary Bennett Co-Authored by: Nandni Jamnadas Co-Authored by: Sinan Lin Co-Authored by: Simon Cook Co-Authored by: Shihua Liao Co-Authored by: Yulong Shi gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): New operators. (riscv_ip): Ditto. * testsuite/gas/riscv/zcmp-mv.d: New test. * testsuite/gas/riscv/zcmp-mv.s: New test. include/ChangeLog: * opcode/riscv-opc.h (MATCH_CM_MVA01S): New opcode. (MASK_CM_MVA01S): New mask. (MATCH_CM_MVSA01): New opcode. (MASK_CM_MVSA01): New mask. (DECLARE_INSN): New declarations. * opcode/riscv.h (OP_MASK_SREG1): New mask. (OP_SH_SREG1): New operand code. (OP_MASK_SREG2): New mask. (OP_SH_SREG2): New operand code. (X_A0): New reg number. (X_A1): Ditto. (X_S7): Ditto. (RISCV_SREG_0_7): New macro function. opcodes/ChangeLog: * riscv-dis.c (riscv_zcmp_get_sregno): New function. (print_insn_args): New operators. * riscv-opc.c (match_sreg1_not_eq_sreg2): New match function. --- gas/config/tc-riscv.c | 15 +++++++++++++++ gas/testsuite/gas/riscv/zcmp-mv.d | 26 ++++++++++++++++++++++++++ gas/testsuite/gas/riscv/zcmp-mv.s | 21 +++++++++++++++++++++ include/opcode/riscv-opc.h | 6 ++++++ include/opcode/riscv.h | 12 ++++++++++++ opcodes/riscv-dis.c | 19 +++++++++++++++++++ opcodes/riscv-opc.c | 9 +++++++++ 7 files changed, 108 insertions(+) create mode 100644 gas/testsuite/gas/riscv/zcmp-mv.d create mode 100644 gas/testsuite/gas/riscv/zcmp-mv.s diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c index a9f0b90af71..569bbbac3fd 100644 --- a/gas/config/tc-riscv.c +++ b/gas/config/tc-riscv.c @@ -1566,6 +1566,9 @@ validate_riscv_insn (const struct riscv_opcode *opc, int length) case 'c': switch (*++oparg) { + /* sreg operators in cm.mvsa01 and cm.mva01s. */ + case '1': USE_BITS (OP_MASK_SREG1, OP_SH_SREG1); break; + case '2': USE_BITS (OP_MASK_SREG2, OP_SH_SREG2); break; /* byte immediate operators, load/store byte insns. */ case 'h': used_bits |= ENCODE_ZCB_HALFWORD_UIMM (-1U); break; /* halfword immediate operators, load/store halfword insns. */ @@ -3814,6 +3817,18 @@ riscv_ip (char *str, struct riscv_cl_insn *ip, expressionS *imm_expr, asarg = expr_parse_end; imm_expr->X_op = O_absent; continue; + case '1': + if (!reg_lookup (&asarg, RCLASS_GPR, ®no) + || !RISCV_SREG_0_7 (regno)) + break; + INSERT_OPERAND (SREG1, *ip, regno % 8); + continue; + case '2': + if (!reg_lookup (&asarg, RCLASS_GPR, ®no) + || !RISCV_SREG_0_7 (regno)) + break; + INSERT_OPERAND (SREG2, *ip, regno % 8); + continue; default: goto unknown_riscv_ip_operand; } diff --git a/gas/testsuite/gas/riscv/zcmp-mv.d b/gas/testsuite/gas/riscv/zcmp-mv.d new file mode 100644 index 00000000000..351d301dd3f --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-mv.d @@ -0,0 +1,26 @@ +#as: -march=rv64i_zcmp +#source: zcmp-mv.s +#objdump: -dr -Mno-aliases + +.*:[ ]+file format .* + + +Disassembly of section .text: + +0+000 : +[ ]*[0-9a-f]+:[ ]+ac7e[ ]+cm.mva01s[ ]+s0,s7 +[ ]*[0-9a-f]+:[ ]+ac7a[ ]+cm.mva01s[ ]+s0,s6 +[ ]*[0-9a-f]+:[ ]+acfe[ ]+cm.mva01s[ ]+s1,s7 +[ ]*[0-9a-f]+:[ ]+acfa[ ]+cm.mva01s[ ]+s1,s6 +[ ]*[0-9a-f]+:[ ]+afee[ ]+cm.mva01s[ ]+s7,s3 +[ ]*[0-9a-f]+:[ ]+ade2[ ]+cm.mva01s[ ]+s3,s0 +[ ]*[0-9a-f]+:[ ]+aef2[ ]+cm.mva01s[ ]+s5,s4 +[ ]*[0-9a-f]+:[ ]+aefa[ ]+cm.mva01s[ ]+s5,s6 +[ ]*[0-9a-f]+:[ ]+afa2[ ]+cm.mvsa01[ ]+s7,s0 +[ ]*[0-9a-f]+:[ ]+af22[ ]+cm.mvsa01[ ]+s6,s0 +[ ]*[0-9a-f]+:[ ]+afa6[ ]+cm.mvsa01[ ]+s7,s1 +[ ]*[0-9a-f]+:[ ]+af26[ ]+cm.mvsa01[ ]+s6,s1 +[ ]*[0-9a-f]+:[ ]+adbe[ ]+cm.mvsa01[ ]+s3,s7 +[ ]*[0-9a-f]+:[ ]+ada2[ ]+cm.mvsa01[ ]+s3,s0 +[ ]*[0-9a-f]+:[ ]+aeb2[ ]+cm.mvsa01[ ]+s5,s4 +[ ]*[0-9a-f]+:[ ]+aeba[ ]+cm.mvsa01[ ]+s5,s6 diff --git a/gas/testsuite/gas/riscv/zcmp-mv.s b/gas/testsuite/gas/riscv/zcmp-mv.s new file mode 100644 index 00000000000..0bcf2a6cd98 --- /dev/null +++ b/gas/testsuite/gas/riscv/zcmp-mv.s @@ -0,0 +1,21 @@ +target: + + # cm.mva01s + cm.mva01s s0,s7 + cm.mva01s s0,s6 + cm.mva01s s1,s7 + cm.mva01s s1,s6 + cm.mva01s s7,s3 + cm.mva01s x19,s0 + cm.mva01s s5,x20 + cm.mva01s x21,x22 + + # cm.mvsa01 + cm.mvsa01 s7,s0 + cm.mvsa01 s6,s0 + cm.mvsa01 s7,s1 + cm.mvsa01 s6,s1 + cm.mvsa01 s3,s7 + cm.mvsa01 x19,s0 + cm.mvsa01 s5,x20 + cm.mvsa01 x21,x22 diff --git a/include/opcode/riscv-opc.h b/include/opcode/riscv-opc.h index d0f93b11f01..606982d7bb7 100644 --- a/include/opcode/riscv-opc.h +++ b/include/opcode/riscv-opc.h @@ -2244,6 +2244,10 @@ #define MASK_CM_POPRET 0xff03 #define MATCH_CM_POPRETZ 0xbc02 #define MASK_CM_POPRETZ 0xff03 +#define MATCH_CM_MVA01S 0xac62 +#define MASK_CM_MVA01S 0xfc63 +#define MATCH_CM_MVSA01 0xac22 +#define MASK_CM_MVSA01 0xfc63 /* Svinval instruction. */ #define MATCH_SINVAL_VMA 0x16000073 #define MASK_SINVAL_VMA 0xfe007fff @@ -3930,6 +3934,8 @@ DECLARE_INSN(cm_push, MATCH_CM_PUSH, MASK_CM_PUSH) DECLARE_INSN(cm_pop, MATCH_CM_POP, MASK_CM_POP) DECLARE_INSN(cm_popret, MATCH_CM_POPRET, MASK_CM_POPRET) DECLARE_INSN(cm_popretz, MATCH_CM_POPRETZ, MASK_CM_POPRETZ) +DECLARE_INSN(cm_mvsa01, MATCH_CM_MVSA01, MASK_CM_MVSA01) +DECLARE_INSN(cm_mva01s, MATCH_CM_MVA01S, MASK_CM_MVA01S) /* Vendor-specific (T-Head) XTheadBa instructions. */ DECLARE_INSN(th_addsl, MATCH_TH_ADDSL, MASK_TH_ADDSL) /* Vendor-specific (T-Head) XTheadBb instructions. */ diff --git a/include/opcode/riscv.h b/include/opcode/riscv.h index 630c9cf13ff..a12c6cc3b1e 100644 --- a/include/opcode/riscv.h +++ b/include/opcode/riscv.h @@ -346,6 +346,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define OP_MASK_REG_LIST 0xf #define OP_SH_REG_LIST 4 #define SP_ALIGNMENT 16 +#define OP_MASK_SREG1 0x7 +#define OP_SH_SREG1 7 +#define OP_MASK_SREG2 0x7 +#define OP_SH_SREG2 2 #define NVECR 32 #define NVECM 1 @@ -367,7 +371,10 @@ static inline unsigned int riscv_insn_length (insn_t insn) #define X_T2 7 #define X_S0 8 #define X_S1 9 +#define X_A0 10 +#define X_A1 11 #define X_S2 18 +#define X_S7 23 #define X_S10 26 #define X_S11 27 #define X_T3 28 @@ -415,6 +422,11 @@ static inline unsigned int riscv_insn_length (insn_t insn) /* The maximal number of subset can be required. */ #define MAX_SUBSET_NUM 4 +/* The range of sregs. */ +#define RISCV_SREG_0_7(REGNO) \ + ((REGNO == X_S0 || REGNO == X_S1) \ + || (REGNO >= X_S2 && REGNO <= X_S7)) + /* All RISC-V instructions belong to at least one of these classes. */ enum riscv_insn_class { diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c index f1a7c975038..c3be451ba4d 100644 --- a/opcodes/riscv-dis.c +++ b/opcodes/riscv-dis.c @@ -263,6 +263,17 @@ riscv_get_spimm (insn_t l) return spimm; } +/* Get s-register regno by using sreg number. + e.g. the regno of s0 is 8, so + riscv_zcmp_get_sregno (0) equals 8. */ + +static unsigned +riscv_zcmp_get_sregno (unsigned sreg_idx) +{ + return sreg_idx > 1 ? + sreg_idx + 16 : sreg_idx + 8; +} + /* Print insn arguments for 32/64-bit code. */ static void @@ -676,6 +687,14 @@ print_insn_args (const char *oparg, insn_t l, bfd_vma pc, disassemble_info *info case 'c': /* Zcb extension 16 bits length instruction fields. */ switch (*++oparg) { + case '1': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_zcmp_get_sregno (EXTRACT_OPERAND (SREG1, l))]); + break; + case '2': + print (info->stream, dis_style_register, "%s", + riscv_gpr_names[riscv_zcmp_get_sregno (EXTRACT_OPERAND (SREG2, l))]); + break; case 'b': print (info->stream, dis_style_immediate, "%d", (int)EXTRACT_ZCB_BYTE_UIMM (l)); diff --git a/opcodes/riscv-opc.c b/opcodes/riscv-opc.c index 3da75db6db1..9d61ce95433 100644 --- a/opcodes/riscv-opc.c +++ b/opcodes/riscv-opc.c @@ -333,6 +333,13 @@ match_th_load_pair(const struct riscv_opcode *op, return rd1 != rd2 && rd1 != rs && rd2 != rs && match_opcode (op, insn); } +static int +match_sreg1_not_eq_sreg2 (const struct riscv_opcode *op, insn_t insn) +{ + return match_opcode (op, insn) + && (EXTRACT_OPERAND (SREG1, insn) != EXTRACT_OPERAND (SREG2, insn)); +} + /* The order of overloaded instructions matters. Label arguments and register arguments look the same. Instructions that can have either for arguments must apear in the correct order in this table for the @@ -1998,6 +2005,8 @@ const struct riscv_opcode riscv_opcodes[] = {"cm.pop", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POP, MASK_CM_POP, match_opcode, 0 }, {"cm.popret", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRET, MASK_CM_POPRET, match_opcode, 0 }, {"cm.popretz", 0, INSN_CLASS_ZCMP, "{Wcr},Wcp", MATCH_CM_POPRETZ, MASK_CM_POPRETZ, match_opcode, 0 }, +{"cm.mva01s", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVA01S, MASK_CM_MVA01S, match_opcode, 0 }, +{"cm.mvsa01", 0, INSN_CLASS_ZCMP, "Wc1,Wc2", MATCH_CM_MVSA01, MASK_CM_MVSA01, match_sreg1_not_eq_sreg2, 0 }, /* Supervisor instructions. */ {"csrr", 0, INSN_CLASS_ZICSR, "d,E", MATCH_CSRRS, MASK_CSRRS|MASK_RS1, match_opcode, INSN_ALIAS },