From patchwork Wed Jan 24 05:02:03 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 191349 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp781542dyi; Tue, 23 Jan 2024 21:03:17 -0800 (PST) X-Google-Smtp-Source: AGHT+IG4NpJbU1jLJErxIKIr5W2b5SkU4MPJfGXaxSmQN2dHKMODtGxcmxxpPzshm11+SrIN1L1I X-Received: by 2002:a05:620a:424d:b0:783:9be1:38f with SMTP id w13-20020a05620a424d00b007839be1038fmr5510413qko.29.1706072597721; Tue, 23 Jan 2024 21:03:17 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706072597; cv=pass; d=google.com; s=arc-20160816; b=OluLrKu6Lv5tYwQrHflnxJ8jhYqXjUKHuzA0dQjRi2narRDm+uIx0HGPPvYxWhtBWt PEd94ZPKm0h2vpa8v+bHJu5yMuwNAchnQEnS9+R1mTk2H9NZsau4WGNzNoutF0UL6i/k x4Bm6OsCUB9Li5ukdZjf1XeLs0nY25wqlqlzZJPKibXcRvj+XgUyIGqgwFJC442OODX8 Q7hH7Jdv+rkj2W+B01Ubm30DT7XtP+0c1FCAkeBTNf16hR5ISP4TaGQF6f3l5QIXlTc1 nx4g70W7vURC0eWWRRUOck2kEHUZ7Lsi7QXdhZ0BTgk5Lolj65106leXfm4Rdk6iGwNx xnNQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=9frCqJNZ9Ebl8UrjoEJV5vlBplYaNAj2sCVd9+6gDP0=; fh=/FcLXTpjOid3TvFfEUjbYIuo/hdxOddxBi/MbWsARlw=; b=pblF3J+tq/LlpydYsNnsU+WeuorY0SJK9sDhfbAEv7d6c3Ar8NLHe+M61Va/5pb04y 1UxzEbtAaUZjeaVtkTniI5TbMoLeI7LSomlHy3y/Cw/+S6R2HDhdMybzBbfyyL687lfj GoLzqn58jKAKjkKdLjCAup2kD3I+XMgNkiDpzeQBI7Kp4LoYiApcXCj9sWc6MDHjUUpD uTZJXlfa+xWTLFA3zYcLODE3Qf5wog1UF8jXsmL3Bsj5t0mXmHGjvMEt3gu+dcAWirsa fAqm7adZEu5Blm48d4kC+f73rcqak+ip09IRg8ArVuY41lvEjo1oEgIzSO0LqXc4l3lH 2C/g== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MrQnhGrA; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36446-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36446-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. [2604:1380:45d1:ec00::1]) by mx.google.com with ESMTPS id v2-20020a05620a0a8200b00783966e534bsi8306021qkg.11.2024.01.23.21.03.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 21:03:17 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-36446-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) client-ip=2604:1380:45d1:ec00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=MrQnhGrA; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36446-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36446-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ny.mirrors.kernel.org (Postfix) with ESMTPS id 82EBA1C26350 for ; Wed, 24 Jan 2024 05:03:17 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 152F4134CD; Wed, 24 Jan 2024 05:02:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="MrQnhGrA" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9F002C8F1 for ; Wed, 24 Jan 2024 05:02:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.55.52.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072549; cv=none; b=Y3PY0QWGs6xBRpx8wRdvfTDCoswkgJFnnYJoDo7NNy2z8plvYQzEIv6yWh75gr4b0Yrm38L27l1S4/t953kGMiyQtXInwUd3C81b/ZPiZaC/JLPN5QC6W2KZLZZgRjAQr9fk/LyK41frczBhhsT3HbEzVpqquG8uYX7IRsbAhkA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072549; c=relaxed/simple; bh=fGpX5d8msWVViBqm7sRAsYLfy5pDgJccFA8lspAl428=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uiocoVPPkilVTWn0nUry9KhbceSO61/LbkT4KG4oIcLgKtTYgncSVnaBNUwKWSglQCp1bgy2LksMYxXnucOqOfF7kP5pfYKPbKzTVyeKWHvRypWnJsyEgdRu7Zp2MJmlpNyHVBp0eAOxoWoIxPNQ4PYsmTRyhj+RUUsgulEghEY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=MrQnhGrA; arc=none smtp.client-ip=192.55.52.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706072547; x=1737608547; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fGpX5d8msWVViBqm7sRAsYLfy5pDgJccFA8lspAl428=; b=MrQnhGrA6wZIvmbGcsytF5q2nf2KbMhUGpwXbdolK5AlaNHuUqE9Ee6w 91z8AF/a79MuVhQH2x5sA+RzXanK7a6/PF7HjZrD4PmXNtbk5GovONj1S ZDJGLNrKDsaBOj11dkJgL+2JYrdoy5kGM3t0gaF+LUfpIpSZhUkEnKNdL faSa71kUMBaCztDcTuHHH0BbQ2KyX1mlcUP4Oitl7vSEzEx5VshMfegxE jhyYDSBdMWovfNH/clNry/q72YZuHmblNk6LpsJsStdX095CLRdF6gMnU vmVI3Dd30kOgtoqfIiDGdZAa4q+S9rIBwTqVbPwV75zpu05UP7jHfZ5Xy w==; X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="401399359" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="401399359" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="909551505" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="909551505" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:23 -0800 From: Lucas De Marchi To: Yury Norov Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andy Shevchenko , Jani Nikula , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org Subject: [PATCH 1/3] bits: introduce fixed-type genmasks Date: Tue, 23 Jan 2024 21:02:03 -0800 Message-ID: <20240124050205.3646390-2-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240124050205.3646390-1-lucas.demarchi@intel.com> References: <20240124050205.3646390-1-lucas.demarchi@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788946780163679639 X-GMAIL-MSGID: 1788946780163679639 From: Yury Norov Generalize __GENMASK() to support different types, and implement fixed-types versions of GENMASK() based on it. The fixed-type version allows more strict checks to the min/max values accepted, which is useful for defining registers like implemented by i915 and xe drivers with their REG_GENMASK*() macros. Signed-off-by: Yury Norov Acked-by: Jani Nikula --- include/linux/bitops.h | 1 - include/linux/bits.h | 22 ++++++++++++---------- 2 files changed, 12 insertions(+), 11 deletions(-) diff --git a/include/linux/bitops.h b/include/linux/bitops.h index 2ba557e067fe..1db50c69cfdb 100644 --- a/include/linux/bitops.h +++ b/include/linux/bitops.h @@ -15,7 +15,6 @@ # define aligned_byte_mask(n) (~0xffUL << (BITS_PER_LONG - 8 - 8*(n))) #endif -#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) #define BITS_TO_LONGS(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(long)) #define BITS_TO_U64(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u64)) #define BITS_TO_U32(nr) __KERNEL_DIV_ROUND_UP(nr, BITS_PER_TYPE(u32)) diff --git a/include/linux/bits.h b/include/linux/bits.h index 7c0cf5031abe..cb94128171b2 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -6,6 +6,8 @@ #include #include +#define BITS_PER_TYPE(type) (sizeof(type) * BITS_PER_BYTE) + #define BIT_MASK(nr) (UL(1) << ((nr) % BITS_PER_LONG)) #define BIT_WORD(nr) ((nr) / BITS_PER_LONG) #define BIT_ULL_MASK(nr) (ULL(1) << ((nr) % BITS_PER_LONG_LONG)) @@ -30,16 +32,16 @@ #define GENMASK_INPUT_CHECK(h, l) 0 #endif -#define __GENMASK(h, l) \ - (((~UL(0)) - (UL(1) << (l)) + 1) & \ - (~UL(0) >> (BITS_PER_LONG - 1 - (h)))) -#define GENMASK(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK(h, l)) +#define __GENMASK(t, h, l) \ + (GENMASK_INPUT_CHECK(h, l) + \ + (((t)~0ULL - ((t)(1) << (l)) + 1) & \ + ((t)~0ULL >> (BITS_PER_TYPE(t) - 1 - (h))))) -#define __GENMASK_ULL(h, l) \ - (((~ULL(0)) - (ULL(1) << (l)) + 1) & \ - (~ULL(0) >> (BITS_PER_LONG_LONG - 1 - (h)))) -#define GENMASK_ULL(h, l) \ - (GENMASK_INPUT_CHECK(h, l) + __GENMASK_ULL(h, l)) +#define GENMASK(h, l) __GENMASK(unsigned long, h, l) +#define GENMASK_ULL(h, l) __GENMASK(unsigned long long, h, l) +#define GENMASK_U8(h, l) __GENMASK(u8, h, l) +#define GENMASK_U16(h, l) __GENMASK(u16, h, l) +#define GENMASK_U32(h, l) __GENMASK(u32, h, l) +#define GENMASK_U64(h, l) __GENMASK(u64, h, l) #endif /* __LINUX_BITS_H */ From patchwork Wed Jan 24 05:02:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 191351 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp781662dyi; Tue, 23 Jan 2024 21:03:36 -0800 (PST) X-Google-Smtp-Source: AGHT+IE5/+atehqBIqzAqKizA3KX8X3bv+Mi7qhsYgSu3jy54xxJwr76c6h4jmhCYo1WSJuWR1Ff X-Received: by 2002:a05:6a21:6d94:b0:19a:26d2:8ab0 with SMTP id wl20-20020a056a216d9400b0019a26d28ab0mr231423pzb.1.1706072616028; Tue, 23 Jan 2024 21:03:36 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706072616; cv=pass; d=google.com; s=arc-20160816; b=oWjRhTVlGzsQraEn4RYt63Ld8LdnVFfYWRSAgFZCFbyISybi/qSPqoH2GPp4hn45/Y aTMuGJXGh89aw9pEmclxy2MFjzBgC/dwuU2wtuxgafTO55v038FN9tEorhrAgTv2As0p azIg+P73NH816G8QgfV1sNeoyTEx9Gv7DtAMnUMvSqyuhYJX71+SU8IahMBb0XLvA9Ft D0TPeOFtn6V4xzUYEX6YpyOJbpOzjJqGWHwRBOco8Dy982jVpIPYgnJWsZg876/Ja1hx B5VMPrImZjLSOTQdKlhvAr7OZv8Y/dZQuZqMCKDHFBvhrsIEuHxnIMgryi4/Ck9VvjnJ WSpA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=jObf4vVe6eeXcp61IURwBgfPl9PozRFkW0RjRF6Db7k=; fh=GrJu7WEKMDCoaMYblymFhfIS8N+GbFr4FHsLoZJFT3E=; b=YD6v9jgxOzSXxlvNK+HrwiyMJkji3qBKClDxoBHjA+5V4T9Y86vQTltFs8ATurJL8v 0iHFIphTHi5cHbo21G5EldY+eyGUbDW1re7L55FZqvYHNueBCsCkpFmCBbYoLEhOezU3 rp431cyhO0KlOz7sZK7pt2Y2U9aY2DkcoXc7GRdzF8O/0kdE94zHX8i79GS3w9VdY2bT ptDT7gk7FFduEdsGJtAI+woZaW0/rV00m8wf8IhmNdlZL2WGAH9QL2ySmkl4AN3M49vR iZ1AmKFU4o/FNOyvhil9RBk4HVSbi3DzaSiFTmbpEkcdX7FYQUPZ65bItrmZgJvj6xoL tlmQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="EjhNUJ/x"; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36445-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36445-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. [2604:1380:40f1:3f00::1]) by mx.google.com with ESMTPS id i9-20020a17090aee8900b0028e796330dbsi10997008pjz.52.2024.01.23.21.03.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 21:03:36 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-36445-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) client-ip=2604:1380:40f1:3f00::1; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b="EjhNUJ/x"; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36445-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36445-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by sy.mirrors.kernel.org (Postfix) with ESMTPS id 9C1F4B262AD for ; Wed, 24 Jan 2024 05:03:09 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5863CFBFC; Wed, 24 Jan 2024 05:02:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="EjhNUJ/x" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B473C2D9 for ; Wed, 24 Jan 2024 05:02:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.55.52.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072548; cv=none; b=bVMymIzlT6rsWYf+nb7ItJczfXcRsUOrqlGfkwu7nt6GhAcG40AyH+AGewsIX6slEzpvghZyB2CwLS+w6XKs0wS/+Gdsi7UG7eZwAwM7Eq5u1oKCXnhAgAHyCMfTltnHXuiT0gjgBmXZGoFyA85V5zSLq1MuMa5BJxvBDMQs4F0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072548; c=relaxed/simple; bh=ThgMTkix4es6j5rky2OKrHCglG8hdtZ/YRFkq6PjGxQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=PIRelFfSJoQLYZQJ7IJfrPKQKLRVqDRXuEYzX9Fl3F/tICFocMMmi4qC9lrRWY7Dq6rZLX2xEpn1fY521pkwSk8Mi/GfdnjJNpj6rBnMr4w9DJgR1CeyeU1yOrxlIRHzK8pbMyXSmbOaZJSw4gUCTr2jEQv1/k/JgZD4ogvruYs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=EjhNUJ/x; arc=none smtp.client-ip=192.55.52.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706072547; x=1737608547; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ThgMTkix4es6j5rky2OKrHCglG8hdtZ/YRFkq6PjGxQ=; b=EjhNUJ/xnItscaGjesrNp7mLtE9p/yFQbPkII000R/xSsKddaoDQOFP0 PGdV4oOOfk5XQkFe9wCgfTl/h7LHUWoSqCU6Jw1iMfEJrf3RxF6smq8KL vLXgnL3bhlhnN7KR2vohYxAMHnjOu55L14ZUYAF1kaEG04LEVypH8Wrqw LYiIEdUeftYvHlWErm8E/dndQn2bM+BZ3hdUln1yD3XGbeu3P1fhJABhx Va+ZyNijat5G19l7EFIJ0qSsNKTNfjT4y/59ZZPzecElG1sPACBGLE2uM ZQs2rXbmE/ucBolAZEcW5HFI5ilYg5iDnqUXBlaZ6wrCAh2rq1Si/1KJC w==; X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="401399356" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="401399356" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="909551509" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="909551509" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:23 -0800 From: Lucas De Marchi To: Yury Norov Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andy Shevchenko , Jani Nikula , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Lucas De Marchi Subject: [PATCH 2/3] bits: Introduce fixed-type BIT Date: Tue, 23 Jan 2024 21:02:04 -0800 Message-ID: <20240124050205.3646390-3-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240124050205.3646390-1-lucas.demarchi@intel.com> References: <20240124050205.3646390-1-lucas.demarchi@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788946799751329010 X-GMAIL-MSGID: 1788946799751329010 Implement fixed-type BIT() to help drivers add stricter checks, like was done for GENMASK. Signed-off-by: Lucas De Marchi Reviewed-by: Yury Norov --- include/linux/bits.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/include/linux/bits.h b/include/linux/bits.h index cb94128171b2..5754a1251078 100644 --- a/include/linux/bits.h +++ b/include/linux/bits.h @@ -24,12 +24,16 @@ #define GENMASK_INPUT_CHECK(h, l) \ (BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ __is_constexpr((l) > (h)), (l) > (h), 0))) +#define BIT_INPUT_CHECK(type, b) \ + ((BUILD_BUG_ON_ZERO(__builtin_choose_expr( \ + __is_constexpr(b), (b) >= BITS_PER_TYPE(type), 0)))) #else /* * BUILD_BUG_ON_ZERO is not available in h files included from asm files, * disable the input check if that is the case. */ #define GENMASK_INPUT_CHECK(h, l) 0 +#define BIT_INPUT_CHECK(type, b) 0 #endif #define __GENMASK(t, h, l) \ @@ -44,4 +48,9 @@ #define GENMASK_U32(h, l) __GENMASK(u32, h, l) #define GENMASK_U64(h, l) __GENMASK(u64, h, l) +#define BIT_U8(b) ((u8)(BIT_INPUT_CHECK(u8, b) + BIT(b))) +#define BIT_U16(b) ((u16)(BIT_INPUT_CHECK(u16, b) + BIT(b))) +#define BIT_U32(b) ((u32)(BIT_INPUT_CHECK(u32, b) + BIT(b))) +#define BIT_U64(b) ((u64)(BIT_INPUT_CHECK(u64, b) + BIT(b))) + #endif /* __LINUX_BITS_H */ From patchwork Wed Jan 24 05:02:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lucas De Marchi X-Patchwork-Id: 191350 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp781613dyi; Tue, 23 Jan 2024 21:03:28 -0800 (PST) X-Google-Smtp-Source: AGHT+IFHL4WucXGkAWLOGDPqME+2oqtLHHOrJv4iKNAS+xSrxPASmaVOG/ohxPX6YI7J3rwaG/aa X-Received: by 2002:a17:906:6a85:b0:a24:da44:efb4 with SMTP id p5-20020a1709066a8500b00a24da44efb4mr539222ejr.23.1706072608650; Tue, 23 Jan 2024 21:03:28 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1706072608; cv=pass; d=google.com; s=arc-20160816; b=NOEIL7fd8a2oKQWIEzKOFf4FivYJsoDhyWGKoOmErTwXyt/vr6gQK7B8mHvliPY+WZ Pn7kPk1ZWzlFvsCGRYPURk8JPDDH1HVq2FemMOQl0yaMgb7sAi2R7X3n95Rn9SSd/oab 7vP3+D0kenVb4YsY5L6JduVvTN3AIrj9vJP8tG+hpFGqEsSSB5ThCmMcJzQr3cAMogk3 Gtx+7qsu0SoMQynpvovy076wNfMBOJLWgu74/WbkjJNXDr093zkfQFOyL4IGaawGNF0K 4kf/IKPEq0wri/cvPf3ShmAesGw1bmELgWGncA1B0ZgFEwqq4f4zOENiMncsARkfpJ6H +b4g== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=fqsMqCW/wWYjuM/HLuH9RgfDyjHwAZQB1sObX3vYq8s=; fh=GrJu7WEKMDCoaMYblymFhfIS8N+GbFr4FHsLoZJFT3E=; b=qEmqlJ36ck9szXoe4/r/jAaHOGKsy7ylyAy/1SFPF1PHDEowpJUyYkHAXLLuwOAP/B 4uvsDHpBxdZ8RAVQwvpGSGJPIsfq3vPXP67TeNKdiTIJmEy68ySOL7OVIgF5kT/BhgJq friI5W3q/eIB6pDkXGqpZ/Y6yHa5UhzNMMCv7k8fMlFmAjtfrXS97QmEBeTy7Kg1Atn4 N9Mfz/H27We7zq7KW2hG5hrMM6Z0Y5hpUGrtHF9QWBJdqXO6LnvAkisf61XUrACEEaC9 GXKvvv4l/eU1VJqqZ5UbP4iD13+89qRB3W6peztM6fOuBQkIhRqFZMpsUh8iDES9TuU2 4Zuw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gTJfdyCe; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36447-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36447-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. [147.75.80.249]) by mx.google.com with ESMTPS id v24-20020a1709064e9800b00a30985036b4si1913774eju.416.2024.01.23.21.03.28 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 21:03:28 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-36447-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) client-ip=147.75.80.249; Authentication-Results: mx.google.com; dkim=pass header.i=@intel.com header.s=Intel header.b=gTJfdyCe; arc=pass (i=1 spf=pass spfdomain=intel.com dkim=pass dkdomain=intel.com dmarc=pass fromdomain=intel.com); spf=pass (google.com: domain of linux-kernel+bounces-36447-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-36447-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=intel.com Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id 1FACE1F21C05 for ; Wed, 24 Jan 2024 05:03:28 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A20D51642B; Wed, 24 Jan 2024 05:02:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="gTJfdyCe" Received: from mgamail.intel.com (mgamail.intel.com [192.55.52.115]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCEC8DDD0 for ; Wed, 24 Jan 2024 05:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.55.52.115 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072550; cv=none; b=tRUXtdb5MLwhmxws5G2GGRZfsOhkrhx1e8lwgiMMvniB2cqpdj5khz67urcIwALkP9PFS9401mRLcRTILEZb/3Ktx91Ge7BPtRbwuPXEgKqFhyD9sbI25VsXu6uz5Pxl6i0YswMXu9+JPwwQOAbMLwmwgbrVNVAACx7T+Rj9K/c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1706072550; c=relaxed/simple; bh=P8PQBBw9UEqmtPjJgNQPIytPI7cLia4XHiT7U1LD/g0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c3SbLRfJyCQYunBQHKWiOtrVoSEPwcbLPy+BTT1irbOu7HS1yvyVaHxXhz/wI+oGmQQLicWF3yWvps0cx3FWkCGoHKJBbnchTsB+yZaVSK0NoCcDtOgNLDDXOTbi3j3/KgTudrb+bEKpBY5cPAGaY5OZ5wMZIXinZgsWirafvw8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=gTJfdyCe; arc=none smtp.client-ip=192.55.52.115 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1706072548; x=1737608548; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P8PQBBw9UEqmtPjJgNQPIytPI7cLia4XHiT7U1LD/g0=; b=gTJfdyCe1czyVvvG0ftDBiRxRro9P5ncWmvCFPSLGNMWPZrgdhBnX8Cx Ze+WOC/r6RYYQlXqdQDi2PLLSArpVRLl4nR4d9aBp1tUtU2iwWOM04IWg G33cgj17Wo4u1Bf/sQGqMxf7hKxSnxU7WggA1C79UqXEAsKvO3b2to5to ijLDB1J+vS6hbKYgW1OVaCyytu2CLyGLFV9Q5zWBlEJjnNSle9Sf8D6LU aStWgYhrGT90CDuU0gmVcyZ0nOsGoDvg95m5QwzobQna5nRsqSc96e3Tm uz15DehU3uMxNcmFmFRk3EwrKqiUQ6Ch/ooHC9iKL5NnGXOPB6NOEBvIv w==; X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="401399362" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="401399362" Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:24 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10962"; a="909551512" X-IronPort-AV: E=Sophos;i="6.05,216,1701158400"; d="scan'208";a="909551512" Received: from lucas-s2600cw.jf.intel.com ([10.165.21.196]) by orsmga004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Jan 2024 21:02:23 -0800 From: Lucas De Marchi To: Yury Norov Cc: linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Andy Shevchenko , Jani Nikula , intel-xe@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, Lucas De Marchi Subject: [PATCH 3/3] drm/i915: Convert REG_GENMASK* to fixed-width GENMASK_* Date: Tue, 23 Jan 2024 21:02:05 -0800 Message-ID: <20240124050205.3646390-4-lucas.demarchi@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240124050205.3646390-1-lucas.demarchi@intel.com> References: <20240124050205.3646390-1-lucas.demarchi@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788946791481430923 X-GMAIL-MSGID: 1788946791481430923 Now that include/linux/bits.h implements fixed-width GENMASK_*, use them to implement the i915/xe specific macros. Converting each driver to use the generic macros are left for later, when/if other driver-specific macros are also generalized. Signed-off-by: Lucas De Marchi --- drivers/gpu/drm/i915/i915_reg_defs.h | 108 +++------------------------ 1 file changed, 11 insertions(+), 97 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg_defs.h b/drivers/gpu/drm/i915/i915_reg_defs.h index a685db1e815d..52f99eb96f86 100644 --- a/drivers/gpu/drm/i915/i915_reg_defs.h +++ b/drivers/gpu/drm/i915/i915_reg_defs.h @@ -9,76 +9,19 @@ #include #include -/** - * REG_BIT() - Prepare a u32 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u32, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT(__n) \ - ((u32)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 31)))) - -/** - * REG_BIT8() - Prepare a u8 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u8, with compile time checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT8(__n) \ - ((u8)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 7)))) - -/** - * REG_GENMASK() - Prepare a continuous u32 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u32, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK(__high, __low) \ - ((u32)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 31 || (__low) > (__high))))) - -/** - * REG_GENMASK64() - Prepare a continuous u64 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK_ULL() to force u64, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. +/* + * Wrappers over the generic BIT_* and GENMASK_* implementations, + * for compatibility reasons with previous implementation */ -#define REG_GENMASK64(__high, __low) \ - ((u64)(GENMASK_ULL(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 63 || (__low) > (__high))))) +#define REG_GENMASK(__high, __low) GENMASK_U32(__high, __low) +#define REG_GENMASK64(__high, __low) GENMASK_U64(__high, __low) +#define REG_GENMASK16(__high, __low) GENMASK_U16(__high, __low) +#define REG_GENMASK8(__high, __low) GENMASK_U8(__high, __low) -/** - * REG_GENMASK8() - Prepare a continuous u8 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u8, with compile time checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK8(__high, __low) \ - ((u8)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 7 || (__low) > (__high))))) +#define REG_BIT(__n) BIT_U32(__n) +#define REG_BIT64(__n) BIT_U64(__n) +#define REG_BIT16(__n) BIT_U16(__n) +#define REG_BIT8(__n) BIT_U8(__n) /* * Local integer constant expression version of is_power_of_2(). @@ -143,35 +86,6 @@ */ #define REG_FIELD_GET64(__mask, __val) ((u64)FIELD_GET(__mask, __val)) -/** - * REG_BIT16() - Prepare a u16 bit value - * @__n: 0-based bit number - * - * Local wrapper for BIT() to force u16, with compile time - * checks. - * - * @return: Value with bit @__n set. - */ -#define REG_BIT16(__n) \ - ((u16)(BIT(__n) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__n) && \ - ((__n) < 0 || (__n) > 15)))) - -/** - * REG_GENMASK16() - Prepare a continuous u8 bitmask - * @__high: 0-based high bit - * @__low: 0-based low bit - * - * Local wrapper for GENMASK() to force u16, with compile time - * checks. - * - * @return: Continuous bitmask from @__high to @__low, inclusive. - */ -#define REG_GENMASK16(__high, __low) \ - ((u16)(GENMASK(__high, __low) + \ - BUILD_BUG_ON_ZERO(__is_constexpr(__high) && \ - __is_constexpr(__low) && \ - ((__low) < 0 || (__high) > 15 || (__low) > (__high))))) /** * REG_FIELD_PREP16() - Prepare a u16 bitfield value