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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id h10-20020a170902704a00b001d4816958c2sm8277113plt.166.2024.01.23.00.06.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:06:47 -0800 (PST) From: Jacky Huang To: linus.walleij@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, p.zabel@pengutronix.de, j.neuschaefer@gmx.net Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com, Krzysztof Kozlowski Subject: [PATCH v3 1/4] dt-bindings: reset: Add syscon to nuvoton ma35d1 system-management node Date: Tue, 23 Jan 2024 08:06:34 +0000 Message-Id: <20240123080637.1902578-2-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240123080637.1902578-1-ychuang570808@gmail.com> References: <20240123080637.1902578-1-ychuang570808@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788867786180660735 X-GMAIL-MSGID: 1788867786180660735 From: Jacky Huang Add a compatible 'syscon' to the system management node since the system control registers are mapped by this driver. The other driver must access the system control registers through 'regmap' using a phandle that references this node. Signed-off-by: Jacky Huang Acked-by: Krzysztof Kozlowski Acked-by: Philipp Zabel --- .../devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml index 34c5c1c08ec1..3ce7dcecd87a 100644 --- a/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml +++ b/Documentation/devicetree/bindings/reset/nuvoton,ma35d1-reset.yaml @@ -18,6 +18,7 @@ properties: compatible: items: - const: nuvoton,ma35d1-reset + - const: syscon reg: maxItems: 1 @@ -37,7 +38,7 @@ examples: - | system-management@40460000 { - compatible = "nuvoton,ma35d1-reset"; + compatible = "nuvoton,ma35d1-reset", "syscon"; reg = <0x40460000 0x200>; #reset-cells = <1>; }; From patchwork Tue Jan 23 08:06:35 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jacky Huang X-Patchwork-Id: 190767 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7300:2553:b0:103:945f:af90 with SMTP id p19csp185307dyi; Tue, 23 Jan 2024 00:08:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IGGSAEJyo5a3X1rHnfnru2cHQ1/dZFLezC1OWpsOzV82zV3pi7fOypSImcX6W2gYaoAD3Gx X-Received: by 2002:a17:906:3912:b0:a30:dd5d:3de7 with SMTP id f18-20020a170906391200b00a30dd5d3de7mr17692eje.140.1705997283538; Tue, 23 Jan 2024 00:08:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705997283; cv=pass; d=google.com; s=arc-20160816; b=e68aDLEOXob/GnjZJavdiIA1nIgefS/y+LaIEm1ZLTjeIgVVpkbAqOLUzVrhk7wyqG kNu7N0SZu/C2T65KTX7VY0UUL14yHY76PV8OMvQqyBDXgEOwQFQoRzTS6WrAZQ9DJkzo fhTec83vErgxxXAsPswLjJwP4+xsGBMICWpF5c3LQsIAAFuDImKMFbUA7dFl7tnfoDSr vvxKMSPvf/IZCQ4gy/6EGPfoEgt+mn9Ll23BZLFt5pIZYnCoLZOtHEqLmW32ckyKtFj3 ROoRpS2KIwzZX0ev4rwMpme9ePIM6dI3gLzGmS1mFHjSUi4j10eviQRgvvmqok+Pfw7o NrDA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=vi+Ee4Ra75GhWDNWvzS2HrP3/rPXxeeFPkLpeIHFmOs=; fh=tgUrbkNhf6DIZqZzkpsgQ15JawBXa6kDAtx2UnddeWA=; b=C+TlGVbflaX7/Uv6SR8I3Y6gW/zRERSQSZSUFA0P59Exi7NQKgNLW1Zxox28EWNdG/ ufhXMx27ShVxGYyv4g2DJwhzwniVWVcpm1mJR8inIsAMfdW5FEo5ZwX5PicqdreeT3fw RllrFiNmmnSMhtS9ZW5b6FVcvaFcFzNpK732g8J33sFaLX8a0KgW5XoQyPasOvFsVeXn tXLH4X5+mhLHSe6WB/Kp9fbAPGjk8lCRvxj++ce9tNE/Tk3+X90ztQrcY1HntS0AA+RC y98HYltAikxTa6YF4fYmOq+MNleDqwqiryYnCNXguWpViwVkBFNZOke5+eAMxDukA0vF Fzwg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@gmail.com header.s=20230601 header.b=GrDo3ZqL; arc=pass (i=1 spf=pass spfdomain=gmail.com dkim=pass dkdomain=gmail.com dmarc=pass fromdomain=gmail.com); spf=pass (google.com: domain of linux-kernel+bounces-34867-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-34867-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=QUARANTINE dis=NONE) header.from=gmail.com Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id h10-20020a170902704a00b001d4816958c2sm8277113plt.166.2024.01.23.00.06.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 23 Jan 2024 00:06:49 -0800 (PST) From: Jacky Huang To: linus.walleij@linaro.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, p.zabel@pengutronix.de, j.neuschaefer@gmx.net Cc: linux-arm-kernel@lists.infradead.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, ychuang3@nuvoton.com, schung@nuvoton.com Subject: [PATCH v3 2/4] dt-bindings: pinctrl: Document nuvoton ma35d1 pin control Date: Tue, 23 Jan 2024 08:06:35 +0000 Message-Id: <20240123080637.1902578-3-ychuang570808@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20240123080637.1902578-1-ychuang570808@gmail.com> References: <20240123080637.1902578-1-ychuang570808@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788867807636184895 X-GMAIL-MSGID: 1788867807636184895 From: Jacky Huang Add documentation to describe nuvoton ma35d1 pin control and GPIO. Signed-off-by: Jacky Huang Reviewed-by: Krzysztof Kozlowski --- .../pinctrl/nuvoton,ma35d1-pinctrl.yaml | 163 ++++++++++++++++++ 1 file changed, 163 insertions(+) create mode 100644 Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml diff --git a/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml new file mode 100644 index 000000000000..8b9ec263213f --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nuvoton,ma35d1-pinctrl.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nuvoton,ma35d1-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton MA35D1 pin control and GPIO + +maintainers: + - Shan-Chun Hung + - Jacky Huang + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - nuvoton,ma35d1-pinctrl + + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + nuvoton,sys: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle of the system-management node. + + ranges: true + +patternProperties: + "^gpio@[0-9a-f]+$": + type: object + additionalProperties: false + properties: + gpio-controller: true + + '#gpio-cells': + const: 2 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + interrupts: + description: + The interrupt outputs to sysirq. + maxItems: 1 + + required: + - gpio-controller + - '#gpio-cells' + - reg + - clocks + - interrupt-controller + - '#interrupt-cells' + - interrupts + + "^pin-[a-z0-9]+$": + type: object + description: + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input + schmitt. + + $ref: pincfg-node.yaml# + + properties: + power-source: + description: | + Valid arguments are described as below: + 0: power supply of 1.8V + 1: power supply of 3.3V + enum: [0, 1] + + drive-strength-microamp: + oneOf: + - enum: [ 2900, 4400, 5800, 7300, 8600, 10100, 11500, 13000 ] + description: 1.8V I/O driving strength + - enum: [ 17100, 25600, 34100, 42800, 48000, 56000, 77000, 82000 ] + description: 3.3V I/O driving strength + + unevaluatedProperties: false + + "-grp$": + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + properties: + nuvoton,pins: + description: + Each entry consists of 4 parameters and represents the mux and config + setting for one pin. + $ref: /schemas/types.yaml#/definitions/uint32-matrix + minItems: 1 + items: + items: + - minimum: 0 + maximum: 13 + description: + Pin bank. + - minimum: 0 + maximum: 15 + description: + Pin bank index. + - minimum: 0 + maximum: 15 + description: + Mux 0 means GPIO and mux 1 to 15 means the specific device function. + +required: + - compatible + - nuvoton,sys + +additionalProperties: false + +examples: + - | + #include + #include + #include + + pinctrl@40040000 { + compatible = "nuvoton,ma35d1-pinctrl"; + #address-cells = <1>; + #size-cells = <1>; + nuvoton,sys = <&sys>; + ranges = <0 0x40040000 0xc00>; + + gpio@0 { + reg = <0x0 0x40>; + interrupts = ; + clocks = <&clk GPA_GATE>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + uart-grp { + uart11-pins { + nuvoton,pins = <11 0 2>, + <11 1 2>, + <11 2 2>, + <11 3 2>; + bias-disable; + power-source = <1>; + }; + }; + };