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Mon, 22 Jan 2024 07:20:03 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id d21-20020adfa355000000b003392a486758sm6401113wrb.99.2024.01.22.07.20.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 07:20:02 -0800 (PST) Date: Mon, 22 Jan 2024 18:19:52 +0300 From: Dan Carpenter To: Niklas Cassel Cc: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v3 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788812792578481117 X-GMAIL-MSGID: 1788812792578481117 The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does: msg_addr &= ~aligned_offset; it will unintentionally zero out the high 32 bits. Use ALIGN_DOWN() to do the alignment instead. Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") Signed-off-by: Dan Carpenter Reviewed-by: Niklas Cassel --- v2: fix typo in commit message v3: Use ALIGN_DOWN() instead of ANDing with ~aligned_offset (this is a style improvement). drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b..51679c6702cf 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -551,7 +551,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, } aligned_offset = msg_addr & (epc->mem->window.page_size - 1); - msg_addr &= ~aligned_offset; + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret) From patchwork Mon Jan 22 15:21:00 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Carpenter X-Patchwork-Id: 190215 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2697397dyb; Mon, 22 Jan 2024 08:48:39 -0800 (PST) X-Google-Smtp-Source: AGHT+IEe/sWsw2Ed1IVx+SYaF+178AazOGHGdbV2tfkZHUaULvJBsOaEegTBcvBZ94y2lr091bgg X-Received: by 2002:a05:6402:1487:b0:55c:4ef:f8d5 with SMTP id e7-20020a056402148700b0055c04eff8d5mr113061edv.8.1705942119618; Mon, 22 Jan 2024 08:48:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705942119; cv=pass; d=google.com; s=arc-20160816; b=Cu9+JhrLLo6fYX15Ck0rDSHYkxx2MG1a9UGGvJn4T0dw1hSZphGSCFUq3HqEglg1KO bOjwofDU5CEBWsfNdaiKvt0OKws9SulcPH0tnT0V1V+VavrLIW+JjNIa3og+LR4QwNBQ WvPszDxyFpKH9KuFpBRa9bbbEG88CMwJbotf81Z9QJMhARYOI/GkstCFq7ZKmLzzfcvO qai4vhgAwAzVjz7XqJSCKsy2luZNm56877Zuz28qnXnshgiQurMtoXZ+DuzXo/OESr3i Wff90Gf2yIPBCie2jXB6lO3EgW2I9z36j6xGs/WjyVCQxAL0VZBW3SfnUcSXGw+sQmjB S/ZA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:subject:cc:to:from :date:dkim-signature; bh=3NSmP683nHsYZ+QYwFDjWG0Am9VIQRDzOaWrn4+k4gg=; fh=eXzY3uCod0uoUhoSFH26hwNyKgz3imtHgoKrWTV58bE=; b=LSj/dD4H7I51Kor1NkS16dnlaHfXdU0YfqW3rqb/z0d+wgH3uKWCqj7vA17RK4bLZ4 rrRHU4gIOTDpRbbGNGdi85u1ACX3o7IPadObb/Oo3WQv92X3NoVW7/Wf727vgcmFNlvg LUHgLYPuuHq4THKamrTEwHKcT6rpIsij8R8sXIyTMtB82H3K/3FVBKLMrYmOyQqCjyRT /n46VGo4DZL0P18Xlqf2eDstE6wqyqLTcShLoKV8NI6BjTy1XGPISJEyry5w6jx5v2yX ZA3Sk5VCWYJ9YTBCrhV0ep6XXC7nVrSILF+r7ByXoXA8UyHHNPXVTxCbyCzvCwzZ54l8 5zZg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="D/yBbLD2"; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-33575-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-33575-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Mon, 22 Jan 2024 07:21:13 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id jb13-20020a05600c54ed00b0040e418494absm38542327wmb.46.2024.01.22.07.21.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 07:21:13 -0800 (PST) Date: Mon, 22 Jan 2024 18:21:00 +0300 From: Dan Carpenter To: Jingoo Han Cc: Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v3 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788809964000702608 X-GMAIL-MSGID: 1788809964000702608 I recently changed the code in dw_pcie_ep_raise_msix_irq() to use ALIGN_DOWN(). The code in dw_pcie_ep_raise_msi_irq() is similar so update it to match as well. (No effect on runtime, just a cleanup). Signed-off-by: Dan Carpenter Reviewed-by: Niklas Cassel --- v2: Add this patch v3: Use ALIGN_DOWN() as a style improvement drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 51679c6702cf..1c8d2e938851 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -483,8 +483,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); } aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); - msg_addr = ((u64)msg_addr_upper) << 32 | - (msg_addr_lower & ~aligned_offset); + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; + msg_addr = ALIGN_DOWN(msg_addr, epc->mem->window.page_size); ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret)