From patchwork Mon Jan 22 12:19:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190139 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2533081dyb; Mon, 22 Jan 2024 04:25:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IEZMw+UXpSkMN9uawPy5zM7OkppIDIFYPBQLHEEZsd1EaoE6uguoP7M1ppNShGFp4LzABl+ X-Received: by 2002:a05:6870:b291:b0:210:dbf8:2712 with SMTP id c17-20020a056870b29100b00210dbf82712mr3843092oao.12.1705926339847; Mon, 22 Jan 2024 04:25:39 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705926339; cv=pass; d=google.com; s=arc-20160816; b=rlgdu3nPSMKPiKmdscFu4btZNm0zAMT+z6Wcf11vgcbLk+4Xz9v9XIkDnIBq4a1zFY U3wjFyLBexbhrkIfNwtNDohwKiCUT/ucOeayNYVItRrpDQK/Bxk5Ov9J7hU1DvCyMGiR zhV7Gc2okSKFUhxgPL1/Oe/0NcWOJ6Ca3A2B5DkUFKpsQtDZBpIN/TcfqqgEgG7GOgHg YHcdlzO7pVu6RUQBWD2Kn1CEkc+FY9yEaaQX/zvu0TjoYMPLYH50s+O1gWCdD+ltKCjH jmkFxDFCSRiSfMFw7ARCyWyfeGpGhXDLYHR0V9xONAMhq1qJfXPUynlvaYBEIWC03FJu vKvw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=1fOyVahCYLH5bhhFiWgoQ8fqLcbL1XxJ64HhTzkKiSE=; fh=KxiCt5h9moAxCK7yf1rsC0rZmIJdvZ3ZC0odlgP90NU=; b=dQicEKWS7apOSO5lGuV/m6d0YF33rGvGf9FodtJuF5hit+fD/HVqo3R82Xib61qNsN AkFiDHpmMr4b3xSWpb+KvJwo4YBq5l+aGXdquFATftpKzB2WC1TkwwNDJ5xYw0KcOGqB 7pXWr00P3BEZGxANosKIh7GNo7qWQwG+3qeP52LkCCF617QtBmf9C3pp5laSghBdmE0g x6H9xxQtsb4ORpmPWi54mclGwiJay4jIbMrp2ff1Kn5DmrGcKx5yHywm6Go/vnjyYcLQ q2ISyub4D8p7MH1x65oeBaCN0vX2o3LnhNjwfzqAMXoEznQN6GR2kySVy21h/q0aUp2e PuBw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=h22W9lTp; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-32997-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-32997-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 1/7] dt-bindings: clock: mpfs: add more MSSPLL output definitions Date: Mon, 22 Jan 2024 12:19:49 +0000 Message-ID: <20240122-envoy-chosen-7ae961b3b07e@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=944; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=28AMgJEH+kbgvVu06aM3gqKT3dUxuCabMm2ZpjhF9GI=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlPmLJT0Kn5llKNl++tn4PHwJTLlOU3r4h9yynFfO zGhrk2xo5SFQYyDQVZMkSXxdl+L1Po/Ljuce97CzGFlAhnCwMUpABMxSmb4Z+C2z3dvWZXJbYWJ ckqH4j6pfZduK8xPfVT3Z86GIiY/U0aGd4aP8g6uOMUo/7Qn1c1qZlV/T7PIsZBg9Q3bgrb+cuj iBwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793417615469801 X-GMAIL-MSGID: 1788793417615469801 From: Conor Dooley There are 3 undocumented outputs of the MSSPLL that are used for the CAN bus, "user crypto" module and eMMC. Add their clock IDs so that they can be hooked up in DT. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- include/dt-bindings/clock/microchip,mpfs-clock.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h index 79775a5134ca..b52f19a2b480 100644 --- a/include/dt-bindings/clock/microchip,mpfs-clock.h +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -44,6 +44,11 @@ #define CLK_RTCREF 33 #define CLK_MSSPLL 34 +#define CLK_MSSPLL0 34 +#define CLK_MSSPLL1 35 +#define CLK_MSSPLL2 36 +#define CLK_MSSPLL3 37 +/* 38 is reserved for MSS PLL internals */ /* Clock Conditioning Circuitry Clock IDs */ From patchwork Mon Jan 22 12:19:50 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190140 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2533158dyb; Mon, 22 Jan 2024 04:25:53 -0800 (PST) X-Google-Smtp-Source: AGHT+IEKhoqSXkO7nHL/cOnfJFEqzHaGOLX98AwhWFP9EWiqVcZ4YxFJ+aeb2EQ43Seu0ZzXbBTz X-Received: by 2002:a05:6a20:daa5:b0:19b:a07a:3495 with SMTP id iy37-20020a056a20daa500b0019ba07a3495mr7214329pzb.25.1705926353027; Mon, 22 Jan 2024 04:25:53 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705926353; cv=pass; d=google.com; s=arc-20160816; b=I1xY+1SOGc2b/iliCSAJEJA81e44ngs7BWAsT5uleJebJw45ghzy8Q9LbhmjH/Rxez YXIRQ9K4l8bv8pNv9fS5OgBxmJYVQ6SisAUwDlurPzg0zb9GUEJjQicpdTOWfCWfhglu yMopHxvPs7+exVPyS2Wh4leulOXHXvDuVxHbwnKnww+Rnwh4zymO7LHo32dvWJc7yMku t2D/B1wfsQeOEYbAXaSKLp/XZ54ExXua1KC3thxBMMlakMISWZhKxAqXxa8V7bB5EnpA BguHhgK03Zbl63GWhBBaE2AeHfA7wWyLJ4+x2wEqfUGoJiohjrZqXL9TYYjwceQ371Ct vczA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=T1eR2ZWK2YFg1dfgPImWRNx1PM+Oe3qV2tgVYPTyk/Y=; fh=7owW42T6ZLRf2RzLwZvq8R8LNTe7zgMt8CKJpj74120=; b=iQuDZBflZApy4jpSG5df8/LU04pewSictmPAMx80CrZzaKd8FgNGSwMTOGgMZQlslg UyIRcQktM4mVAUUCzz8GZejcR82ZQNoF4672nMsPCPL99IPAXmHxF5pFyJqa8F9pnVrP SOAfTVDaKDshXjEbs3SF2szUIO04M+xfiixodN+lS4WLkYPROPI3lLvrWRdiDEZZ+K4b 3S8MSt9ZAsPMTKn7czpfNnfmmJnaEDe8vDZ/B8RfcQYqxli72UmlCVOz8M3hlXeRGGK4 81BkjfuCOysSY1PtItlzy62oDEa4EStEyVJqDEkr+NkSxWLi0JJ/2rCckgcYLcbqoQmw 8KJQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=q0+1BfKX; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-32998-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45e3:2400::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-32998-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/7] dt-bindings: can: mpfs: add missing required clock Date: Mon, 22 Jan 2024 12:19:50 +0000 Message-ID: <20240122-breeder-lying-0d3668d98886@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1423; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=NrajZ8DKLByCJYLOG7gevyAp2euhGy7v9GQJAOxw45A=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlPKSnQ17k1J/f3WvmYO46S1vI6Zc+PX+eiHL7mtm OS1+1xcRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACay9Bwjw6rOzD+StveFa45F 3lLZYsjaYnNviefhqQbpbO5Pw4zdvRj+xxjJuMotUOz7uJhffcfz6Q+9jdZdWXft3VytDs0X8uH qLAA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793431755284231 X-GMAIL-MSGID: 1788793431755284231 From: Conor Dooley The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a CAN bus clock. The bus clock was omitted when the binding was written, but is required for operation. Make up for lost time and add it. Cautionary tale in adding bindings without having implemented a real user for them perhaps. Fixes: c878d518d7b6 ("dt-bindings: can: mpfs: document the mpfs CAN controller") Signed-off-by: Conor Dooley Reviewed-by: Krzysztof Kozlowski --- .../devicetree/bindings/net/can/microchip,mpfs-can.yaml | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml index 45aa3de7cf01..01e4d4a54df6 100644 --- a/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml +++ b/Documentation/devicetree/bindings/net/can/microchip,mpfs-can.yaml @@ -24,7 +24,9 @@ properties: maxItems: 1 clocks: - maxItems: 1 + items: + - description: AHB peripheral clock + - description: CAN bus clock required: - compatible @@ -39,7 +41,7 @@ examples: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x2010c000 0x1000>; - clocks = <&clkcfg 17>; + clocks = <&clkcfg 17>, <&clkcfg 37>; interrupt-parent = <&plic>; interrupts = <56>; }; From patchwork Mon Jan 22 12:19:51 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190135 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2531703dyb; Mon, 22 Jan 2024 04:22:55 -0800 (PST) X-Google-Smtp-Source: AGHT+IHBDteKMUrCT30LTtp++u8Nawsw1gzMPX5jqM5ChA/VDbs+rfUiegz1LIbjsm3w9uMgr+Ol X-Received: by 2002:a05:620a:450d:b0:783:ad2:9031 with SMTP id t13-20020a05620a450d00b007830ad29031mr6390366qkp.61.1705926174776; Mon, 22 Jan 2024 04:22:54 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705926174; cv=pass; d=google.com; s=arc-20160816; b=tHKtrj8UNRbpZWPJVDrSRMv9HysXJoQyw8v3dMJEygka4QvoYsu0pxK8YV0F6GTxtp yIk8G2zrQAJZ+IYt+KZHEpscl6+r7L5PqfrX0ZGlDiI4ssu8McfrdyToezCZtkxSMYUk mfRBdqFqBj4IeVX2VNHhSQRWihfmqiZL1w9tjFxDXavkofXIEaOXLp5KfDwNPbgsHwLY uhEUNCbZLxZgk9+b/l+yqH4JrM0g5Sym6t3HyFnvdUwf4yQalB6tQ+OvBSJwjcdMfvQd N/7ugOCbLJC0w3i+kLpgdi6hKAWm3Vb/mBSrl35cgX8LHP4+0qIHDpa/tkN5vzgNhNFj mPeQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=e9lo5+9aXX6B1Mp5c7CO30ccMkmLjcH1UZ8vzpojHHk=; fh=7owW42T6ZLRf2RzLwZvq8R8LNTe7zgMt8CKJpj74120=; b=uccXEuhIpBbG2mI3k8GSWYpPQkOLF0nygaQrJSFoG+2Lm4MYheHZHzX7U+fr6xys2S rmeYADxtf5tqE8rz0gzPzojddyxY3V57DkvhSoootd5Pb8K0zkOTUW94m7cZ5t/APkM3 2qSeSR81l2Bpy+NqLwVZJ8b6RGJvBehpCK2y2eqHnOD3Axv98rGnPrVmTniv1H6lpokX Rta7a4OzI4O+G1WQBvf32gTKnMGEWr3Jy1cYbY2fkHAKLDBoe68K8sv6u+cVXfJ3BRGU aTWNyig/1qM1Mk6n47NGRFMIVBZFQi+B1mR46KIBNF/guQZL6giA++X+Lo7skGX6iHS0 mW8Q== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=q8NqcTJp; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-32999-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-32999-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 3/7] clk: microchip: mpfs: split MSSPLL in two Date: Mon, 22 Jan 2024 12:19:51 +0000 Message-ID: <20240122-truth-scope-7b96ba10d491@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=10025; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=TAPscgRc3/2SRGpBrHR1CQ9xRHawcumgg4V8O/3bXw4=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlNKUtlFtc5bbjywetfx7FOeLzr5J5vuuHikT+cmu 1rm3IiPHaUsDGIcDLJiiiyJt/tapNb/cdnh3PMWZg4rE8gQBi5OAZjIanaG/3kKsQu7D5zn182r 4rBZ5imdYXG/i+1hWtSeSQeXPJ8VY83IMFefpar+he7e2HS5yc8spszS8Qotf7FwfvExvS+10nl POQA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793244735150094 X-GMAIL-MSGID: 1788793244735150094 From: Conor Dooley The MSSPLL is really two stages - there's the PLL itself and 4 outputs, each with their own divider. The current driver models this as a single entity, outputting a single clock, used for both the CPU and AHB/AXI buses. The other 3 outputs are used for the eMMC, "user crypto" and CAN controller. Split the MSSPLL in two, as a precursor to adding support for the other 3 outputs, with the PLL itself as one "hw" clock and the output divider stage as another. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 188 ++++++++++++++++++++----------- 1 file changed, 123 insertions(+), 65 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index c8ffa755b58d..acf598a32ce0 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -30,6 +30,13 @@ #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u +/* + * This clock ID is defined here, rather than the binding headers, as it is an + * internal clock only, and therefore has no consumers in other peripheral + * blocks. + */ +#define CLK_MSSPLL_INTERNAL 38u + struct mpfs_clock_data { struct device *dev; void __iomem *base; @@ -39,17 +46,27 @@ struct mpfs_clock_data { struct mpfs_msspll_hw_clock { void __iomem *base; + struct clk_hw hw; + struct clk_init_data init; unsigned int id; u32 reg_offset; u32 shift; u32 width; u32 flags; - struct clk_hw hw; - struct clk_init_data init; }; #define to_mpfs_msspll_clk(_hw) container_of(_hw, struct mpfs_msspll_hw_clock, hw) +struct mpfs_msspll_out_hw_clock { + void __iomem *base; + struct clk_hw hw; + struct clk_init_data init; + unsigned int id; + u32 flags; +}; + +#define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw) + struct mpfs_cfg_hw_clock { struct clk_divider cfg; struct clk_init_data init; @@ -93,93 +110,40 @@ static const struct clk_div_table mpfs_div_rtcref_table[] = { { 0, 0 } }; +/* + * MSS PLL internal clock + */ + static unsigned long mpfs_clk_msspll_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; - u32 mult, ref_div, postdiv; - - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; - postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); - - return prate * mult / (ref_div * MSSPLL_FIXED_DIV * postdiv); -} - -static long mpfs_clk_msspll_round_rate(struct clk_hw *hw, unsigned long rate, unsigned long *prate) { struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; u32 mult, ref_div; - unsigned long rate_before_ctrl; mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; - - return divider_round_rate(hw, rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, - msspll_hw->flags); -} - -static int mpfs_clk_msspll_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_msspll_hw_clock *msspll_hw = to_mpfs_msspll_clk(hw); - void __iomem *mult_addr = msspll_hw->base + msspll_hw->reg_offset; - void __iomem *ref_div_addr = msspll_hw->base + REG_MSSPLL_REF_CR; - void __iomem *postdiv_addr = msspll_hw->base + REG_MSSPLL_POSTDIV_CR; - u32 mult, ref_div, postdiv; - int divider_setting; - unsigned long rate_before_ctrl, flags; - - mult = readl_relaxed(mult_addr) >> MSSPLL_FBDIV_SHIFT; - mult &= clk_div_mask(MSSPLL_FBDIV_WIDTH); - ref_div = readl_relaxed(ref_div_addr) >> MSSPLL_REFDIV_SHIFT; - ref_div &= clk_div_mask(MSSPLL_REFDIV_WIDTH); - - rate_before_ctrl = rate * (ref_div * MSSPLL_FIXED_DIV) / mult; - divider_setting = divider_get_val(rate_before_ctrl, prate, NULL, MSSPLL_POSTDIV_WIDTH, - msspll_hw->flags); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); - writel_relaxed(postdiv, postdiv_addr); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; + return prate * mult / (ref_div * MSSPLL_FIXED_DIV); } static const struct clk_ops mpfs_clk_msspll_ops = { .recalc_rate = mpfs_clk_msspll_recalc_rate, - .round_rate = mpfs_clk_msspll_round_rate, - .set_rate = mpfs_clk_msspll_set_rate, }; #define CLK_PLL(_id, _name, _parent, _shift, _width, _flags, _offset) { \ .id = _id, \ + .flags = _flags, \ .shift = _shift, \ .width = _width, \ .reg_offset = _offset, \ - .flags = _flags, \ .hw.init = CLK_HW_INIT_PARENTS_DATA(_name, _parent, &mpfs_clk_msspll_ops, 0), \ } static struct mpfs_msspll_hw_clock mpfs_msspll_clks[] = { - CLK_PLL(CLK_MSSPLL, "clk_msspll", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, + CLK_PLL(CLK_MSSPLL_INTERNAL, "clk_msspll_internal", mpfs_ext_ref, MSSPLL_FBDIV_SHIFT, MSSPLL_FBDIV_WIDTH, 0, REG_MSSPLL_SSCG_2_CR), }; @@ -196,7 +160,7 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c ret = devm_clk_hw_register(dev, &msspll_hw->hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll id: %d\n", - CLK_MSSPLL); + CLK_MSSPLL_INTERNAL); data->hw_data.hws[msspll_hw->id] = &msspll_hw->hw; } @@ -204,6 +168,94 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c return 0; } +/* + * MSS PLL output clocks + */ + +static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 postdiv; + + postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; + postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + + return prate / postdiv; +} + +static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + + return divider_round_rate(hw, rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_out_hw->flags); +} + +static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) +{ + struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); + void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + u32 postdiv; + int divider_setting; + unsigned long flags; + + divider_setting = divider_get_val(rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + msspll_out_hw->flags); + + if (divider_setting < 0) + return divider_setting; + + spin_lock_irqsave(&mpfs_clk_lock, flags); + + postdiv = readl_relaxed(postdiv_addr); + postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + writel_relaxed(postdiv, postdiv_addr); + + spin_unlock_irqrestore(&mpfs_clk_lock, flags); + + return 0; +} + +static const struct clk_ops mpfs_clk_msspll_out_ops = { + .recalc_rate = mpfs_clk_msspll_out_recalc_rate, + .round_rate = mpfs_clk_msspll_out_round_rate, + .set_rate = mpfs_clk_msspll_out_set_rate, +}; + +#define CLK_PLL_OUT(_id, _name, _parent, _flags) { \ + .id = _id, \ + .flags = _flags, \ + .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ +} + +static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { + CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", 0), +}; + +static int mpfs_clk_register_msspll_outs(struct device *dev, + struct mpfs_msspll_out_hw_clock *msspll_out_hws, + unsigned int num_clks, struct mpfs_clock_data *data) +{ + unsigned int i; + int ret; + + for (i = 0; i < num_clks; i++) { + struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i]; + + msspll_out_hw->base = data->msspll_base; + ret = devm_clk_hw_register(dev, &msspll_out_hw->hw); + if (ret) + return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n", + msspll_out_hw->id); + + data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->hw; + } + + return 0; +} + /* * "CFG" clocks */ @@ -442,8 +494,8 @@ static int mpfs_clk_probe(struct platform_device *pdev) int ret; /* CLK_RESERVED is not part of clock arrays, so add 1 */ - num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_cfg_clks) - + ARRAY_SIZE(mpfs_periph_clks) + 1; + num_clks = ARRAY_SIZE(mpfs_msspll_clks) + ARRAY_SIZE(mpfs_msspll_out_clks) + + ARRAY_SIZE(mpfs_cfg_clks) + ARRAY_SIZE(mpfs_periph_clks) + 1; clk_data = devm_kzalloc(dev, struct_size(clk_data, hw_data.hws, num_clks), GFP_KERNEL); if (!clk_data) @@ -466,6 +518,12 @@ static int mpfs_clk_probe(struct platform_device *pdev) if (ret) return ret; + ret = mpfs_clk_register_msspll_outs(dev, mpfs_msspll_out_clks, + ARRAY_SIZE(mpfs_msspll_out_clks), + clk_data); + if (ret) + return ret; + ret = mpfs_clk_register_cfgs(dev, mpfs_cfg_clks, ARRAY_SIZE(mpfs_cfg_clks), clk_data); if (ret) return ret; From patchwork Mon Jan 22 12:19:52 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190137 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2531781dyb; Mon, 22 Jan 2024 04:23:05 -0800 (PST) X-Google-Smtp-Source: AGHT+IGsYJ32KGjrZGPRSuQdmlATGfz6ad1tJ+sgjjTN/ehkBhxKoy7OLgJi0EnvKqvLVbsGX0f5 X-Received: by 2002:ad4:5be9:0:b0:685:238a:76d6 with SMTP id k9-20020ad45be9000000b00685238a76d6mr4568029qvc.0.1705926185211; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 4/7] clk: microchip: mpfs: setup for using other mss pll outputs Date: Mon, 22 Jan 2024 12:19:52 +0000 Message-ID: <20240122-sprint-hacking-8d2f20654bf1@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=4672; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=t4FAgw3fopovHlUFM1DCXwuCj6lBGSfP99KWVcOPLP0=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlOeBpZyrb4z/7tEllyWxuwSk0q7AwlKBy423daUS n0XP39/RykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACayfwojw1SB7ZFr3NyPKT+c 8eofw6WKl4KhDjniFtPe/Pi/RaGx9Agjw9K9nwu+3/vlvr1hBm+IdsQ16x1Tb3B89n+8l2F506P 0VC4A X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793255604361156 X-GMAIL-MSGID: 1788793255604361156 From: Conor Dooley Now that the MSSPLL is split, and the "postdiv" divider of the cpu/AHB/AXI bus clock is represented by its own "hw" struct, make the shifts, register offset and width a parameter of the initialisation macro, rather than using defines that only work for one of the four outputs. Configuring this at initialisaion paves the way for using the other three output clocks, where the register offset, and the bit shift within that register, will differ. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 30 +++++++++++++++++++----------- 1 file changed, 19 insertions(+), 11 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index acf598a32ce0..911905d0433d 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -15,7 +15,8 @@ /* address offset of control registers */ #define REG_MSSPLL_REF_CR 0x08u -#define REG_MSSPLL_POSTDIV_CR 0x10u +#define REG_MSSPLL_POSTDIV01_CR 0x10u +#define REG_MSSPLL_POSTDIV23_CR 0x14u #define REG_MSSPLL_SSCG_2_CR 0x2Cu #define REG_CLOCK_CONFIG_CR 0x08u #define REG_RTC_CLOCK_CR 0x0Cu @@ -26,7 +27,7 @@ #define MSSPLL_FBDIV_WIDTH 0x0Cu #define MSSPLL_REFDIV_SHIFT 0x08u #define MSSPLL_REFDIV_WIDTH 0x06u -#define MSSPLL_POSTDIV_SHIFT 0x08u +#define MSSPLL_POSTDIV02_SHIFT 0x08u #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u @@ -62,6 +63,9 @@ struct mpfs_msspll_out_hw_clock { struct clk_hw hw; struct clk_init_data init; unsigned int id; + u32 reg_offset; + u32 shift; + u32 width; u32 flags; }; @@ -175,11 +179,11 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; u32 postdiv; - postdiv = readl_relaxed(postdiv_addr) >> MSSPLL_POSTDIV_SHIFT; - postdiv &= clk_div_mask(MSSPLL_POSTDIV_WIDTH); + postdiv = readl_relaxed(postdiv_addr) >> msspll_out_hw->shift; + postdiv &= clk_div_mask(msspll_out_hw->width); return prate / postdiv; } @@ -189,19 +193,19 @@ static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - return divider_round_rate(hw, rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + return divider_round_rate(hw, rate, prate, NULL, msspll_out_hw->width, msspll_out_hw->flags); } static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + REG_MSSPLL_POSTDIV_CR; + void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; u32 postdiv; int divider_setting; unsigned long flags; - divider_setting = divider_get_val(rate, prate, NULL, MSSPLL_POSTDIV_WIDTH, + divider_setting = divider_get_val(rate, prate, NULL, msspll_out_hw->width, msspll_out_hw->flags); if (divider_setting < 0) @@ -210,7 +214,7 @@ static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, u spin_lock_irqsave(&mpfs_clk_lock, flags); postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(MSSPLL_POSTDIV_WIDTH) << MSSPLL_POSTDIV_SHIFT); + postdiv &= ~(clk_div_mask(msspll_out_hw->width) << msspll_out_hw->shift); writel_relaxed(postdiv, postdiv_addr); spin_unlock_irqrestore(&mpfs_clk_lock, flags); @@ -224,14 +228,18 @@ static const struct clk_ops mpfs_clk_msspll_out_ops = { .set_rate = mpfs_clk_msspll_out_set_rate, }; -#define CLK_PLL_OUT(_id, _name, _parent, _flags) { \ +#define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ .id = _id, \ + .shift = _shift, \ + .width = _width, \ + .reg_offset = _offset, \ .flags = _flags, \ .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ } static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { - CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", 0), + CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", 0, + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), }; static int mpfs_clk_register_msspll_outs(struct device *dev, From patchwork Mon Jan 22 12:19:53 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190136 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2531717dyb; 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[2604:1380:4601:e00::3]) by mx.google.com with ESMTPS id bd2-20020a056402206200b0055a91a3698asi2522478edb.246.2024.01.22.04.22.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Jan 2024 04:22:56 -0800 (PST) Received-SPF: pass (google.com: domain of linux-kernel+bounces-33001-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) client-ip=2604:1380:4601:e00::3; Authentication-Results: mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=d39xi6db; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-33001-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-33001-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from smtp.subspace.kernel.org (wormhole.subspace.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by am.mirrors.kernel.org (Postfix) with ESMTPS id BE8C51F22928 for ; Mon, 22 Jan 2024 12:22:55 +0000 (UTC) Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C23B93D97F; Mon, 22 Jan 2024 12:20:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="d39xi6db" Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A64B3BB3F; Mon, 22 Jan 2024 12:20:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705926036; cv=none; b=uy12PQR8VVwrhdQilyfI7Wwl+sC20dzCQtKUkvAvYe33ZqsO2rdvWs3wF6A+eC1Yt4lkjItNDb+A7WViezSpVMWXb3Kafvbmxh1FXSrHbNeBCWKmp3v4DeJgCnMYUxyOpM2FhXB245d87DZHx/2SstBCRlE8tscSuz9yH/x+KZ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1705926036; c=relaxed/simple; bh=tebc2epqBPqi3q6nwRuHzvgjiwhDevUi+LtXh9FShW4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=npQI4ep4Cb95zqwSWdoIvFhz7ZDGvEH2dUQfy+PKL1FOdCGhyBferBr3h0G8KhwZRnw3d+ndFpSI9uWBS/yQJbg1plGU7q7qzPG6WU2tMlXJW8oAs1YjLo7aG1vDWWB8AS8p3wakrRwsQC8kwBSz9/oDOfDkiTtv56MOiP2qFM8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=d39xi6db; arc=none smtp.client-ip=10.30.226.201 Received: by smtp.kernel.org (Postfix) with ESMTPSA id 4DD11C43390; Mon, 22 Jan 2024 12:20:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1705926035; bh=tebc2epqBPqi3q6nwRuHzvgjiwhDevUi+LtXh9FShW4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d39xi6db5ggCp+RmilEG82Cw9t3JzSuihoMmextnDsrpiac5WF2FYM9xtMbYTsZhd gg1TVEJIxBuI8dWXqC5YyD0NLvgJ83BNRytMIc2Y58yxFN/pGdyHfqp4vGl1KHECBO xQcVeiqpy69wAC2PQiGYY0+wpiUB/YXFmE9ggje4IyR9ctb+m/DnDYp7+g87pnagRt YiM7BPGhsWm6acnIecy+zNOjgpEx1021GKPKDAYz56NJUiclVhIf6SnlYLN1pp7F/z qHrAD6Xz0r+Dkby7a+xFW+0piYlfl5eLWNxXjgCU7M3hUo8Bc5isbLaDkHRROab0mO 7I/2++UtIizFQ== From: Conor Dooley To: linux-riscv@lists.infradead.org Cc: conor@kernel.org, Conor Dooley , Daire McNamara , Wolfgang Grandegger , Marc Kleine-Budde , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 5/7] clk: microchip: mpfs: add missing MSSPLL outputs Date: Mon, 22 Jan 2024 12:19:53 +0000 Message-ID: <20240122-scarring-auction-b13c25a422bd@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1722; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=1OkhpL0+t001V44z+z0voVrWBZYio2gp1txLGSVnNbo=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlP3b48MMc7LmOpeONVl+ZN3Wi3azvNyyuOFVm489 4R5HbNZRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACbypIGRYdWbLRoPHrc907lS dppBYWmKnll0tqplgMev0M8egmvWJDMyPLe/2pW153XCpOTFKn36lx/WV5atsZE2FPtYEjevevs 3VgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793245943929265 X-GMAIL-MSGID: 1788793245943929265 From: Conor Dooley The MSSPLL has 4 outputs, of which only the cpu/axi/ahb clock parent is currently implemented. Add the CAN clock too, as that'll be needed by the driver for the CAN controller and uses output 3. While we are here, the other two missing clocks, used by the eMMC/SD controller and by the "user crypto". Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index 911905d0433d..bed6adbb8a70 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -28,6 +28,7 @@ #define MSSPLL_REFDIV_SHIFT 0x08u #define MSSPLL_REFDIV_WIDTH 0x06u #define MSSPLL_POSTDIV02_SHIFT 0x08u +#define MSSPLL_POSTDIV13_SHIFT 0x18u #define MSSPLL_POSTDIV_WIDTH 0x07u #define MSSPLL_FIXED_DIV 4u @@ -240,6 +241,12 @@ static const struct clk_ops mpfs_clk_msspll_out_ops = { static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", 0, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), + CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", 0, + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), + CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", 0, + MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), + CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", 0, + MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), }; static int mpfs_clk_register_msspll_outs(struct device *dev, From patchwork Mon Jan 22 12:19:54 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190156 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2549088dyb; Mon, 22 Jan 2024 04:58:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IGIJtHWqLGvT+UjxKPGHGpFGvYZe+uHp65l9JzFEuN/68ZDl14ucMFvjjS40cPQy8iP2N1I X-Received: by 2002:a05:6a20:12d2:b0:199:da11:8efa with SMTP id v18-20020a056a2012d200b00199da118efamr6278309pzg.27.1705928305866; Mon, 22 Jan 2024 04:58:25 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705928305; cv=pass; d=google.com; s=arc-20160816; b=NVK+UDG4+vf16ez95Sgec13y+jKWXglcqDqgfteVBwkFhAPSX6w6c023PBY7WvRaX9 /VQyt5Kp1qsH8CtEcF185KfOUYSHLwwCcY0Nxbe/IvBjjxefgIXFqk0hU0p1F/2QCtYl 60Rp4TFVBa5tHVOlWrsvaIHSmRhDuhJDwI5dVKDrw2Dr0w7uHZG6FZkBSNI3226cbQME DV7Yb07AKuHclydQ49iQWEviHfAZrA8wBthKjnyiP/+AlxTY1BHkR7ToSf/WsBbAM+PP x1cIcXh8R5Dk1EbLr6f9+5YPGtVb8Ix8uLDWabZDRNCmVIVAeJY89/wIfpntS6HeB6iE NVZQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=tbI31mZHvvYmqh6f8/ThALMFDgDxkFqOKalcMtrjCeg=; fh=7owW42T6ZLRf2RzLwZvq8R8LNTe7zgMt8CKJpj74120=; b=E/IWVtttxdnoivd4023u6Y2Y4ZWkm4v55cA6bGbpgBGJneKQCVS56IcELFOFinSj// RZGaedrw1FX/gghJGaSahkfluDk4vD/+t14sf23OD9S+Kx77QZDngNapiY3wAniPM+4u Z5OsWOlhifOd4wqgnmfP/vk/8fvTFkubvRynwSyouEI95h0GPBczXJ5UA/QM2f3L9hts lkoZNWclBkEW5exogquchmwA596aEn0KASyqYnnAt8jDsSw39xlNG+rHDsKVBRdM382N lrvmZ8xcVU+e6CkPsc84jCcOSZ6yJJ6+LbmEpxAH3TDvFwvkjHJecxJmxEOwQpu5uhSm NovA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@kernel.org header.s=k20201202 header.b=kGUqRyUF; arc=pass (i=1 dkim=pass dkdomain=kernel.org); spf=pass (google.com: domain of linux-kernel+bounces-33003-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-33003-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 6/7] clk: microchip: mpfs: convert MSSPLL outputs to clk_divider Date: Mon, 22 Jan 2024 12:19:54 +0000 Message-ID: <20240122-drop-down-kooky-1fdc850c16b6@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=5154; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=GstYXae7YmaE0PSrBEvAfhgo8lU9+0CrRNVIt4fzA+k=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlPLRXftesahl2KR0/pwwgmP9JDY1Ad2N82lW92ND r25z5HdUcrCIMbBICumyJJ4u69Fav0flx3OPW9h5rAygQxh4OIUgImU5jIynDAuWLrR4WuVhQ+L SsmPo3eTEuxWs61gtDkqeubh9f/fChkZfgmVqKat7979P2LT7E3XJJzc5p5k6LzGfOdTYpR+dLg hAwA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788795479049685291 X-GMAIL-MSGID: 1788795479049685291 From: Conor Dooley After splitting the MSSPLL in two, the PLL outputs have become open-coded versions of clk_divider. Drop the custom clk ops structs, and instead use the generic clk_divider_ops. Signed-off-by: Conor Dooley --- drivers/clk/microchip/clk-mpfs.c | 81 ++++++-------------------------- 1 file changed, 14 insertions(+), 67 deletions(-) diff --git a/drivers/clk/microchip/clk-mpfs.c b/drivers/clk/microchip/clk-mpfs.c index bed6adbb8a70..22eab91a6712 100644 --- a/drivers/clk/microchip/clk-mpfs.c +++ b/drivers/clk/microchip/clk-mpfs.c @@ -61,13 +61,10 @@ struct mpfs_msspll_hw_clock { struct mpfs_msspll_out_hw_clock { void __iomem *base; - struct clk_hw hw; + struct clk_divider output; struct clk_init_data init; unsigned int id; u32 reg_offset; - u32 shift; - u32 width; - u32 flags; }; #define to_mpfs_msspll_out_clk(_hw) container_of(_hw, struct mpfs_msspll_out_hw_clock, hw) @@ -177,75 +174,25 @@ static int mpfs_clk_register_mssplls(struct device *dev, struct mpfs_msspll_hw_c * MSS PLL output clocks */ -static unsigned long mpfs_clk_msspll_out_recalc_rate(struct clk_hw *hw, unsigned long prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; - u32 postdiv; - - postdiv = readl_relaxed(postdiv_addr) >> msspll_out_hw->shift; - postdiv &= clk_div_mask(msspll_out_hw->width); - - return prate / postdiv; -} - -static long mpfs_clk_msspll_out_round_rate(struct clk_hw *hw, unsigned long rate, - unsigned long *prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - - return divider_round_rate(hw, rate, prate, NULL, msspll_out_hw->width, - msspll_out_hw->flags); -} - -static int mpfs_clk_msspll_out_set_rate(struct clk_hw *hw, unsigned long rate, unsigned long prate) -{ - struct mpfs_msspll_out_hw_clock *msspll_out_hw = to_mpfs_msspll_out_clk(hw); - void __iomem *postdiv_addr = msspll_out_hw->base + msspll_out_hw->reg_offset; - u32 postdiv; - int divider_setting; - unsigned long flags; - - divider_setting = divider_get_val(rate, prate, NULL, msspll_out_hw->width, - msspll_out_hw->flags); - - if (divider_setting < 0) - return divider_setting; - - spin_lock_irqsave(&mpfs_clk_lock, flags); - - postdiv = readl_relaxed(postdiv_addr); - postdiv &= ~(clk_div_mask(msspll_out_hw->width) << msspll_out_hw->shift); - writel_relaxed(postdiv, postdiv_addr); - - spin_unlock_irqrestore(&mpfs_clk_lock, flags); - - return 0; -} - -static const struct clk_ops mpfs_clk_msspll_out_ops = { - .recalc_rate = mpfs_clk_msspll_out_recalc_rate, - .round_rate = mpfs_clk_msspll_out_round_rate, - .set_rate = mpfs_clk_msspll_out_set_rate, -}; - #define CLK_PLL_OUT(_id, _name, _parent, _flags, _shift, _width, _offset) { \ .id = _id, \ - .shift = _shift, \ - .width = _width, \ + .output.shift = _shift, \ + .output.width = _width, \ + .output.table = NULL, \ .reg_offset = _offset, \ - .flags = _flags, \ - .hw.init = CLK_HW_INIT(_name, _parent, &mpfs_clk_msspll_out_ops, 0), \ + .output.flags = _flags, \ + .output.hw.init = CLK_HW_INIT(_name, _parent, &clk_divider_ops, 0), \ + .output.lock = &mpfs_clk_lock, \ } static struct mpfs_msspll_out_hw_clock mpfs_msspll_out_clks[] = { - CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL0, "clk_msspll", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), - CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL1, "clk_msspll1", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV01_CR), - CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL2, "clk_msspll2", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV02_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), - CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", 0, + CLK_PLL_OUT(CLK_MSSPLL3, "clk_msspll3", "clk_msspll_internal", CLK_DIVIDER_ONE_BASED, MSSPLL_POSTDIV13_SHIFT, MSSPLL_POSTDIV_WIDTH, REG_MSSPLL_POSTDIV23_CR), }; @@ -259,13 +206,13 @@ static int mpfs_clk_register_msspll_outs(struct device *dev, for (i = 0; i < num_clks; i++) { struct mpfs_msspll_out_hw_clock *msspll_out_hw = &msspll_out_hws[i]; - msspll_out_hw->base = data->msspll_base; - ret = devm_clk_hw_register(dev, &msspll_out_hw->hw); + msspll_out_hw->output.reg = data->msspll_base + msspll_out_hw->reg_offset; + ret = devm_clk_hw_register(dev, &msspll_out_hw->output.hw); if (ret) return dev_err_probe(dev, ret, "failed to register msspll out id: %d\n", msspll_out_hw->id); - data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->hw; + data->hw_data.hws[msspll_out_hw->id] = &msspll_out_hw->output.hw; } return 0; From patchwork Mon Jan 22 12:19:55 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 190138 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2532245dyb; Mon, 22 Jan 2024 04:23:58 -0800 (PST) X-Google-Smtp-Source: AGHT+IHxSxDM4lQsOGcy6OBIdHUVJXFyZd5u0ah1QwMtQWJ5uulertjk5HVWvxognCw1NqIWH2T0 X-Received: by 2002:a05:620a:4799:b0:781:c142:8cd0 with SMTP id dt25-20020a05620a479900b00781c1428cd0mr4457790qkb.77.1705926238625; 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Michael Turquette , Stephen Boyd , linux-can@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 7/7] riscv: dts: microchip: add missing CAN bus clocks Date: Mon, 22 Jan 2024 12:19:55 +0000 Message-ID: <20240122-splice-poncho-18a369c7dbc7@spud> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20240122-catty-roast-d3625dbb02fe@spud> References: <20240122-catty-roast-d3625dbb02fe@spud> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1347; i=conor.dooley@microchip.com; h=from:subject:message-id; bh=pLA+R73nzpZMSjL5ZIEEpNbYsZjEzmZPe5bK/xmNjSY=; b=owGbwMvMwCFWscWwfUFT0iXG02pJDKnrYlPleT5Wn+6OL38lGp3sdiX9kvjzCpZLh79GzvM5s zmRq2ByRykLgxgHg6yYIkvi7b4WqfV/XHY497yFmcPKBDKEgYtTACZS+YmRYZunivptLuErjQu/ N1lXLrlwi/XW5XCGE7N82m+Ic7Ruv83wz+SeTKeekUOK973a71eDBd/2iDnWPnL2uLo3PEXiktF WJgA= X-Developer-Key: i=conor.dooley@microchip.com; a=openpgp; fpr=F9ECA03CF54F12CD01F1655722E2C55B37CF380C X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788793311562600891 X-GMAIL-MSGID: 1788793311562600891 From: Conor Dooley The CAN controller on PolarFire SoC has an AHB peripheral clock _and_ a CAN bus clock. The bus clock was omitted when the binding was written, but is required for operation. Make up for lost time and add to the DT. Fixes: 38a71fc04895 ("riscv: dts: microchip: add mpfs's CAN controllers") Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index 266489d43912..4d70df0f908c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -416,7 +416,7 @@ i2c1: i2c@2010b000 { can0: can@2010c000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010c000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN0>; + clocks = <&clkcfg CLK_CAN0>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <56>; status = "disabled"; @@ -425,7 +425,7 @@ can0: can@2010c000 { can1: can@2010d000 { compatible = "microchip,mpfs-can"; reg = <0x0 0x2010d000 0x0 0x1000>; - clocks = <&clkcfg CLK_CAN1>; + clocks = <&clkcfg CLK_CAN1>, <&clkcfg CLK_MSSPLL3>; interrupt-parent = <&plic>; interrupts = <57>; status = "disabled";