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Use the pre-processor to put the attributes in place (like we already do for AddrPrefixOpReg), rather than spelling them out explicitly in every respective template. This reduces line length - and hence improves readability - for many templates. --- a/opcodes/i386-opc.tbl +++ b/opcodes/i386-opc.tbl @@ -75,12 +75,17 @@ #define Size32 Size=SIZE32 #define Size64 Size=SIZE64 +#define IsPrefix IsPrefix|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf + #define AddrPrefixOpReg OperandConstraint=ADDR_PREFIX_OP_REG | \ No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf #define Anysize OperandConstraint=ANY_SIZE -#define DistinctDest OperandConstraint=DISTINCT_DEST -#define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 -#define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP +#define DistinctDest OperandConstraint=DISTINCT_DEST | \ + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf +#define Implicit1stXmm0 OperandConstraint=IMPLICIT_1ST_XMM0 | \ + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf +#define ImplicitQuadGroup OperandConstraint=IMPLICIT_QUAD_GROUP | \ + No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf #define NoDefMask OperandConstraint=NO_DEFAULT_MASK #define RegKludge OperandConstraint=REG_KLUDGE #define SwapSources OperandConstraint=SWAP_SOURCES @@ -125,6 +130,11 @@ #define VecSIB512 SIB=VECSIB512 #define Sibmem SIB=SIBMEM|Modrm +#define SIB No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SIB +#define VexSources No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VexSources +#define Broadcast No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Broadcast +#define Masking No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Masking + #define EVex128 EVex=EVEX128 #define EVex256 EVex=EVEX256 #define EVex512 EVex=EVEX512 @@ -828,60 +838,60 @@ fwait, 0x9b, None, CpuFP, No_bSuf|No_wSu // Opcode prefixes; we allow them as separate insns too. -addr16, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -addr32, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -aword, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -adword, 0x67, None, Cpu386, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -data16, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -data32, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -word, 0x66, None, Cpu386, Size16|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -dword, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -lock, 0xf0, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -wait, 0x9b, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -cs, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -ds, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -es, 0x26, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -fs, 0x64, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -gs, 0x65, None, Cpu386, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -ss, 0x36, None, CpuNo64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rep, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -repe, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -repz, 0xf3, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -repne, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -repnz, 0xf2, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -ht, 0x3e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -hnt, 0x2e, None, 0, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex, 0x40, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexz, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexy, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexyz, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexx, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexxz, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexxy, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rexxyz, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64z, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64y, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64yz, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64x, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64xz, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64xy, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex64xyz, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.b, 0x41, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.x, 0x42, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.xb, 0x43, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.r, 0x44, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.rb, 0x45, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.rx, 0x46, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.rxb, 0x47, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.w, 0x48, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wb, 0x49, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wx, 0x4a, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wxb, 0x4b, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wr, 0x4c, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wrb, 0x4d, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wrx, 0x4e, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -rex.wrxb, 0x4f, None, Cpu64, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} +addr16, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|IsPrefix, {} +addr32, 0x67, None, Cpu386, Size32|IgnoreSize|IsPrefix, {} +aword, 0x67, None, Cpu386|CpuNo64, Size16|IgnoreSize|IsPrefix, {} +adword, 0x67, None, Cpu386, Size32|IgnoreSize|IsPrefix, {} +data16, 0x66, None, Cpu386, Size16|IgnoreSize|IsPrefix, {} +data32, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|IsPrefix, {} +word, 0x66, None, Cpu386, Size16|IgnoreSize|IsPrefix, {} +dword, 0x66, None, Cpu386|CpuNo64, Size32|IgnoreSize|IsPrefix, {} +lock, 0xf0, None, 0, IsPrefix, {} +wait, 0x9b, None, 0, IsPrefix, {} +cs, 0x2e, None, 0, IsPrefix, {} +ds, 0x3e, None, 0, IsPrefix, {} +es, 0x26, None, CpuNo64, IsPrefix, {} +fs, 0x64, None, Cpu386, IsPrefix, {} +gs, 0x65, None, Cpu386, IsPrefix, {} +ss, 0x36, None, CpuNo64, IsPrefix, {} +rep, 0xf3, None, 0, IsPrefix, {} +repe, 0xf3, None, 0, IsPrefix, {} +repz, 0xf3, None, 0, IsPrefix, {} +repne, 0xf2, None, 0, IsPrefix, {} +repnz, 0xf2, None, 0, IsPrefix, {} +ht, 0x3e, None, 0, IsPrefix, {} +hnt, 0x2e, None, 0, IsPrefix, {} +rex, 0x40, None, Cpu64, IsPrefix, {} +rexz, 0x41, None, Cpu64, IsPrefix, {} +rexy, 0x42, None, Cpu64, IsPrefix, {} +rexyz, 0x43, None, Cpu64, IsPrefix, {} +rexx, 0x44, None, Cpu64, IsPrefix, {} +rexxz, 0x45, None, Cpu64, IsPrefix, {} +rexxy, 0x46, None, Cpu64, IsPrefix, {} +rexxyz, 0x47, None, Cpu64, IsPrefix, {} +rex64, 0x48, None, Cpu64, IsPrefix, {} +rex64z, 0x49, None, Cpu64, IsPrefix, {} +rex64y, 0x4a, None, Cpu64, IsPrefix, {} +rex64yz, 0x4b, None, Cpu64, IsPrefix, {} +rex64x, 0x4c, None, Cpu64, IsPrefix, {} +rex64xz, 0x4d, None, Cpu64, IsPrefix, {} +rex64xy, 0x4e, None, Cpu64, IsPrefix, {} +rex64xyz, 0x4f, None, Cpu64, IsPrefix, {} +rex.b, 0x41, None, Cpu64, IsPrefix, {} +rex.x, 0x42, None, Cpu64, IsPrefix, {} +rex.xb, 0x43, None, Cpu64, IsPrefix, {} +rex.r, 0x44, None, Cpu64, IsPrefix, {} +rex.rb, 0x45, None, Cpu64, IsPrefix, {} +rex.rx, 0x46, None, Cpu64, IsPrefix, {} +rex.rxb, 0x47, None, Cpu64, IsPrefix, {} +rex.w, 0x48, None, Cpu64, IsPrefix, {} +rex.wb, 0x49, None, Cpu64, IsPrefix, {} +rex.wx, 0x4a, None, Cpu64, IsPrefix, {} +rex.wxb, 0x4b, None, Cpu64, IsPrefix, {} +rex.wr, 0x4c, None, Cpu64, IsPrefix, {} +rex.wrb, 0x4d, None, Cpu64, IsPrefix, {} +rex.wrx, 0x4e, None, Cpu64, IsPrefix, {} +rex.wrxb, 0x4f, None, Cpu64, IsPrefix, {} // Pseudo prefixes (base_opcode == PSEUDO_PREFIX) @@ -890,7 +900,7 @@ rex.wrxb, 0x4f, None, Cpu64, No_bSuf|No_ vex:VEX:0, vex2:VEX:0, vex3:VEX3:0, evex:EVEX:0, + rex:REX:Cpu64, nooptimize:NoOptimize:0> -{}, PSEUDO_PREFIX, Prefix_, , No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} +{}, PSEUDO_PREFIX, Prefix_, , IsPrefix, {} // 486 extensions. @@ -1345,8 +1355,8 @@ pabsd, 0x0f381e, None, blendp, 0x660f3a0c | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -blendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , None, CpuAVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|VexSources=2|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +blendvp, 0x664a | , None, CpuAVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|VexSources=2|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } blendvp, 0x660f3814 | , None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } dpp, 0x660f3a40 | , None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1358,8 +1368,8 @@ insertps, 0x660f3a21, None, , 0x660f382a, None, , Modrm||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegXMM } mpsadbw, 0x660f3a42, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } packusdw, 0x660f382b, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } -pblendvb, 0x664c, None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV=1|VexW=1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, None, CpuAVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|VexSources=2|SSE2AVX, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } +pblendvb, 0x664c, None, CpuAVX, Modrm|Vex128|Space0F3A|VexVVVV|VexW0|VexSources=2|Implicit1stXmm0|SSE2AVX, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Acc|Xmmword, RegXMM|Unspecified|BaseIndex, RegXMM } pblendvb, 0x660f3810, None, CpuSSE4_1, Modrm|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM } pblendw, 0x660f3a0e, None, , Modrm|||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1492,7 +1502,7 @@ vaddsubps, 0xf2d0, None, CpuAVX, Modrm|V vandnp, 0x55, None, CpuAVX, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vandp, 0x54, None, CpuAVX, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vblendp, 0x660c | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vblendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vblendvp, 0x664a | , None, CpuAVX, Modrm|Vex|Space0F3A|VexVVVV|VexW0|VexSources=2|CheckRegSize, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vbroadcastf128, 0x661a, None, CpuAVX, Modrm|Vex=2|Space0F38|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Xmmword|Unspecified|BaseIndex, RegYMM } vbroadcastsd, 0x6619, None, CpuAVX, Modrm|Vex256|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } vbroadcastss, 0x6618, None, CpuAVX, Modrm|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM|RegYMM } @@ -1588,7 +1598,7 @@ vpalignr, 0x660f, None, CpuAVX|CpuAVX2, vpand, 0x66db, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpandn, 0x66df, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpavg, 0x66e0 | (3 * ), None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpblendvb, 0x664c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpblendvb, 0x664c, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|VexSources=2, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpblendw, 0x660e, None, CpuAVX|CpuAVX2, Modrm|Vex|Space0F3A|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeq, 0x6674 | , None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcmpeqd, 0x6676, None, CpuAVX|CpuAVX2, Modrm|C|Vex|Space0F|VexVVVV|VexWIG|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } @@ -1749,18 +1759,18 @@ vpsravd, 0x6646, None, CpuAVX2, Modrm|Ve vpsrlv, 0x6645, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } // AVX gather instructions -vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex=2|Space0F38|VexVVVV|VexW1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp, 0x6693, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex128|Space0F38|VexVVVV|VexW0|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV|VexW1|CheckRegSize|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq, 0x6691, None, CpuAVX2, Modrm|Vex|Space0F38|VexVVVV||VecSIB128, { RegXMM, |Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW0|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, None, CpuAVX2, Modrm|Vex256|Space0F38|VexVVVV|VexW1|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex, RegYMM } // AES + AVX @@ -1814,8 +1824,8 @@ vfnmsubs, 0x668f | 0x, // HLE prefixes -xacquire, 0xf2, None, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} -xrelease, 0xf3, None, CpuHLE, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} +xacquire, 0xf2, None, CpuHLE, IsPrefix, {} +xrelease, 0xf3, None, CpuHLE, IsPrefix, {} // RTM instructions xabort, 0xc6f8, None, CpuRTM, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8 } @@ -1835,16 +1845,16 @@ shrx, 0xf2f7, None, CpuBMI2, Modrm|Check // FMA4 instructions -vfmaddp, 0x6668 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmadds, 0x666a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfmaddsubp, 0x665c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubaddp, 0x665e | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubp, 0x666c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfmsubs, 0x666e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmaddp, 0x6678 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmadds, 0x667a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } -vfnmsubp, 0x667c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vfnmsubs, 0x667e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddp, 0x6668 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmadds, 0x666a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfmaddsubp, 0x665c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubaddp, 0x665e | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubp, 0x666c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfmsubs, 0x666e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmaddp, 0x6678 | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmadds, 0x667a | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } +vfnmsubp, 0x667c | , None, CpuFMA4, D|Modrm|Vex|Space0F3A|VexVVVV|VexW1|VexSources=2|CheckRegSize, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vfnmsubs, 0x667e | , None, CpuFMA4, D|Modrm|VexLIG|Space0F3A|VexVVVV|VexW1|VexSources=2, { |Unspecified|BaseIndex|RegXMM, RegXMM, RegXMM, RegXMM } // XOP instructions @@ -1854,11 +1864,11 @@ vfnmsubs, 0x667e | , None, C vfrczp, 0x80 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM } vfrczs, 0x82 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { |RegXMM|Unspecified|BaseIndex, RegXMM } -vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpcmov, 0xa2, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|CheckRegSize|Vex, { RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vpcom, 0xcc | 0x | , None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } vpcom, 0xcc | 0x | , , CpuXOP, Modrm|Vex128|SpaceXOP08|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } -vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW0|Vex|VexSources=2|CheckRegSize, { Imm8, RegXMM|RegYMM, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } +vpermil2p, 0x6648 | , None, CpuXOP, Modrm|Space0F3A|VexVVVV|VexW1|Vex|VexSources=2|CheckRegSize, { Imm8, Unspecified|BaseIndex|RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM, RegXMM|RegYMM } vphaddb, 0xc2 | , None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphaddbw, 0xc1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphadddq, 0xcb, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } @@ -1870,23 +1880,23 @@ vphaddw, 0xc6 | , None, CpuX vphsubbw, 0xe1, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubdq, 0xe3, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } vphsubwd, 0xe2, None, CpuXOP, Modrm|SpaceXOP09|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf|Vex, { RegXMM|Unspecified|BaseIndex, RegXMM } -vpmacsdd, 0x9e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdqh, 0x9f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsdql, 0x97, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdd, 0x8e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdqh, 0x8f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssdql, 0x87, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsswd, 0x86, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacssww, 0x85, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacswd, 0x96, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmacsww, 0x95, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } -vprot, 0x90 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vprot, 0xc0 | , None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } -vpsha, 0x98 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } -vpshl, 0x94 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_ldSuf|No_qSuf, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vpmacsdd, 0x9e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdqh, 0x9f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsdql, 0x97, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdd, 0x8e, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdqh, 0x8f, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssdql, 0x87, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsswd, 0x86, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacssww, 0x85, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacswd, 0x96, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmacsww, 0x95, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcsswd, 0xa6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpmadcswd, 0xb6, None, CpuXOP, Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vpperm, 0xa3, None, CpuXOP, D|Modrm|SpaceXOP08|VexSources=2|VexVVVV|VexW0|Vex, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM, RegXMM } +vprot, 0x90 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vprot, 0xc0 | , None, CpuXOP, Modrm|Vex128|SpaceXOP08|VexW0|VexSources=1, { Imm8, RegXMM|Unspecified|BaseIndex, RegXMM } +vpsha, 0x98 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } +vpshl, 0x94 | , None, CpuXOP, D|Modrm|Vex128|SpaceXOP09|VexW0|VexSources=1, { RegXMM, RegXMM|Unspecified|BaseIndex, RegXMM } @@ -2017,7 +2027,7 @@ clac, 0xf01ca, None, CpuSMAP, No_bSuf|No stac, 0xf01cb, None, CpuSMAP, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // BND prefix -bnd, 0xf2, None, CpuMPX, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} +bnd, 0xf2, None, CpuMPX, IsPrefix, {} // MPX instructions. bndmk, 0xf30f1b, None, CpuMPX, Modrm|Anysize|IgnoreSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { BaseIndex, RegBND } @@ -2087,97 +2097,97 @@ kshiftr, 0x6630, None, , Mo kunpckbw, 0x664B, None, CpuAVX512F, Modrm|Vex=2|Space0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask } -vaddp, 0x58, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vdivp, 0x5e, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmulp, 0x59, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vsqrtp, 0x51, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vsubp, 0x5c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vadds, 0x58, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vdivs, 0x5e, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vmuls, 0x59, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } - -valign, 0x6603, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpblendm, 0x6664, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2, 0x6676, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2, 0x667E, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxs, 0x663D, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxu, 0x663F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmins, 0x6639, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminu, 0x663B, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprolv, 0x6615, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vprorv, 0x6614, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllv, 0x6647, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrav, 0x6646, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlv, 0x6645, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpternlog, 0x6625, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vbroadcastf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti64x4, 0x665B, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM } - -vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vaddp, 0x58, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdivp, 0x5e, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmulp, 0x59, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vsqrtp, 0x51, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vsubp, 0x5c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vadds, 0x58, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vdivs, 0x5e, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vmuls, 0x59, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsqrts, 0x51, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vsubs, 0x5C, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +valign, 0x6603, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vblendmp, 0x6665, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpblendm, 0x6664, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2, 0x6676, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermi2p, 0x6677, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667E, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2p, 0x667F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxs, 0x663D, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxu, 0x663F, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmins, 0x6639, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminu, 0x663B, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuldq, 0x6628, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulld, 0x6640, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprolv, 0x6615, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vprorv, 0x6614, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllv, 0x6647, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrav, 0x6646, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlv, 0x6645, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpternlog, 0x6625, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vbroadcastf32x4, 0x661A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=4, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti32x4, 0x665A, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=4, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vbroadcastf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW1|Disp8MemShift=5, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti64x4, 0x665B, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW1|Disp8MemShift=5, { YMMword|Unspecified|BaseIndex, RegZMM } + +vbroadcastss, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcastsd, 0x6619, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpbroadcast, 0x6658 | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x667c, None, CpuAVX512F, Modrm|Masking=3|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { , RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x6658 | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Disp8MemShift, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x667c, None, CpuAVX512F, Modrm|Masking=3|Space0F38|, { , RegXMM|RegYMM|RegZMM } -vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp, 0xC2, 0x, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|ImmExt|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpp, 0xC2, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmps, 0xC2, 0x, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } -vcmps, 0xC2, None, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, 0x, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|SAE|ImmExt, { RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } +vcmps, 0xC2, None, CpuAVX512F, Modrm|EVexLIG|Masking=2|Space0F|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegMask } vcomis, 0x2f, None, , Modrm|EVexLIG|||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } vucomis, 0x2e, None, , Modrm|EVexLIG|||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM } -vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressq, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressd, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompresspd, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW1|Disp8MemShift=3|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vcompressps, 0x668A, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressq, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW1|Disp8MemShift=3|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressd, 0x668B, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Dword|Unspecified|BaseIndex } -vscatterqpd, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { RegZMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { RegZMM, Qword|Unspecified|BaseIndex } +vpscatterqd, 0x66A1, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { RegZMM, Dword|Unspecified|BaseIndex } +vscatterqpd, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512, { RegZMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { RegYMM, Dword|Unspecified|BaseIndex } -vcvtdq2pd, 0xF3E6, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F|VexW=1|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtdq2pd, 0xF3E6, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtudq2pd, 0xF37A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtdq2ps, 0x5B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2udq, 0x79, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } +vcvtpd2dq, 0xf2e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } -vcvtpd2ps, 0x665a, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } +vcvtpd2ps, 0x665a, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } -vcvtpd2udq, 0x79, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } +vcvtpd2udq, 0x79, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } -vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } +vcvtph2ps, 0x6613, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5|SAE, { RegYMM|Unspecified|BaseIndex, RegZMM } -vcvtps2dq, 0x665B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtps2dq, 0x665B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtps2pd, 0x5A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2pd, 0x5A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_ldSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2ph, 0x661D, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5|SAE, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } vcvts2si, 0x2d, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } vcvts2usi, 0x79, None, , Modrm|EVexLIG||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvtsd2ss, 0xF25A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2ss, 0xF25A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW1|Disp8MemShift=3|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|ATTSyntax, { Reg32|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2sd, 0xF22A, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -2193,98 +2203,98 @@ vcvtsi2ss, 0xF32A, None, CpuAVX512F, Mod vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtusi2ss, 0xF37B, None, CpuAVX512F, Modrm|EVexLIG|Space0F|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sd, 0xF35A, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F|VexVVVV|VexW0|Disp8MemShift=2|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } -vcvttpd2udq, 0x78, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } +vcvttpd2dq, 0x66e6, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } +vcvttpd2udq, 0x78, None, CpuAVX512F|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } -vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2dq, 0xF35B, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttps2udq, 0x78, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vcvtts2si, 0x2c, None, CpuAVX512F, Modrm|EVexLIG|Space0F|Disp8MemShift|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } vcvtts2usi, 0x78, None, , Modrm|EVexLIG||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, Reg32|Reg64 } -vcvtudq2ps, 0xF27A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtudq2ps, 0xF27A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandpd, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandq, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=3|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandpd, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandq, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=3|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vexpandps, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandd, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW=1|Disp8MemShift=2|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vexpandps, 0x6688, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandd, 0x6689, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=2|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vextractf32x4, 0x6619, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti32x4, 0x6639, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextractf32x4, 0x6619, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti32x4, 0x6639, None, CpuAVX512F, Modrm|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextractf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextractf64x4, 0x661B, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW1|Disp8MemShift=5, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti64x4, 0x663B, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW1|Disp8MemShift=5, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } vextractps, 0x6617, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg32|Dword|Unspecified|BaseIndex } vextractps, 0x6617, None, CpuAVX512F|Cpu64, RegMem|EVex128|Space0F3A|VexWIG|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, Reg64 } -vfixupimmp, 0x6654, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfixupimms, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfixupimmp, 0x6654, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfixupimms, 0x6655, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vgetmantp, 0x26, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetmants, 0x27, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vgetmantp, 0x26, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetmants, 0x27, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrndscalep, 0x08 | , None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrndscales, 0x0a | , None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrndscalep, 0x08 | , None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrndscales, 0x0a | , None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddp, 0x6688 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmadds, 0x6689 | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddsubp, 0x6686 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubp, 0x668a | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmsubs, 0x668b | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfmsubaddp, 0x6687 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmaddp, 0x668c | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmadds, 0x668d | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vfnmsubp, 0x668e | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfnmsubs, 0x668f | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } - -vscalefp, 0x662c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vscalefs, 0x662d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } - -vgatherdpd, 0x6692, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherdps, 0x6692, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vgatherqpd, 0x6693, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vgatherqps, 0x6693, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdd, 0x6690, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegZMM } -vpgatherdq, 0x6690, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM } -vpgatherqd, 0x6691, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherqq, 0x6691, None, CpuAVX512F, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegZMM } +vfmaddp, 0x6688 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmadds, 0x6689 | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddsubp, 0x6686 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubp, 0x668a | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmsubs, 0x668b | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfmsubaddp, 0x6687 | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmaddp, 0x668c | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmadds, 0x668d | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vfnmsubp, 0x668e | 0x, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfnmsubs, 0x668f | 0x, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +vscalefp, 0x662c, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vscalefs, 0x662d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|StaticRounding|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } + +vgatherdpd, 0x6692, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherdps, 0x6692, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex, RegZMM } +vgatherqpd, 0x6693, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512, { Qword|Unspecified|BaseIndex, RegZMM } +vgatherqps, 0x6693, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdd, 0x6690, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex, RegZMM } +vpgatherdq, 0x6690, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex, RegZMM } +vpgatherqd, 0x6691, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherqq, 0x6691, None, CpuAVX512F, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB512, { Qword|Unspecified|BaseIndex, RegZMM } vmovntdqa, 0x662A, None, CpuAVX512F, Modrm|Space0F38|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|YMMword|ZMMword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetexpp, 0x6642, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vgetexps, 0x6643, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vgetexpp, 0x6642, None, , Modrm|Masking=3|||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vgetexps, 0x6643, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vinsertf32x4, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti32x4, 0x6638, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinsertf32x4, 0x6618, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckRegSize, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti32x4, 0x6638, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW0|Disp8MemShift=4|CheckRegSize, { Imm8, RegXMM|XMMword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinsertf64x4, 0x661A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti64x4, 0x663A, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinsertf64x4, 0x661A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8MemShift=5, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti64x4, 0x663A, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8MemShift=5, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } vinsertps, 0x6621, None, CpuAVX512F, Modrm|EVex128|Space0F3A|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vmaxp, 0x5f, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmaxs, 0x5f, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vmaxp, 0x5f, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmaxs, 0x5f, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vminp, 0x5d, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmins, 0x5d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vminp, 0x5d, None, , Modrm|Masking=3||VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vmins, 0x5d, None, , Modrm|EVexLIG|Masking=3||VexVVVV||Disp8MemShift|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vmovap, 0x28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovap, 0x28, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vmovntp, 0x2B, None, CpuAVX512F, Modrm|Space0F||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovup, 0x10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovup, 0x10, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vmovd, 0x666E, None, CpuAVX512F, D|Modrm|EVex=2|Space0F|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32|Unspecified|BaseIndex, RegXMM } -vmovddup, 0xF212, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } +vmovddup, 0xF212, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW1|Disp8ShiftVL|CheckRegSize, { RegYMM|RegZMM|Unspecified|BaseIndex, RegYMM|RegZMM } -vmovdqa64, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqa32, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa64, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW1|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqa32, 0x666F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW0|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vmovntdq, 0x66E7, None, CpuAVX512F, Modrm|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, XMMword|YMMword|ZMMword|Unspecified|BaseIndex } -vmovdqu32, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu64, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu32, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW0|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu64, 0xF36F, None, CpuAVX512F, D|Modrm|MaskingMorZ|Space0F|VexW1|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vmovhlps, 0x12, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } vmovlhps, 0x16, None, CpuAVX512F, Modrm|EVex=4|Space0F|VexVVVV=1|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } @@ -2298,114 +2308,114 @@ vmovq, 0x666E, None, CpuAVX512F|Cpu64, D vmovq, 0xF37E, None, CpuAVX512F, Load|Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex|RegXMM, RegXMM } vmovq, 0x66D6, None, CpuAVX512F, Modrm|EVex=2|Space0F|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Qword|Unspecified|BaseIndex|RegXMM } -vmovs, 0x10, None, , D|Modrm|EVexLIG|MaskingMorZ|||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM } -vmovs, 0x10, None, , D|Modrm|EVexLIG|Masking=3||VexVVVV||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM, RegXMM } +vmovs, 0x10, None, , D|Modrm|EVexLIG|MaskingMorZ|||Disp8MemShift, { |Unspecified|BaseIndex, RegXMM } +vmovs, 0x10, None, , D|Modrm|EVexLIG|Masking=3||VexVVVV|, { RegXMM, RegXMM, RegXMM } -vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovshdup, 0xF316, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovsldup, 0xF312, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpabs, 0x661e | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpand, 0x66db, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpandn, 0x66df, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpor, 0x66eb, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub, 0x66fa | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpxor, 0x66ef, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpabs, 0x661e | , None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpaddd, 0x66FE, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddq, 0x66d4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpand, 0x66db, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpandn, 0x66df, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmuludq, 0x66f4, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpor, 0x66eb, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66fa | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhdq, 0x666A, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhqdq, 0x666d, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckldq, 0x6662, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklqdq, 0x666c, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpxor, 0x66ef, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x661e, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x661f, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x661e, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqd, 0x6676, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpeqq, 0x6629, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtd, 0x6666, None, CpuAVX512F, Modrm|Masking=2|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgtq, 0x6637, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, None, CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x661f, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x661e, , CpuAVX512F, Modrm|Masking=2|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|ImmExt, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestm, 0x6627, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm, 0xf327, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm, 0x6627, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf327, None, CpuAVX512F, Modrm|Masking=2|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermd, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermps, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermilp, 0x6604 | , None, CpuAVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpermilp, 0x660C | , None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermilp, 0x6604 | , None, CpuAVX512F, Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpermilp, 0x660C | , None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermpd, 0x6601, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermpd, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpermq, 0x6600, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vpermq, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermpd, 0x6601, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermpd, 0x6616, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vpermq, 0x6600, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vpermq, 0x6636, None, CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vpmovdb, 0xF331, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovdb, 0xF331, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsdb, 0xF321, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusdb, 0xF311, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovdw, 0xF333, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovdw, 0xF333, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqb, 0xF332, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqb, 0xF332, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegZMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovqd, 0xF335, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovqw, 0xF334, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovqw, 0xF334, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovsqw, 0xF324, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } +vpmovusqw, 0xF314, None, CpuAVX512F, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegZMM, RegXMM|Unspecified|BaseIndex } -vpmovsxbd, 0x6621, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbd, 0x6631, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbd, 0x6621, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbd, 0x6631, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbq, 0x6622, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovzxbq, 0x6632, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovsxbq, 0x6622, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } +vpmovzxbq, 0x6632, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegZMM } -vpmovsxdq, 0x6625, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxdq, 0x6635, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxdq, 0x6625, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxdq, 0x6635, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwd, 0x6623, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwd, 0x6633, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwd, 0x6623, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwd, 0x6633, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } -vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovsxwq, 0x6624, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegZMM } +vpmovzxwq, 0x6634, None, CpuAVX512F, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegZMM } -vprol, 0x6672, 1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpror, 0x6672, 0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vprol, 0x6672, 1, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpror, 0x6672, 0, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufd, 0x6670, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsll, 0x66f2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsll, 0x6672 | , 6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsra, 0x66e2, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsra, 0x6672, 4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrl, 0x66d2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrl, 0x6672 | , 2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsll, 0x66f2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsll, 0x6672 | , 6, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsra, 0x66e2, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsra, 0x6672, 4, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrl, 0x66d2 | , None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrl, 0x6672 | , 2, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV=2||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14p, 0x664C, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcp14s, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp14p, 0x664C, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcp14s, 0x664D, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt14p, 0x664E, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrt14s, 0x664F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt14p, 0x664E, None, CpuAVX512F, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrt14s, 0x664F, None, CpuAVX512F, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vshuff32x4, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi32x4, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff32x4, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi32x4, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshuff64x2, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufi64x2, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshuff64x2, 0x6623, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vshufi64x2, 0x6643, None, CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vshufp, 0xC6, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vshufp, 0xC6, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpckhp, 0x15, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vunpcklp, 0x14, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpckhp, 0x15, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vunpcklp, 0x14, None, CpuAVX512F, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512F instructions end. @@ -2414,39 +2424,39 @@ vunpcklp, 0x14, None, CpuAV vpbroadcastmb2q, 0xF32A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM } vpbroadcastmw2d, 0xF33A, None, CpuAVX512CD, Modrm|Space0F38|EVex=5|VexW=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpconflict, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpconflict, 0x66c4, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vplzcnt, 0x6644, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vplzcnt, 0x6644, None, CpuAVX512CD, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512CD instructions end. // AVX512ER instructions. -vexp2p, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vexp2p, 0x66C8, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrcp28p, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrcp28s, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrcp28p, 0x66CA, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vrcp28s, 0x66CB, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrt28p, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } -vrsqrt28s, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrt28p, 0x66CC, None, CpuAVX512ER, Modrm|EVex512|Masking=3|Space0F38||Broadcast|Disp8MemShift=6|SAE, { RegZMM||Unspecified|BaseIndex, RegZMM } +vrsqrt28s, 0x66CD, None, CpuAVX512ER, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV||Disp8MemShift|SAE, { RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512ER instructions end. // AVX512PF instructions. -vgatherpf0dpd, 0x66C6, 1, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } -vgatherpf0dps, 0x66C6, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } -vgatherpf0qp, 0x66C7, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex } -vgatherpf1dpd, 0x66C6, 2, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } -vgatherpf1dps, 0x66C6, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } -vgatherpf1qp, 0x66C7, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex } - -vscatterpf0dpd, 0x66C6, 5, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } -vscatterpf0dps, 0x66C6, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } -vscatterpf0qp, 0x66C7, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex } -vscatterpf1dpd, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex } -vscatterpf1dps, 0x66C6, 6, CpuAVX512PF, Modrm|EVex=1|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex } -vscatterpf1qp, 0x66C7, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex } +vgatherpf0dpd, 0x66C6, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex } +vgatherpf0dps, 0x66C6, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex } +vgatherpf0qp, 0x66C7, 1, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512, { |Unspecified|BaseIndex } +vgatherpf1dpd, 0x66C6, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex } +vgatherpf1dps, 0x66C6, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex } +vgatherpf1qp, 0x66C7, 2, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512, { |Unspecified|BaseIndex } + +vscatterpf0dpd, 0x66C6, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex } +vscatterpf0dps, 0x66C6, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex } +vscatterpf0qp, 0x66C7, 5, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512, { |Unspecified|BaseIndex } +vscatterpf1dpd, 0x66C6, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex } +vscatterpf1dps, 0x66C6, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB512, { Dword|Unspecified|BaseIndex } +vscatterpf1qp, 0x66C7, 6, CpuAVX512PF, Modrm|EVex512|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB512, { |Unspecified|BaseIndex } // AVX512PF instructions end. @@ -2488,107 +2498,107 @@ enclv, 0xf01c0, None, CpuSE1, No_bSuf|No // AVX512VL instructions. -vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vgatherqp, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM } -vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } -vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegYMM } -vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } -vpgatherq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Unspecified|BaseIndex, RegXMM } -vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Dword|Unspecified|BaseIndex, RegXMM } -vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Qword|Unspecified|BaseIndex, RegYMM } - -vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vpscatterq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseIndex } -vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } -vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Dword|Unspecified|BaseIndex } -vscatterqp, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, |Unspecified|BaseIndex } -vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, Qword|Unspecified|BaseIndex } -vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Dword|Unspecified|BaseIndex } - -vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } - -vmovddup, 0xF212, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } - -vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } -vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } - -vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } -vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } - -vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } - -vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } -vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } - -vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } -vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=2|Masking=3|Space0F38|VexWIG|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } -vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex=3|Masking=3|Space0F38|VexWIG|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vgatherdpd, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128, { Dword|Unspecified|BaseIndex, RegXMM } +vgatherdps, 0x6692, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { Dword|Unspecified|BaseIndex, RegYMM } +vgatherqp, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128, { |Unspecified|BaseIndex, RegXMM } +vgatherqpd, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex, RegYMM } +vgatherqps, 0x6693, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherdd, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { Dword|Unspecified|BaseIndex, RegYMM } +vpgatherdq, 0x6690, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128, { Qword|Unspecified|BaseIndex, RegXMM|RegYMM } +vpgatherq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128, { |Unspecified|BaseIndex, RegXMM } +vpgatherqd, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { Dword|Unspecified|BaseIndex, RegXMM } +vpgatherqq, 0x6691, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { Qword|Unspecified|BaseIndex, RegYMM } + +vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterdd, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex } +vpscatterdq, 0x66A0, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vpscatterq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128, { RegXMM, |Unspecified|BaseIndex } +vpscatterqd, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex } +vpscatterqq, 0x66A1, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterdpd, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB128, { RegXMM|RegYMM, Qword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB128, { RegXMM, Dword|Unspecified|BaseIndex } +vscatterdps, 0x66A2, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { RegYMM, Dword|Unspecified|BaseIndex } +vscatterqp, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=2|NoDefMask|Space0F38||Disp8MemShift|VecSIB128, { RegXMM, |Unspecified|BaseIndex } +vscatterqpd, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW1|Disp8MemShift=3|VecSIB256, { RegYMM, Qword|Unspecified|BaseIndex } +vscatterqps, 0x66A3, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=2|NoDefMask|Space0F38|VexW0|Disp8MemShift=2|VecSIB256, { RegXMM, Dword|Unspecified|BaseIndex } + +vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtdq2pd, 0xF3E6, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtudq2pd, 0xF37A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexW0|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2ps, 0x6613, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexW0|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2pd, 0x5A, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=3, { Imm8, RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vcvtps2ph, 0x661D, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=4, { Imm8, RegYMM, RegXMM|Unspecified|BaseIndex } + +vmovddup, 0xF212, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW1|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } + +vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovdb, 0xF331, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsdb, 0xF321, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusdb, 0xF311, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovdw, 0xF333, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsdw, 0xF323, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusdw, 0xF313, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovqb, 0xF332, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovsqb, 0xF322, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=1, { RegXMM, RegXMM|Word|Unspecified|BaseIndex } +vpmovusqb, 0xF312, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegYMM, RegXMM|Dword|Unspecified|BaseIndex } + +vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovqd, 0xF335, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqd, 0xF325, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } +vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqd, 0xF315, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovqw, 0xF334, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovsqw, 0xF324, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=2, { RegXMM, RegXMM|Dword|Unspecified|BaseIndex } +vpmovusqw, 0xF314, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegYMM, RegXMM|Qword|Unspecified|BaseIndex } + +vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxbd, 0x6621, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxbd, 0x6631, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } + +vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=1, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovsxbq, 0x6622, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=1, { RegXMM|Word|Unspecified|BaseIndex, RegXMM } +vpmovzxbq, 0x6632, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexW0|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxdq, 0x6625, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexW0|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexW0|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxdq, 0x6635, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexW0|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxwd, 0x6623, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxwd, 0x6633, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } + +vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovsxwq, 0x6624, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } +vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F38|VexWIG|Disp8MemShift=2, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM } +vpmovzxwq, 0x6634, None, CpuAVX512F|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F38|VexWIG|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM } // AVX512VL instructions end. @@ -2611,71 +2621,71 @@ kunpckwd, 0x4B, None, CpuAVX512BW, Modrm kshiftl, 0x6633, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } kshiftr, 0x6631, None, CpuAVX512BW, Modrm|Vex128|Space0F3A||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegMask, RegMask } -vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdbpsadbw, 0x6642, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vmovdqu8, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vmovdqu16, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu8, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW0|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vmovdqu16, 0xF26F, None, CpuAVX512BW, D|Modrm|MaskingMorZ|Space0F|VexW1|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpabs, 0x661c | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpmaxsb, 0x663C, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsb, 0x6638, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufb, 0x6600, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaddubsw, 0x6604, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminuw, 0x663A, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhrsw, 0x660B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpackssdw, 0x666B, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpacksswb, 0x6663, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackuswb, 0x6667, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpackusdw, 0x662B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpadd, 0x66fc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpadds, 0x66ec | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpaddus, 0x66dc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpavg, 0x66e0 | (3 * ), None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmaxub, 0x66DE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminub, 0x66DA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsub, 0x66f8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubs, 0x66e8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsubus, 0x66d8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhbw, 0x6668, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklbw, 0x6660, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpmaxsw, 0x66EE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpminsw, 0x66EA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhuw, 0x66E4, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmulhw, 0x66E5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmullw, 0x66D5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllw, 0x6671, 6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsllw, 0x66F1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsraw, 0x6671, 4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsraw, 0x66E1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x6671, 2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpsrlw, 0x66D1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpckhwd, 0x6669, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpunpcklwd, 0x6661, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpalignr, 0x660F, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpblendm, 0x6666, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x6678 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpbroadcast, 0x667a | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Reg32, RegXMM|RegYMM|RegZMM } - -vpermi2, 0x6675, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpermt2, 0x667d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vperm, 0x668d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsllvw, 0x6612, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsravw, 0x6611, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpsrlvw, 0x6610, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vpcmpeq, 0x6674 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpgt, 0x6664 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x663f, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x663e, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmp, 0x663f, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vpcmpu, 0x663e, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpabs, 0x661c | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpmaxsb, 0x663C, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsb, 0x6638, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshufb, 0x6600, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaddubsw, 0x6604, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxuw, 0x663E, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminuw, 0x663A, None, CpuAVX512BW, Modrm|Masking=3|VexWIG|Space0F38|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhrsw, 0x660B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpackssdw, 0x666B, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpacksswb, 0x6663, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackuswb, 0x6667, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpackusdw, 0x662B, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpadd, 0x66fc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpadds, 0x66ec | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpaddus, 0x66dc | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpavg, 0x66e0 | (3 * ), None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaxub, 0x66DE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminub, 0x66DA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsub, 0x66f8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubs, 0x66e8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsubus, 0x66d8 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhbw, 0x6668, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklbw, 0x6660, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpmaxsw, 0x66EE, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpminsw, 0x66EA, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhuw, 0x66E4, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmulhw, 0x66E5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullw, 0x66D5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllw, 0x6671, 6, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsllw, 0x66F1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsraw, 0x6671, 4, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsraw, 0x66E1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x6671, 2, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpsrlw, 0x66D1, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8MemShift=4|CheckRegSize, { RegXMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpckhwd, 0x6669, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpunpcklwd, 0x6661, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpalignr, 0x660F, None, CpuAVX512BW, Modrm|Masking=3|Space0F3A|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpblendm, 0x6666, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x6678 | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift, { RegXMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpbroadcast, 0x667a | , None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexW0, { Reg32, RegXMM|RegYMM|RegZMM } + +vpermi2, 0x6675, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpermt2, 0x667d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vperm, 0x668d, None, , Modrm|Masking=3|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsllvw, 0x6612, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsravw, 0x6611, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpsrlvw, 0x6610, None, CpuAVX512BW, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vpcmpeq, 0x6674 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpgt, 0x6664 | , None, CpuAVX512BW, Modrm|Masking=2|Space0F|VexWIG|VexVVVV|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x663f, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x663e, None, CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmp, 0x663f, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpcmpu, 0x663e, , CpuAVX512BW, Modrm|Masking=2|Space0F3A|VexVVVV||Disp8ShiftVL|CheckRegSize|ImmExt, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } vpslldq, 0x6673, 7, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vpsrldq, 0x6673, 3, CpuAVX512BW, Modrm|Space0F|VexWIG|VexVVVV=2|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } @@ -2689,37 +2699,37 @@ vpinsrw, 0x66C4, None, CpuAVX512BW, Modr vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Reg32|Reg64, RegXMM, RegXMM } vpinsrb, 0x6620, None, CpuAVX512BW, Modrm|EVex128|Space0F3A|VexWIG|VexVVVV|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, Byte|Unspecified|BaseIndex, RegXMM, RegXMM } -vpmaddwd, 0x66F5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmaddwd, 0x66F5, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexVVVV|VexWIG|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } vpmov2m, 0xf329, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask } vpmovm2, 0xf328, None, CpuAVX512BW, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpmovswb, 0xF320, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovuswb, 0xF310, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovwb, 0xF330, None, CpuAVX512BW, Modrm|EVex=1|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegZMM, RegYMM|Unspecified|BaseIndex } -vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } -vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|MaskingMorZ|Space0F38|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM, RegXMM|Unspecified|BaseIndex } - -vpmovsxbw, 0x6620, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW, Modrm|EVex=1|Masking=3|Space0F38|VexWIG|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegYMM|Unspecified|BaseIndex, RegZMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=2|Masking=3|VexWIG|Space0F38|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } -vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex=3|Masking=3|VexWIG|Space0F38|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovswb, 0xF320, None, CpuAVX512BW, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovswb, 0xF320, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovuswb, 0xF310, None, CpuAVX512BW, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovuswb, 0xF310, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovwb, 0xF330, None, CpuAVX512BW, Modrm|EVex512|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=5, { RegZMM, RegYMM|Unspecified|BaseIndex } +vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex128|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=3, { RegXMM, RegXMM|Qword|Unspecified|BaseIndex } +vpmovwb, 0xF330, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex256|MaskingMorZ|Space0F38|VexW0|Disp8MemShift=4, { RegYMM, RegXMM|Unspecified|BaseIndex } + +vpmovsxbw, 0x6620, None, CpuAVX512BW, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex128|Masking=3|VexWIG|Space0F38|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovsxbw, 0x6620, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex256|Masking=3|VexWIG|Space0F38|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } +vpmovzxbw, 0x6630, None, CpuAVX512BW, Modrm|EVex512|Masking=3|Space0F38|VexWIG|Disp8MemShift=5, { RegYMM|Unspecified|BaseIndex, RegZMM } +vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex128|Masking=3|VexWIG|Space0F38|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM } +vpmovzxbw, 0x6630, None, CpuAVX512BW|CpuAVX512VL, Modrm|EVex256|Masking=3|VexWIG|Space0F38|Disp8MemShift=4, { RegXMM|Unspecified|BaseIndex, RegYMM } vpsadbw, 0x66F6, None, CpuAVX512BW, Modrm|Space0F|VexVVVV=1|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshufhw, 0xF370, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshuflw, 0xF270, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshufhw, 0xF370, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpshuflw, 0xF270, None, CpuAVX512BW, Modrm|Masking=3|Space0F|VexWIG|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vptestm, 0x6626, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vptestnm, 0xf326, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestm, 0x6626, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vptestnm, 0xf326, None, CpuAVX512BW, Modrm|Masking=2|Space0F38|VexVVVV||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512BW instructions end. @@ -2735,76 +2745,76 @@ vptestnm, 0xf326, None, CpuAVX512BW, kadd, 0x4A, None, CpuAVX512DQ, Modrm|Vex256|Space0F|VexVVVV|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask, RegMask } ktest, 0x99, None, CpuAVX512DQ, Modrm|Vex128|Space0F|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegMask } -vandnp, 0x55, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vandp, 0x54, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vorp, 0x56, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vxorp, 0x57, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } - -vbroadcastf32x2, 0x6619, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcastf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM } -vbroadcasti32x2, 0x6659, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vbroadcasti32x8, 0x665B, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F38|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { YMMword|Unspecified|BaseIndex, RegZMM } - -vbroadcastf64x2, 0x661A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } -vbroadcasti64x2, 0x665A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } - -vcvtpd2qq, 0x667B, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtpd2uqq, 0x6679, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvtps2qq, 0x667B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtqq2pd, 0xF3E6, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } - -vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } - -vcvttps2qq, 0x667A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } -vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } - -vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Qword, } - -vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex=1|MaskingMorZ|Space0F3A|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } -vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } -vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex=1|Masking=3|Space0F3A|VexVVVV=1|VexW=1|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vandnp, 0x55, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vandp, 0x54, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vorp, 0x56, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vxorp, 0x57, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|Optimize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } + +vbroadcastf32x2, 0x6619, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcastf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5, { YMMword|Unspecified|BaseIndex, RegZMM } +vbroadcasti32x2, 0x6659, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW0|Disp8MemShift=3, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vbroadcasti32x8, 0x665B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F38|VexW0|Disp8MemShift=5, { YMMword|Unspecified|BaseIndex, RegZMM } + +vbroadcastf64x2, 0x661A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=4, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } +vbroadcasti64x2, 0x665A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=4, { XMMword|Unspecified|BaseIndex, RegYMM|RegZMM } + +vcvtpd2qq, 0x667B, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtpd2uqq, 0x6679, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvtps2qq, 0x667B, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2qq, 0x667B, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvtps2uqq, 0x6679, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|StaticRounding|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvtps2uqq, 0x6679, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtqq2pd, 0xF3E6, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuqq2pd, 0xF37A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvtqq2ps, 0x5b, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } + +vcvttpd2qq, 0x667A, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttpd2uqq, 0x6678, None, CpuAVX512DQ, Modrm|Masking=3|Space0F|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } + +vcvttps2qq, 0x667A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2qq, 0x667A, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } +vcvttps2uqq, 0x6678, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=5|SAE, { RegYMM|Dword|Unspecified|BaseIndex, RegZMM } +vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Dword|Qword|Unspecified|BaseIndex, RegXMM } +vcvttps2uqq, 0x6678, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=3|Space0F|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Dword|Unspecified|BaseIndex, RegYMM } + +vcvtuqq2ps, 0xf27a, None, CpuAVX512DQ|, Modrm||Masking=3|Space0F|VexW1|Broadcast|, { |Qword, } + +vextractf32x8, 0x661B, None, CpuAVX512DQ, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vextracti32x8, 0x663B, None, CpuAVX512DQ, Modrm|EVex512|MaskingMorZ|Space0F3A|VexW0|Disp8MemShift=5, { Imm8, RegZMM, RegYMM|Unspecified|BaseIndex } +vinsertf32x8, 0x661A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F3A|VexVVVV|VexW0|Disp8MemShift=5, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } +vinserti32x8, 0x663A, None, CpuAVX512DQ, Modrm|EVex512|Masking=3|Space0F3A|VexVVVV|VexW0|Disp8MemShift=5, { Imm8, RegYMM|Unspecified|BaseIndex, RegZMM, RegZMM } vpextr, 0x6616, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM, |Unspecified|BaseIndex } vpinsr, 0x6622, None, CpuAVX512DQ|, Modrm|EVex128|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, |Unspecified|BaseIndex, RegXMM, RegXMM } -vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW=2|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } -vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } -vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Disp8MemShift=4|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } - -vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } -vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } -vfpclasspz, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask } -vfpclasspx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } -vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegYMM||Unspecified|BaseIndex, RegMask } -vfpclasss, 0x67, None, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } +vextractf64x2, 0x6619, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW1|Disp8MemShift=4, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vextracti64x2, 0x6639, None, CpuAVX512DQ, Modrm|MaskingMorZ|Space0F3A|VexW1|Disp8MemShift=4, { Imm8, RegYMM|RegZMM, RegXMM|Unspecified|BaseIndex } +vinsertf64x2, 0x6618, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8MemShift=4|CheckRegSize, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } +vinserti64x2, 0x6638, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8MemShift=4|CheckRegSize, { Imm8, RegXMM|Unspecified|BaseIndex, RegYMM|RegZMM, RegYMM|RegZMM } + +vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|IntelSyntax, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegMask } +vfpclassp, 0x6666, None, CpuAVX512DQ, Modrm|Masking=2|Space0F3A||Broadcast|Disp8ShiftVL|ATTSyntax, { Imm8, RegXMM|RegYMM|RegZMM||BaseIndex, RegMask } +vfpclasspz, 0x6666, None, CpuAVX512DQ, Modrm|EVex512|Masking=2|Space0F3A||Broadcast|Disp8MemShift=6, { Imm8, RegZMM||Unspecified|BaseIndex, RegMask } +vfpclasspx, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex128|Masking=2|Space0F3A||Broadcast|Disp8MemShift=4, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } +vfpclasspy, 0x6666, None, CpuAVX512DQ|CpuAVX512VL, Modrm|EVex256|Masking=2|Space0F3A||Broadcast|Disp8MemShift=5, { Imm8, RegYMM||Unspecified|BaseIndex, RegMask } +vfpclasss, 0x67, None, , Modrm|EVexLIG|Masking=2|Space0F3A||Disp8MemShift, { Imm8, RegXMM||Unspecified|BaseIndex, RegMask } vpmov2m, 0xf339, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegMask } vpmovm2, 0xf338, None, CpuAVX512DQ, Modrm|EVexDYN|Space0F38||No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegMask, RegXMM|RegYMM|RegZMM } -vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmullq, 0x6640, None, CpuAVX512DQ, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vrangep, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vranges, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vrangep, 0x6650, None, CpuAVX512DQ, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vranges, 0x6651, None, CpuAVX512DQ, Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } -vreducep, 0x56, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vreduces, 0x57, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } +vreducep, 0x56, None, , Modrm|Masking=3|Space0F3A||Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vreduces, 0x57, None, , Modrm|EVexLIG|Masking=3|Space0F3A|VexVVVV||Disp8MemShift|SAE, { Imm8, RegXMM||Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512DQ instructions end. @@ -2816,8 +2826,8 @@ clwb, 0x660fae, 6, CpuCLWB, Modrm|Anysiz // AVX512IFMA instructions -vpmadd52huq, 0x66B5, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52huq, 0x66B5, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmadd52luq, 0x66B4, None, CpuAVX512IFMA, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512IFMA instructions end @@ -2830,61 +2840,61 @@ vpmadd52luq, 0x66B4, None, CpuAVX_IFMA, // AVX512VBMI instructions -vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpmultishiftqb, 0x6683, None, CpuAVX512VBMI, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512VBMI instructions end // AVX512_4FMAPS instructions -v4fmaddps, 0xf29a, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fnmaddps, 0xf2aa, None, CpuAVX512_4FMAPS, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -v4fmaddss, 0xf29b, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } -v4fnmaddss, 0xf2ab, None, CpuAVX512_4FMAPS, Modrm|EVex=4|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fmaddps, 0xf29a, None, CpuAVX512_4FMAPS, Modrm|EVex512|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fnmaddps, 0xf2aa, None, CpuAVX512_4FMAPS, Modrm|EVex512|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +v4fmaddss, 0xf29b, None, CpuAVX512_4FMAPS, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } +v4fnmaddss, 0xf2ab, None, CpuAVX512_4FMAPS, Modrm|EVexLIG|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegXMM, RegXMM } // AVX512_4FMAPS instructions end // AVX512_4VNNIW instructions -vp4dpwssd, 0xf252, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } -vp4dpwssds, 0xf253, None, CpuAVX512_4VNNIW, Modrm|EVex=1|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssd, 0xf252, None, CpuAVX512_4VNNIW, Modrm|EVex512|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } +vp4dpwssds, 0xf253, None, CpuAVX512_4VNNIW, Modrm|EVex512|Masking=3|Space0F38|VexVVVV|VexW0|Disp8MemShift=4|ImplicitQuadGroup, { XMMword|Unspecified|BaseIndex, RegZMM, RegZMM } // AVX512_4VNNIW instructions end // AVX512_VPOPCNTDQ instructions -vpopcnt, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt, 0x6655, None, CpuAVX512_VPOPCNTDQ, Modrm|Masking=3|Space0F38||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } // AVX512_VPOPCNTDQ instructions end // AVX512_VBMI2 instructions -vpcompressb, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpcompressw, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressb, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW0|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } +vpcompressw, 0x6663, None, CpuAVX512_VBMI2, Modrm|MaskingMorZ|Space0F38|VexW1|Disp8MemShift=1|CheckRegSize, { RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex } -vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW=2|Disp8MemShift=1|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandb, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW0|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpexpandw, 0x6662, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexW1|Disp8MemShift=1|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshldv, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldv, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldvw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdv, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdv, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdvw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F38|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshld, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshld, 0x6671, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshldw, 0x6670, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrd, 0x6673, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpshrdw, 0x6672, None, CpuAVX512_VBMI2, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VBMI2 instructions end // AVX512_VNNI instructions -vpdpbusd, 0x6650, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssd, 0x6652, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusd, 0x6650, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssd, 0x6652, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpbusds, 0x6651, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vpdpwssds, 0x6653, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpbusds, 0x6651, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vpdpwssds, 0x6653, None, CpuAVX512_VNNI, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_VNNI instructions end @@ -2911,17 +2921,17 @@ vpdpbsuds, 0xf351, None, CpuAVX_VNNI_INT // AVX512_BITALG instructions -vpopcnt, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38||Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vpopcnt, 0x6654, None, CpuAVX512_BITALG, Modrm|Masking=3|Space0F38||Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vpshufbitqmb, 0x668f, None, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vpshufbitqmb, 0x668f, None, CpuAVX512_BITALG, Modrm|Masking=2|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // AVX512_BITALG instructions end // AVX512 + GFNI instructions -vgf2p8affineinvqb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8affineqb, 0x66ce, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV=1|VexW=2|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vgf2p8mulb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV=1|VexW=1|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineinvqb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8affineqb, 0x66ce, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F3A|VexVVVV|VexW1|Broadcast|Disp8ShiftVL|CheckRegSize, { Imm8, RegXMM|RegYMM|RegZMM|Qword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vgf2p8mulb, 0x66cf, None, CpuGFNI|CpuAVX512F, Modrm|Masking=3|Space0F38|VexVVVV|VexW0|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512 + GFNI instructions end @@ -3016,7 +3026,7 @@ endbr64, 0xf30f1efa, None, CpuIBT, No_bS endbr32, 0xf30f1efb, None, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} // notrack prefix -notrack, 0x3e, None, CpuIBT, No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|IsPrefix, {} +notrack, 0x3e, None, CpuIBT, IsPrefix, {} // CET instructions end. @@ -3057,11 +3067,11 @@ movdir64b, 0x660f38f8, None, CpuMOVDIR64 // AVX512_BF16 instructions. -vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vcvtne2ps2bf16, 0xf272, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, Modrm|Space0F38||Masking=3|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { |Dword, } +vcvtneps2bf16, 0xf372, None, CpuAVX512_BF16|, Modrm|Space0F38||Masking=3|VexW0|Broadcast, { |Dword, } -vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vdpbf16ps, 0xf352, None, CpuAVX512_BF16, Modrm|Space0F38|VexVVVV|Masking=3|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } // AVX512_BF16 instructions end. @@ -3086,7 +3096,7 @@ enqcmds, 0xf30f38f8, None, CpuENQCMD, Mo // VP2INTERSECT instructions. -vp2intersect, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vp2intersect, 0xf268, None, CpuAVX512_VP2INTERSECT, Modrm|Space0F38|VexVVVV||Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM||Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } // VP2INTERSECT instructions end. @@ -3144,9 +3154,9 @@ tdpbuud, 0x5e, None, CpuAMX_INT8|Cpu64 tdpbusd, 0x665e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM } tdpbsud, 0xf35e, None, CpuAMX_INT8|Cpu64, Modrm|Vex128|Space0F38|VexVVVV=1|VexW0|SwapSources|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, RegTMM, RegTMM } -tileloadd, 0xf24b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegTMM } -tileloaddt1, 0x664b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Unspecified|BaseIndex, RegTMM } -tilestored, 0xf34b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegTMM, Unspecified|BaseIndex } +tileloadd, 0xf24b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0, { Unspecified|BaseIndex, RegTMM } +tileloaddt1, 0x664b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0, { Unspecified|BaseIndex, RegTMM } +tilestored, 0xf34b, None, CpuAMX_TILE|Cpu64, Sibmem|Vex128|Space0F38|VexW0, { RegTMM, Unspecified|BaseIndex } tilerelease, 0x49c0, None, CpuAMX_TILE|Cpu64, Vex128|Space0F38|VexW0|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, {} @@ -3197,62 +3207,62 @@ hreset, 0xf30f3af0c0, None, CpuHRESET, N // FP16 (HFNI) instructions. -vfcmaddcph, 0xf256, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmaddcsh, 0xf257, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmaddcph, 0xf256, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmaddcsh, 0xf257, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmaddcph, 0xf356, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmaddcsh, 0xf357, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmaddcph, 0xf356, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmaddcsh, 0xf357, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfcmulcph, 0xf2d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfcmulcph, 0xf2d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfcmulcsh, 0xf2d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } -vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vfmulcph, 0xf3d6, None, CpuAVX512_FP16, Modrm|VexVVVV|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|DistinctDest|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Dword|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegXMM|RegYMM|RegZMM } +vfmulcsh, 0xf3d7, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=2|DistinctDest|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcmpph, 0xc2, 0x, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpph, 0xc2, 0x, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|ImmExt|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } +vcmpph, 0xc2, None, CpuAVX512_FP16, Modrm|Masking=2|Space0F3A|VexVVVV|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { Imm8, RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM, RegMask } -vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpsh, 0xf3c2, 0x, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|ImmExt|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } +vcmpsh, 0xf3c2, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=2|Space0F3A|VexVVVV|VexW0|Disp8MemShift=1|SAE, { Imm8, RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegMask } -vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } -vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } +vcvtdq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|, { |Dword, } +vcvtudq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|, { |Dword, } -vcvtqq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf||, { |Qword, RegXMM } -vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf||, { |Qword, RegXMM } +vcvtqq2ph, 0x5b, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast||, { |Qword, RegXMM } +vcvtuqq2ph, 0xf27a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast||, { |Qword, RegXMM } -vcvtpd2ph, 0x665a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf||, { |Qword, RegXMM } +vcvtpd2ph, 0x665a, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW1|Broadcast||, { |Qword, RegXMM } -vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { |Dword, } +vcvtps2phx, 0x661d, None, CpuAVX512_FP16|, Modrm||Masking=3|EVexMap5|VexW0|Broadcast|, { |Dword, } -vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtw2ph, 0xf37d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtuw2ph, 0xf27d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2dq, 0x665b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2dq, 0x665b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2dq, 0x665b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2udq, 0x79, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2udq, 0x79, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2udq, 0x79, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|StaticRounding|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2qq, 0x667b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2qq, 0x667b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2qq, 0x667b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2uqq, 0x6679, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2uqq, 0x6679, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2uqq, 0x6679, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvtph2pd, 0x5a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } +vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvtph2pd, 0x5a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvtph2pd, 0x5a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } -vcvtph2w, 0x667d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtph2uw, 0x7d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2w, 0x667d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvtph2uw, 0x7d, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|StaticRounding|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvtsd2sh, 0xf25a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtss2sh, 0x1d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsd2sh, 0xf25a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW1|Disp8MemShift=3|StaticRounding|SAE, { RegXMM|Qword|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtss2sh, 0x1d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=2|StaticRounding|SAE, { RegXMM|Dword|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } @@ -3260,48 +3270,48 @@ vcvtsi2sh, 0xf32a, None, CpuAVX512_FP16, vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|IgnoreSize|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|ATTSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtusi2sh, 0xf37b, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|VexVVVV|Disp8ShiftVL|No_bSuf|No_wSuf|No_sSuf|No_ldSuf|StaticRounding|SAE|IntelSyntax, { Reg32|Reg64|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2sd, 0xf35a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vcvtsh2ss, 0x13, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2sd, 0xf35a, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap5|VexVVVV|VexW0|Disp8MemShift=1|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vcvtsh2ss, 0x13, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } vcvtsh2si, 0xf32d, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|StaticRounding|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2dq, 0xf35b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } - -vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvttph2udq, 0x78, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } - -vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2qq, 0x667a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } - -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } -vcvttph2uqq, 0x6678, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } - -vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } -vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } -vcvtph2psx, 0x6613, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } +vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2dq, 0xf35b, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2dq, 0xf35b, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvttph2udq, 0x78, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvttph2udq, 0x78, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=5|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } + +vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2qq, 0x667a, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2qq, 0x667a, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=2, { RegXMM|Word|Dword|Unspecified|BaseIndex, RegXMM } +vcvttph2uqq, 0x6678, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegYMM } +vcvttph2uqq, 0x6678, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap5|VexW0|Broadcast|Disp8MemShift=4|SAE, { RegXMM|Word|Unspecified|BaseIndex, RegZMM } + +vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex128|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=3, { RegXMM|Word|Qword|Unspecified|BaseIndex, RegXMM } +vcvtph2psx, 0x6613, None, CpuAVX512_FP16|CpuAVX512VL, Modrm|EVex256|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=4, { RegXMM|Word|Unspecified|BaseIndex, RegYMM } +vcvtph2psx, 0x6613, None, CpuAVX512_FP16, Modrm|EVex512|Masking=3|EVexMap6|VexW0|Broadcast|Disp8MemShift=5|SAE, { RegYMM|Word|Unspecified|BaseIndex, RegZMM } -vcvttph2w, 0x667c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vcvttph2uw, 0x7c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2w, 0x667c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vcvttph2uw, 0x7c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap5|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|SAE, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } vcvttsh2si, 0xf32c, None, CpuAVX512_FP16, Modrm|EVexLIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|SAE, { RegXMM|Word|Unspecified|BaseIndex, Reg32|Reg64 } -vfpclassph, 0x66, None, CpuAVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf|, { Imm8, |Word, RegMask } +vfpclassph, 0x66, None, CpuAVX512_FP16|, Modrm||Masking=2|Space0F3A|VexW0|Broadcast|, { Imm8, |Word, RegMask } vmovw, 0x666e, None, CpuAVX512_FP16, D|Modrm|EVex128|VexWIG|EVexMap5|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { Word|Unspecified|BaseIndex, RegXMM } vmovw, 0x667e, None, CpuAVX512_FP16, D|RegMem|EVex128|VexWIG|EVexMap5|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM, Reg32 } -vrcpph, 0x664c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrcpph, 0x664c, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrcpsh, 0x664d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrcpsh, 0x664d, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } -vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } +vrsqrtph, 0x664e, None, CpuAVX512_FP16, Modrm|Masking=3|EVexMap6|VexW0|Broadcast|Disp8ShiftVL|CheckRegSize, { RegXMM|RegYMM|RegZMM|Word|Unspecified|BaseIndex, RegXMM|RegYMM|RegZMM } -vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1|No_bSuf|No_wSuf|No_lSuf|No_sSuf|No_qSuf|No_ldSuf, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } +vrsqrtsh, 0x664f, None, CpuAVX512_FP16, Modrm|EVexLIG|Masking=3|EVexMap6|VexVVVV|VexW0|Disp8MemShift=1, { RegXMM|Word|Unspecified|BaseIndex, RegXMM, RegXMM } // FP16 (HFNI) instructions end.