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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788696276836432463 X-GMAIL-MSGID: 1788696276836432463 Some GPUs like the Adreno A305B has a patchid higher than 9, in this case 18. Make sure the regexes can account for that. Acked-by: Krzysztof Kozlowski Signed-off-by: Luca Weiss Reviewed-by: David Heidelberg --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index b019db954793..40b5c6bd11f8 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -23,7 +23,7 @@ properties: The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. items: - - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]$' + - pattern: '^qcom,adreno-[3-7][0-9][0-9]\.[0-9]+$' - const: qcom,adreno - description: | The driver is parsing the compat string for Imageon to @@ -127,7 +127,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' then: properties: @@ -203,7 +203,7 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]$' + pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: From patchwork Sun Jan 21 10:40:39 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 189807 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp2010876dyb; Sun, 21 Jan 2024 02:41:42 -0800 (PST) X-Google-Smtp-Source: AGHT+IHFuLGcdgGBKP/n2pBX1NdcXJijqDca1MPyWny8bDYIc1UJyfg2kHML94MWEUXo70nQNsrD X-Received: by 2002:ac8:57c9:0:b0:42a:df2:d706 with SMTP id w9-20020ac857c9000000b0042a0df2d706mr3362493qta.56.1705833702573; Sun, 21 Jan 2024 02:41:42 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705833702; cv=pass; d=google.com; s=arc-20160816; b=CEsGh3qUNKcfQoNJidYrZJTsr6JTI+Z06wvYDSDWYHCccJQ3pgr9yFnults4YKAQTo dZvvs6FESLdT0XyxqhIzaicgtHb/OGHM5eXbJm3EMWApHGQuWPMHZKttE8vcfqMvXADf HeUOJMcCVxmWdkihtZapbAW0Z/wKPHPoWsnQvAGsA361vtYtabVDFvzbsthllC+6BaNO P6BWux+TrRAB/swA0aVbzIlQa9CBVWf5/9pBaExkVrgaxpY2Gx801TnaqKZMguN7O/kt 3ZlRiz5/js719f6eC/UV6W5OgqCERgF8A7CkkmKEFJy3sBkix7mElSYvN0A8caBpYhwp Hhlw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:list-unsubscribe:list-subscribe:list-id:precedence :subject:date:from:dkim-signature; bh=qVcIC+S04BeGKYb2T0eRPq/ebiQMKsOjWAW4lcHz40g=; fh=+SRI1VeKmVaGGYxg8slCD/uOQWHdJo2H6VxeCiWFGUw=; b=N3ZhCcL61JZrk/Mw3e6i8ZuTgfw+NzsNGCKF2PNcNzv9ojDKVcVmNyNKUCJ92cBHzl R0czb1FmmA3TxY2kcvfwJ9uGpS2oIsaqXc+q4qr6LScMugj/1udABrgqJpbcLGcksiae 0OyCAk81aLa1+dDUu1ixcF4rVXh6EaRAMwAJSpKH7jT/srLQQorXl5c0kGSlqYcOu3B8 jeo9OoUH2BX9JoyY1SD6eC/tYXHaHtD1QPREVKOQobxYsWmNQmmYMgSX0f+a1Lf6BQ7C peuQs4HGZ2Jgzg+UW4EbBv9czN7Wy28bV/1bz93f+Wm4e8CgFHxlJh6iZdr2dR1DgVS0 YYtw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@z3ntu.xyz header.s=s1 header.b=lciop4r4; arc=pass (i=1 spf=pass spfdomain=z3ntu.xyz dkim=pass dkdomain=z3ntu.xyz dmarc=pass fromdomain=z3ntu.xyz); spf=pass (google.com: domain of linux-kernel+bounces-32014-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:45d1:ec00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-32014-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=z3ntu.xyz Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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b=lciop4r4CZbZekaT96/hHLsEzLdGobUf1m+PECD0gZ7By06vI7E1q2hC7vau/zay4 kbHDk5tEGcd7poho8A1O817ifJypF4lQ07vBfANrLXZdJaz3hKjX09ZmuIyPY+R2Xx CxR0sp/5lth1Zn+Om2LC9LZOwaK2fpXhgzxnGTP8= From: Luca Weiss Date: Sun, 21 Jan 2024 11:40:39 +0100 Subject: [PATCH v2 2/2] drm/msm/adreno: Add A305B support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Message-Id: <20240121-msm8226-gpu-v2-2-77f4a6fbbca4@z3ntu.xyz> References: <20240121-msm8226-gpu-v2-0-77f4a6fbbca4@z3ntu.xyz> In-Reply-To: <20240121-msm8226-gpu-v2-0-77f4a6fbbca4@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.4 X-Developer-Signature: v=1; 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788696280742068774 X-GMAIL-MSGID: 1788696280742068774 Add support for the Adreno 305B GPU that is found in MSM8226(v2) SoC. Previously this was mistakenly claimed to be supported but using wrong a configuration. In MSM8226v1 there's also a A305B but with chipid 0x03000510 which should work with the same configuration but due to lack of hardware for testing this is not added. Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: David Heidelberg --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 13 ++++++++++--- drivers/gpu/drm/msm/adreno/adreno_device.c | 15 +++++++++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 5 +++++ 3 files changed, 26 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index c86b377f6f0d..5273dc849838 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -134,6 +134,13 @@ static int a3xx_hw_init(struct msm_gpu *gpu) /* Set up AOOO: */ gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO_EN, 0x0000003c); gpu_write(gpu, REG_A3XX_VBIF_OUT_AXI_AOOO, 0x003c003c); + } else if (adreno_is_a305b(adreno_gpu)) { + gpu_write(gpu, REG_A3XX_VBIF_IN_RD_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_IN_WR_LIM_CONF0, 0x00181818); + gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_OUT_WR_LIM_CONF0, 0x00000018); + gpu_write(gpu, REG_A3XX_VBIF_DDR_OUT_MAX_BURST, 0x00000303); + gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); } else if (adreno_is_a306(adreno_gpu)) { gpu_write(gpu, REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB, 0x0003); gpu_write(gpu, REG_A3XX_VBIF_OUT_RD_LIM_CONF0, 0x0000000a); @@ -230,7 +237,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG, 0x00000001); /* Enable Clock gating: */ - if (adreno_is_a306(adreno_gpu)) + if (adreno_is_a305b(adreno_gpu) || adreno_is_a306(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xaaaaaaaa); else if (adreno_is_a320(adreno_gpu)) gpu_write(gpu, REG_A3XX_RBBM_CLOCK_CTL, 0xbfffffff); @@ -333,7 +340,7 @@ static int a3xx_hw_init(struct msm_gpu *gpu) AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB1_START(2) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_IB2_START(6) | AXXX_CP_QUEUE_THRESHOLDS_CSQ_ST_START(14)); - } else if (adreno_is_a330(adreno_gpu)) { + } else if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { /* NOTE: this (value take from downstream android driver) * includes some bits outside of the known bitfields. But * A330 has this "MERCIU queue" thing too, which might @@ -559,7 +566,7 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) goto fail; /* if needed, allocate gmem: */ - if (adreno_is_a330(adreno_gpu)) { + if (adreno_is_a330(adreno_gpu) || adreno_is_a305b(adreno_gpu)) { ret = adreno_gpu_ocmem_init(&adreno_gpu->base.pdev->dev, adreno_gpu, &a3xx_gpu->ocmem); if (ret) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 2ce7d7b1690d..f2768e52ed12 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -55,10 +55,17 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .chip_ids = ADRENO_CHIP_IDS( - 0x03000512, - 0x03000520 - ), + .chip_ids = ADRENO_CHIP_IDS(0x03000512), + .family = ADRENO_3XX, + .fw = { + [ADRENO_FW_PM4] = "a330_pm4.fw", + [ADRENO_FW_PFP] = "a330_pfp.fw", + }, + .gmem = SZ_128K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a3xx_gpu_init, + }, { + .chip_ids = ADRENO_CHIP_IDS(0x03000520), .family = ADRENO_3XX, .revn = 305, .fw = { diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index bc14df96feb0..d3c41af706df 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -256,6 +256,11 @@ static inline bool adreno_is_a305(const struct adreno_gpu *gpu) return adreno_is_revn(gpu, 305); } +static inline bool adreno_is_a305b(const struct adreno_gpu *gpu) +{ + return gpu->info->chip_ids[0] == 0x03000512; +} + static inline bool adreno_is_a306(const struct adreno_gpu *gpu) { /* yes, 307, because a305c is 306 */