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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:22:34.1830 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: be15154e-ee21-46de-93d7-08dc191b9b7a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB5942 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544111238235437 X-GMAIL-MSGID: 1788544111238235437 The word 11 which was reserved for various scattered CPUID feature bits ran out of bits. Add a word 21 for scattered feature bits. Signed-off-by: Babu Moger --- v2: This is new patch in v2. Added because feature word 11 is full now. --- arch/x86/include/asm/cpufeature.h | 6 ++++-- arch/x86/include/asm/cpufeatures.h | 6 +++++- arch/x86/include/asm/disabled-features.h | 3 ++- arch/x86/include/asm/required-features.h | 3 ++- 4 files changed, 13 insertions(+), 5 deletions(-) diff --git a/arch/x86/include/asm/cpufeature.h b/arch/x86/include/asm/cpufeature.h index a26bebbdff87..de394d8f6d16 100644 --- a/arch/x86/include/asm/cpufeature.h +++ b/arch/x86/include/asm/cpufeature.h @@ -91,8 +91,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 19, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 20, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(REQUIRED_MASK, 21, feature_bit) || \ REQUIRED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 21)) + BUILD_BUG_ON_ZERO(NCAPINTS != 22)) #define DISABLED_MASK_BIT_SET(feature_bit) \ ( CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 0, feature_bit) || \ @@ -116,8 +117,9 @@ extern const char * const x86_bug_flags[NBUGINTS*32]; CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 18, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 19, feature_bit) || \ CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 20, feature_bit) || \ + CHECK_BIT_IN_MASK_WORD(DISABLED_MASK, 21, feature_bit) || \ DISABLED_MASK_CHECK || \ - BUILD_BUG_ON_ZERO(NCAPINTS != 21)) + BUILD_BUG_ON_ZERO(NCAPINTS != 22)) #define cpu_has(c, bit) \ (__builtin_constant_p(bit) && REQUIRED_MASK_BIT_SET(bit) ? 1 : \ diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 29cb275a219d..26bd99a35eae 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -13,7 +13,7 @@ /* * Defines x86 CPU feature bits */ -#define NCAPINTS 21 /* N 32-bit words worth of info */ +#define NCAPINTS 22 /* N 32-bit words worth of info */ #define NBUGINTS 2 /* N 32-bit bug flags */ /* @@ -458,6 +458,10 @@ #define X86_FEATURE_IBPB_BRTYPE (20*32+28) /* "" MSR_PRED_CMD[IBPB] flushes all branch type predictions */ #define X86_FEATURE_SRSO_NO (20*32+29) /* "" CPU is not affected by SRSO */ +/* + * Extended auxiliary flags: For features scattered in various CPUID levels, word 21 + */ + /* * BUG word(s) */ diff --git a/arch/x86/include/asm/disabled-features.h b/arch/x86/include/asm/disabled-features.h index 36d0c1e05e60..784335a74f95 100644 --- a/arch/x86/include/asm/disabled-features.h +++ b/arch/x86/include/asm/disabled-features.h @@ -143,6 +143,7 @@ #define DISABLED_MASK18 (DISABLE_IBT) #define DISABLED_MASK19 0 #define DISABLED_MASK20 0 -#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) +#define DISABLED_MASK21 0 +#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22) #endif /* _ASM_X86_DISABLED_FEATURES_H */ diff --git a/arch/x86/include/asm/required-features.h b/arch/x86/include/asm/required-features.h index 7ba1726b71c7..e9187ddd3d1f 100644 --- a/arch/x86/include/asm/required-features.h +++ b/arch/x86/include/asm/required-features.h @@ -99,6 +99,7 @@ #define REQUIRED_MASK18 0 #define REQUIRED_MASK19 0 #define REQUIRED_MASK20 0 -#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21) +#define REQUIRED_MASK21 0 +#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 22) #endif /* _ASM_X86_REQUIRED_FEATURES_H */ From patchwork Fri Jan 19 18:22:04 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189636 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193164dyb; Fri, 19 Jan 2024 10:23:18 -0800 (PST) X-Google-Smtp-Source: AGHT+IFxGiSCVTlq3JWWFatrUjl8htM//QejvRurnI114Y+Ya1LT1OKLFCeilMbJGCZQlcgGGHrY X-Received: by 2002:a05:6a00:2355:b0:6d2:74fc:1f1e with SMTP id j21-20020a056a00235500b006d274fc1f1emr1855966pfj.14.1705688598052; Fri, 19 Jan 2024 10:23:18 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:22:42.0424 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 773abc58-ca1c-4f1e-d0a8-08dc191ba029 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB8778 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039107716532817 X-GMAIL-MSGID: 1788544127737345697 AMD hardware can support 256 or more RMIDs. However, bandwidth monitoring feature only guarantees that RMIDs currently assigned to a processor will be tracked by hardware. The counters of any other RMIDs which are no longer being tracked will be reset to zero. The MBM event counters return "Unavailable" for the RMIDs that are not active. Users can create 256 or more monitor groups. But there can be only limited number of groups that can be give guaranteed monitoring numbers. With ever changing configurations there is no way to definitely know which of these groups will be active for certain point of time. Users do not have the option to monitor a group or set of groups for certain period of time without worrying about RMID being reset in between. The ABMC feature provides an option to the user to assign an RMID to the hardware counter and monitor the bandwidth for a longer duration. The assigned RMID will be active until the user unassigns it manually. There is no need to worry about counters being reset during this period. Additionally, the user can specify a bitmask identifying the specific bandwidth types from the given source to track with the counter. Linux resctrl subsystem provides the interface to count maximum of two memory bandwidth events per group, from a combination of available total and local events. Keeping the current interface, users can assign a maximum of 2 ABMC counters per group. User will also have the option to assign only one counter to the group. If the system runs out of assignable ABMC counters, kernel will display an error. Users need to unassign an already assigned counter to make space for new assignments. AMD hardware provides total of 32 ABMC counters when supported. The feature can be detected via CPUID_Fn80000020_EBX_x00 bit 5. Bits Description 5 ABMC (Assignable Bandwidth Monitoring Counters) The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: Added dependency on X86_FEATURE_BMEC. --- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/kernel/cpu/cpuid-deps.c | 3 +++ arch/x86/kernel/cpu/scattered.c | 1 + 3 files changed, 5 insertions(+) diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h index 26bd99a35eae..ea57e4515da6 100644 --- a/arch/x86/include/asm/cpufeatures.h +++ b/arch/x86/include/asm/cpufeatures.h @@ -461,6 +461,7 @@ /* * Extended auxiliary flags: For features scattered in various CPUID levels, word 21 */ +#define X86_FEATURE_ABMC (21*32+ 0) /* "" Assignable Bandwidth Monitoring Counters */ /* * BUG word(s) diff --git a/arch/x86/kernel/cpu/cpuid-deps.c b/arch/x86/kernel/cpu/cpuid-deps.c index e462c1d3800a..44e8423628b7 100644 --- a/arch/x86/kernel/cpu/cpuid-deps.c +++ b/arch/x86/kernel/cpu/cpuid-deps.c @@ -70,6 +70,9 @@ static const struct cpuid_dep cpuid_deps[] = { { X86_FEATURE_CQM_MBM_LOCAL, X86_FEATURE_CQM_LLC }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_TOTAL }, { X86_FEATURE_BMEC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_TOTAL }, + { X86_FEATURE_ABMC, X86_FEATURE_CQM_MBM_LOCAL }, + { X86_FEATURE_ABMC, X86_FEATURE_BMEC }, { X86_FEATURE_AVX512_BF16, X86_FEATURE_AVX512VL }, { X86_FEATURE_AVX512_FP16, X86_FEATURE_AVX512BW }, { X86_FEATURE_ENQCMD, X86_FEATURE_XSAVES }, diff --git a/arch/x86/kernel/cpu/scattered.c b/arch/x86/kernel/cpu/scattered.c index 0dad49a09b7a..698f2ccb9ac1 100644 --- a/arch/x86/kernel/cpu/scattered.c +++ b/arch/x86/kernel/cpu/scattered.c @@ -47,6 +47,7 @@ static const struct cpuid_bit cpuid_bits[] = { { X86_FEATURE_MBA, CPUID_EBX, 6, 0x80000008, 0 }, { X86_FEATURE_SMBA, CPUID_EBX, 2, 0x80000020, 0 }, { X86_FEATURE_BMEC, CPUID_EBX, 3, 0x80000020, 0 }, + { X86_FEATURE_ABMC, CPUID_EBX, 5, 0x80000020, 0 }, { X86_FEATURE_PERFMON_V2, CPUID_EAX, 0, 0x80000022, 0 }, { X86_FEATURE_AMD_LBR_V2, CPUID_EAX, 1, 0x80000022, 0 }, { 0, 0, 0, 0, 0 } From patchwork Fri Jan 19 18:22:05 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189637 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193284dyb; Fri, 19 Jan 2024 10:23:34 -0800 (PST) X-Google-Smtp-Source: AGHT+IG8S1ibIu3S3AsLhn1D9kwSjppSPOBtQ2ADx5dMROAQzTuESEwCwC90X6t5RleFwKkdJ/m2 X-Received: by 2002:a05:6a20:6ca2:b0:19b:e91c:1a42 with SMTP id em34-20020a056a206ca200b0019be91c1a42mr222328pzb.55.1705688614189; Fri, 19 Jan 2024 10:23:34 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Signed-off-by: Babu Moger --- v2: No changes --- Documentation/admin-guide/kernel-parameters.txt | 2 +- Documentation/arch/x86/resctrl.rst | 1 + arch/x86/kernel/cpu/resctrl/core.c | 2 ++ 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index b28d80b5af33..68b2c4f799b7 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -5492,7 +5492,7 @@ rdt= [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, abmc. E.g. to turn on cmt and turn off mba use: rdt=cmt,!mba diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index a6279df64a9d..d816ded93c22 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -26,6 +26,7 @@ MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" +ABMC (Assignable Bandwidth Monitoring Counters) "" =============================================== ================================ Historically, new features were made visible by default in /proc/cpuinfo. This diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 19e0681f0435..4efe2d6a9eb7 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -678,6 +678,7 @@ enum { RDT_FLAG_MBA, RDT_FLAG_SMBA, RDT_FLAG_BMEC, + RDT_FLAG_ABMC, }; #define RDT_OPT(idx, n, f) \ @@ -703,6 +704,7 @@ static struct rdt_options rdt_options[] __initdata = { RDT_OPT(RDT_FLAG_MBA, "mba", X86_FEATURE_MBA), RDT_OPT(RDT_FLAG_SMBA, "smba", X86_FEATURE_SMBA), RDT_OPT(RDT_FLAG_BMEC, "bmec", X86_FEATURE_BMEC), + RDT_OPT(RDT_FLAG_ABMC, "abmc", X86_FEATURE_ABMC), }; #define NUM_RDT_OPTIONS ARRAY_SIZE(rdt_options) From patchwork Fri Jan 19 18:22:06 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189640 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193800dyb; Fri, 19 Jan 2024 10:24:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IGhb9DYII10lDyKPt7Um+SX3gskUUhOvkX24tgVZhlygfTPkEH3ppO2raZ/FdParRFNCwfN X-Received: by 2002:a05:6a20:160d:b0:19a:3bd7:dc77 with SMTP id l13-20020a056a20160d00b0019a3bd7dc77mr228403pzj.15.1705688673382; Fri, 19 Jan 2024 10:24:33 -0800 (PST) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:22:57.5266 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7ecd1568-35a0-4511-8706-08dc191ba964 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5368 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544206353913801 X-GMAIL-MSGID: 1788544206353913801 ABMC feature details are reported via CPUID Fn8000_0020_EBX_x5. Bits Description 15:0 MAX_ABMC Maximum Supported Assignable Bandwidth Monitoring Counter ID + 1 Detect the feature details and update /sys/fs/resctrl/info/L3_MON/mon_features. If the system supports Assignable Bandwidth Monitoring Counters (ABMC), the output will have additional text. $ cat /sys/fs/resctrl/info/L3_MON/mon_features mbm_assign_capable The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: Changed the field name to mbm_assign_capable from abmc_capable. --- Documentation/arch/x86/resctrl.rst | 7 +++++++ arch/x86/kernel/cpu/resctrl/core.c | 17 +++++++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 3 +++ include/linux/resctrl.h | 2 ++ 5 files changed, 32 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index d816ded93c22..ecc6c65bdaca 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -197,6 +197,13 @@ with the following files: mbm_local_bytes mbm_local_bytes_config + If the system supports Assignable Bandwidth Monitoring + Counters (ABMC), the output will have additional text. + Example:: + + # cat /sys/fs/resctrl/info/L3_MON/mon_features + mbm_assign_capable + "mbm_total_bytes_config", "mbm_local_bytes_config": Read/write files containing the configuration for the mbm_total_bytes and mbm_local_bytes events, respectively, when the Bandwidth diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index 4efe2d6a9eb7..f40ee271a5c7 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -303,6 +303,17 @@ static void rdt_get_cdp_l2_config(void) rdt_get_cdp_config(RDT_RESOURCE_L2); } +static void rdt_get_abmc_cfg(struct rdt_resource *r) +{ + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + u32 eax, ebx, ecx, edx; + + r->mbm_assign_capable = true; + /* Query CPUID_Fn80000020_EBX_x05 for number of ABMC counters */ + cpuid_count(0x80000020, 5, &eax, &ebx, &ecx, &edx); + hw_res->mbm_assignable_counters = (ebx & 0xFFFF) + 1; +} + static void mba_wrmsr_amd(struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r) { @@ -815,6 +826,12 @@ static __init bool get_rdt_alloc_resources(void) if (get_slow_mem_config()) ret = true; + if (rdt_cpu_has(X86_FEATURE_ABMC)) { + r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + rdt_get_abmc_cfg(r); + ret = true; + } + return ret; } diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index a4f1aa15f0a2..01eb0522b42b 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -391,6 +391,8 @@ struct rdt_parse_data { * resctrl_arch_get_num_closid() to avoid confusion * with struct resctrl_schema's property of the same name, * which has been corrected for features like CDP. + * @mbm_assignable_counters: + * Maximum number of assignable ABMC counters * @msr_base: Base MSR address for CBMs * @msr_update: Function pointer to update QOS MSRs * @mon_scale: cqm counter * mon_scale = occupancy in bytes @@ -404,6 +406,7 @@ struct rdt_parse_data { struct rdt_hw_resource { struct rdt_resource r_resctrl; u32 num_closid; + u32 mbm_assignable_counters; unsigned int msr_base; void (*msr_update) (struct rdt_domain *d, struct msr_param *m, struct rdt_resource *r); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 69a1de92384a..9b82ba977d98 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1077,6 +1077,9 @@ static int rdt_mon_features_show(struct kernfs_open_file *of, seq_printf(seq, "%s_config\n", mevt->name); } + if (r->mbm_assign_capable) + seq_printf(seq, "mbm_assign_capable\n"); + return 0; } diff --git a/include/linux/resctrl.h b/include/linux/resctrl.h index 66942d7fba7f..1751a7b0a369 100644 --- a/include/linux/resctrl.h +++ b/include/linux/resctrl.h @@ -162,6 +162,7 @@ struct resctrl_schema; * @evt_list: List of monitoring events * @fflags: flags to choose base and info files * @cdp_capable: Is the CDP feature available on this resource + * @assign_capable: Does system capable of supporting monitor assignment? */ struct rdt_resource { int rid; @@ -182,6 +183,7 @@ struct rdt_resource { struct list_head evt_list; unsigned long fflags; bool cdp_capable; + bool mbm_assign_capable; }; /** From patchwork Fri Jan 19 18:22:07 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189638 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193594dyb; Fri, 19 Jan 2024 10:24:08 -0800 (PST) X-Google-Smtp-Source: AGHT+IEioNNjCVeDs2L26gLZo/YAmldf97420ktE7vmYNOGzHUP1MB6PtwQ+55jR5r4PtaIrmbQM X-Received: by 2002:a19:674e:0:b0:50e:b255:3ef with SMTP id e14-20020a19674e000000b0050eb25503efmr46999lfj.112.1705688648075; Fri, 19 Jan 2024 10:24:08 -0800 (PST) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CE2.mail.protection.outlook.com (10.167.242.10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Fri, 19 Jan 2024 18:23:04 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 12:23:03 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 05/17] x86/resctrl: Introduce resctrl_file_fflags_init Date: Fri, 19 Jan 2024 12:22:07 -0600 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE2:EE_|BN9PR12MB5052:EE_ X-MS-Office365-Filtering-Correlation-Id: ff8b4bf7-558d-4a93-dae8-08dc191badc9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:04.9171 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ff8b4bf7-558d-4a93-dae8-08dc191badc9 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5052 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544179804889248 X-GMAIL-MSGID: 1788544179804889248 Consolidate multiple fflags initialization into one function. Remove thread_throttle_mode_init, mbm_config_rftype_init and consolidate them into resctrl_file_fflags_init. Signed-off-by: Babu Moger --- v2: New patch. New function to consolidate fflags initialization --- arch/x86/kernel/cpu/resctrl/core.c | 4 +++- arch/x86/kernel/cpu/resctrl/internal.h | 4 ++-- arch/x86/kernel/cpu/resctrl/monitor.c | 6 ++++-- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 16 +++------------- 4 files changed, 12 insertions(+), 18 deletions(-) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index f40ee271a5c7..a38609c82b9e 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -221,7 +221,9 @@ static bool __get_mem_config_intel(struct rdt_resource *r) r->membw.throttle_mode = THREAD_THROTTLE_PER_THREAD; else r->membw.throttle_mode = THREAD_THROTTLE_MAX; - thread_throttle_mode_init(); + + resctrl_file_fflags_init("thread_throttle_mode", + RFTYPE_CTRL_INFO | RFTYPE_RES_MB); r->alloc_capable = true; diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 01eb0522b42b..52ba2fc5c6c4 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -565,8 +565,8 @@ void cqm_handle_limbo(struct work_struct *work); bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d); void __check_limbo(struct rdt_domain *d, bool force_free); void rdt_domain_reconfigure_cdp(struct rdt_resource *r); -void __init thread_throttle_mode_init(void); -void __init mbm_config_rftype_init(const char *config); +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags); void rdt_staged_configs_clear(void); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index f136ac046851..a6c336b6de61 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -815,11 +815,13 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) if (rdt_cpu_has(X86_FEATURE_BMEC)) { if (rdt_cpu_has(X86_FEATURE_CQM_MBM_TOTAL)) { mbm_total_event.configurable = true; - mbm_config_rftype_init("mbm_total_bytes_config"); + resctrl_file_fflags_init("mbm_total_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } if (rdt_cpu_has(X86_FEATURE_CQM_MBM_LOCAL)) { mbm_local_event.configurable = true; - mbm_config_rftype_init("mbm_local_bytes_config"); + resctrl_file_fflags_init("mbm_local_bytes_config", + RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } } diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 9b82ba977d98..3e233251e7ed 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1980,24 +1980,14 @@ static struct rftype *rdtgroup_get_rftype_by_name(const char *name) return NULL; } -void __init thread_throttle_mode_init(void) -{ - struct rftype *rft; - - rft = rdtgroup_get_rftype_by_name("thread_throttle_mode"); - if (!rft) - return; - - rft->fflags = RFTYPE_CTRL_INFO | RFTYPE_RES_MB; -} - -void __init mbm_config_rftype_init(const char *config) +void __init resctrl_file_fflags_init(const char *config, + unsigned long fflags) { struct rftype *rft; rft = rdtgroup_get_rftype_by_name(config); if (rft) - rft->fflags = RFTYPE_MON_INFO | RFTYPE_RES_CACHE; + rft->fflags = fflags; } /** From patchwork Fri Jan 19 18:22:08 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189639 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193704dyb; Fri, 19 Jan 2024 10:24:23 -0800 (PST) X-Google-Smtp-Source: AGHT+IEifYjbnXgKEalBYfp4EouZhi8WgoXhs0Bmp/qggyUe/sAjB0kS0UoDrikA6c65V/v/sKGD X-Received: by 2002:a05:6a20:f81:b0:19a:112e:89dc with SMTP id ga1-20020a056a200f8100b0019a112e89dcmr231222pzb.62.1705688663156; Fri, 19 Jan 2024 10:24:23 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:12.7373 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 62c366eb-7e96-4b50-1c96-08dc191bb273 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB6882 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039124573091647 X-GMAIL-MSGID: 1788544195781351886 The ABMC feature provides an option to the user to pin (or assign) the RMID to the hardware counter and monitor the bandwidth for a longer duration. There are only a limited number of hardware counters. Provide the interface to display the number of ABMC counters supported. Signed-off-by: Babu Moger --- v2: Changed the field name to mbm_assignable_counters from abmc_counters. --- Documentation/arch/x86/resctrl.rst | 4 ++++ arch/x86/kernel/cpu/resctrl/monitor.c | 4 ++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 17 +++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index ecc6c65bdaca..73eeb50fd0b5 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -264,6 +264,10 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15 +"mbm_assignable_counters": + Available when ABMC feature is supported. The number of assignable bandwidth + monitoring counters available. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index a6c336b6de61..fa492ea820f0 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -823,6 +823,10 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) resctrl_file_fflags_init("mbm_local_bytes_config", RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } + + if (rdt_cpu_has(X86_FEATURE_ABMC)) + resctrl_file_fflags_init("mbm_assignable_counters", + RFTYPE_MON_INFO); } l3_mon_evt_init(r); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 3e233251e7ed..53be5cd1c28e 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -811,6 +811,17 @@ static int rdtgroup_rmid_show(struct kernfs_open_file *of, return ret; } +static int rdtgroup_mbm_assignable_counters_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r = of->kn->parent->priv; + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + + seq_printf(s, "%d\n", hw_res->mbm_assignable_counters); + + return 0; +} + #ifdef CONFIG_PROC_CPU_RESCTRL /* @@ -1861,6 +1872,12 @@ static struct rftype res_common_files[] = { .seq_show = mbm_local_bytes_config_show, .write = mbm_local_bytes_config_write, }, + { + .name = "mbm_assignable_counters", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdtgroup_mbm_assignable_counters_show, + }, { .name = "cpus", .mode = 0644, From patchwork Fri Jan 19 18:22:09 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189641 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1193866dyb; Fri, 19 Jan 2024 10:24:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IHuD4wNWDdzB0pQf6WbPvqmffM6KERoVBKDcJmXfN0ltajOWwzwWto2FBrnP5pJKwpMKCUW X-Received: by 2002:a17:90a:a58c:b0:290:4acd:2745 with SMTP id b12-20020a17090aa58c00b002904acd2745mr165357pjq.33.1705688679778; Fri, 19 Jan 2024 10:24:39 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:20.9796 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0909e2ca-d408-45eb-2a6d-08dc191bb75f X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5181 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039128961071050 X-GMAIL-MSGID: 1788544212889033621 Add the functionality to enable/disable ABMC feature. By default, the ABMC is disabled. ABMC is enabled by setting enabled bit(0) in MSR L3_QOS_EXT_CFG. When the state of ABMC is changed, it must be changed to the updated value on all logical processors in the QOS Domain. The ABMC feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: Few text changes in commit message. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 12 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 70 +++++++++++++++++++++++++- 3 files changed, 82 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index f1bd7b91b3c6..ac0ce88a5978 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1126,6 +1126,7 @@ #define MSR_IA32_MBA_BW_BASE 0xc0000200 #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 +#define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 52ba2fc5c6c4..3467221f2af5 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -54,6 +54,9 @@ /* Max event bits supported */ #define MAX_EVT_CONFIG_BITS GENMASK(6, 0) +/* ABMC ENABLE */ +#define ABMC_ENABLE BIT(0) + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -398,6 +401,7 @@ struct rdt_parse_data { * @mon_scale: cqm counter * mon_scale = occupancy in bytes * @mbm_width: Monitor width, to detect and correct for overflow. * @cdp_enabled: CDP state of this resource + * @abmc_enabled: ABMC feature is enabled * * Members of this structure are either private to the architecture * e.g. mbm_width, or accessed via helpers that provide abstraction. e.g. @@ -413,6 +417,7 @@ struct rdt_hw_resource { unsigned int mon_scale; unsigned int mbm_width; bool cdp_enabled; + bool abmc_enabled; }; static inline struct rdt_hw_resource *resctrl_to_arch_res(struct rdt_resource *r) @@ -458,6 +463,13 @@ static inline bool resctrl_arch_get_cdp_enabled(enum resctrl_res_level l) int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable); +static inline bool resctrl_arch_get_abmc_enabled(enum resctrl_res_level l) +{ + return rdt_resources_all[l].abmc_enabled; +} + +int resctrl_arch_set_abmc_enabled(enum resctrl_res_level l, bool enable); + /* * To return the common struct rdt_resource, which is contained in struct * rdt_hw_resource, walk the resctrl member of struct rdt_hw_resource. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 53be5cd1c28e..2fb26227cbec 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -2372,6 +2372,74 @@ int resctrl_arch_set_cdp_enabled(enum resctrl_res_level l, bool enable) return 0; } +static void resctrl_abmc_msrwrite(void *arg) +{ + bool *enable = arg; + u64 msrval; + + rdmsrl(MSR_IA32_L3_QOS_EXT_CFG, msrval); + + if (*enable) + msrval |= ABMC_ENABLE; + else + msrval &= ~ABMC_ENABLE; + + wrmsrl(MSR_IA32_L3_QOS_EXT_CFG, msrval); +} + +static int resctrl_abmc_setup(enum resctrl_res_level l, bool enable) +{ + struct rdt_resource *r = &rdt_resources_all[l].r_resctrl; + struct rdt_domain *d; + + /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ + list_for_each_entry(d, &r->domains, list) { + on_each_cpu_mask(&d->cpu_mask, resctrl_abmc_msrwrite, &enable, 1); + resctrl_arch_reset_rmid_all(r, d); + } + + return 0; +} + +static int resctrl_abmc_enable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res = &rdt_resources_all[l]; + int ret = 0; + + if (!hw_res->abmc_enabled) { + ret = resctrl_abmc_setup(l, true); + if (!ret) + hw_res->abmc_enabled = true; + } + + return ret; +} + +static void resctrl_abmc_disable(enum resctrl_res_level l) +{ + struct rdt_hw_resource *hw_res = &rdt_resources_all[l]; + + if (hw_res->abmc_enabled) { + resctrl_abmc_setup(l, false); + hw_res->abmc_enabled = false; + } +} + +int resctrl_arch_set_abmc_enabled(enum resctrl_res_level l, bool enable) +{ + struct rdt_hw_resource *hw_res = &rdt_resources_all[l]; + + if (!hw_res->r_resctrl.mbm_assign_capable) + return -EINVAL; + + if (enable) + return resctrl_abmc_enable(l); + + resctrl_abmc_disable(l); + + return 0; +} + /* * We don't allow rdtgroup directories to be created anywhere * except the root directory. Thus when looking for the rdtgroup @@ -2456,7 +2524,7 @@ static void rdt_disable_ctx(void) resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L3, false); resctrl_arch_set_cdp_enabled(RDT_RESOURCE_L2, false); set_mba_sc(false); - + resctrl_arch_set_abmc_enabled(RDT_RESOURCE_L3, false); resctrl_debug = false; } From patchwork Fri Jan 19 18:22:10 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189642 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1194028dyb; Fri, 19 Jan 2024 10:24:56 -0800 (PST) X-Google-Smtp-Source: AGHT+IEdchnWzo54abw+rM+TH4ZSm7WDjkCGbGkchV2T+2ffPhmruG9eXCs28G1m6NCdS4eWtK5d X-Received: by 2002:a05:6358:724f:b0:172:ae52:ac40 with SMTP id i15-20020a056358724f00b00172ae52ac40mr187018rwa.38.1705688696482; Fri, 19 Jan 2024 10:24:56 -0800 (PST) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CE3.mail.protection.outlook.com (10.167.242.11) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Fri, 19 Jan 2024 18:23:28 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 12:23:26 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 08/17] x86/resctrl: Introduce the interface to display ABMC state Date: Fri, 19 Jan 2024 12:22:10 -0600 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CE3:EE_|DS7PR12MB6238:EE_ X-MS-Office365-Filtering-Correlation-Id: 3d8d81d7-4fc2-45bf-3f51-08dc191bbb91 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:28.0343 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3d8d81d7-4fc2-45bf-3f51-08dc191bbb91 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6238 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544230882113038 X-GMAIL-MSGID: 1788544230882113038 The ABMC feature provides an option to the user to assign an RMID to the hardware counter and monitor the bandwidth for a longer duration. System can be in only one mode at a time (Legacy Monitor mode or ABMC mode). By default, ABMC mode is disabled. Provide an interface to display the monitor mode on the system. $cat /sys/fs/resctrl/info/L3_MON/mbm_assign_enable 0 Signed-off-by: Babu Moger --- v2: This is new patch to display ABMC mode. --- Documentation/arch/x86/resctrl.rst | 6 ++++++ arch/x86/kernel/cpu/resctrl/monitor.c | 5 ++++- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 17 +++++++++++++++++ 3 files changed, 27 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index 73eeb50fd0b5..f94a4d314690 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -268,6 +268,12 @@ with the following files: Available when ABMC feature is supported. The number of assignable bandwidth monitoring counters available. +"mbm_assign_enable": + Available when ABMC feature is supported. System supports RMID counter + assignment for monitoring. Feature provides an option to assign the RMID + to the hardware counter and monitor the bandwidth for a longer duration. + The assigned RMID will be active until the user unassigns it. + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index fa492ea820f0..a45084e30738 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -824,9 +824,12 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) RFTYPE_MON_INFO | RFTYPE_RES_CACHE); } - if (rdt_cpu_has(X86_FEATURE_ABMC)) + if (rdt_cpu_has(X86_FEATURE_ABMC)) { resctrl_file_fflags_init("mbm_assignable_counters", RFTYPE_MON_INFO); + resctrl_file_fflags_init("mbm_assign_enable", + RFTYPE_MON_INFO); + } } l3_mon_evt_init(r); diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 2fb26227cbec..4f160dbf6376 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -822,6 +822,17 @@ static int rdtgroup_mbm_assignable_counters_show(struct kernfs_open_file *of, return 0; } +static int rdtgroup_mbm_assign_enable_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r = of->kn->parent->priv; + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + + seq_printf(s, "%d\n", hw_res->abmc_enabled); + + return 0; +} + #ifdef CONFIG_PROC_CPU_RESCTRL /* @@ -1878,6 +1889,12 @@ static struct rftype res_common_files[] = { .kf_ops = &rdtgroup_kf_single_ops, .seq_show = rdtgroup_mbm_assignable_counters_show, }, + { + .name = "mbm_assign_enable", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdtgroup_mbm_assign_enable_show, + }, { .name = "cpus", .mode = 0644, From patchwork Fri Jan 19 18:22:11 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189644 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1194495dyb; Fri, 19 Jan 2024 10:25:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IEd1jRc+27u1w5s6NAHDn3nkYb4yHiPD5m1Jqk1igVlDxrZAX4ds6n5aK8aj29MtGDpbQyC X-Received: by 2002:a05:6871:148:b0:210:817c:4af4 with SMTP id z8-20020a056871014800b00210817c4af4mr213932oab.72.1705688746419; Fri, 19 Jan 2024 10:25:46 -0800 (PST) Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:35.7296 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: fccb366e-5e15-49f9-d6da-08dc191bc029 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7870 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544283023121742 X-GMAIL-MSGID: 1788544283023121742 Introduce rdtgroup_assign_enable_write to enable ABMC mode. Users can enable the feature by the following command. $echo 1 > /sys/fs/resctrl/info/L3_MON/mbm_assign_enable Signed-off-by: Babu Moger --- v2: This is new patch to enable/disable ABMC without mounting the filesystem. --- Documentation/arch/x86/resctrl.rst | 6 +++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 34 +++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index f94a4d314690..f09239cb93e8 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -273,6 +273,12 @@ with the following files: assignment for monitoring. Feature provides an option to assign the RMID to the hardware counter and monitor the bandwidth for a longer duration. The assigned RMID will be active until the user unassigns it. + By default, the feature is disabled. Feature can be enabled by writing 1. + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_enable + 0 + # echo 1 > /sys/fs/resctrl/info/L3_MON/mbm_assign_enable "max_threshold_occupancy": Read/write file provides the largest value (in diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 4f160dbf6376..9c8db9562c91 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -833,6 +833,37 @@ static int rdtgroup_mbm_assign_enable_show(struct kernfs_open_file *of, return 0; } +static ssize_t rdtgroup_mbm_assign_enable_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, + loff_t off) +{ + struct rdt_resource *r = of->kn->parent->priv; + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + struct rdtgroup *rdtgrp; + unsigned int enable; + int ret; + + if (!r->mbm_assign_capable) + return -EINVAL; + + ret = kstrtouint(buf, 0, &enable); + if (ret) + return ret; + + rdtgrp = rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + rdtgroup_kn_unlock(of->kn); + return -EINVAL; + } + + if(hw_res->abmc_enabled != enable) + ret = resctrl_arch_set_abmc_enabled(r->rid, enable); + + rdtgroup_kn_unlock(of->kn); + + return ret ?: nbytes; +} + #ifdef CONFIG_PROC_CPU_RESCTRL /* @@ -1891,9 +1922,10 @@ static struct rftype res_common_files[] = { }, { .name = "mbm_assign_enable", - .mode = 0444, + .mode = 0644, .kf_ops = &rdtgroup_kf_single_ops, .seq_show = rdtgroup_mbm_assign_enable_show, + .write = rdtgroup_mbm_assign_enable_write, }, { .name = "cpus", From patchwork Fri Jan 19 18:22:12 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189650 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1196049dyb; Fri, 19 Jan 2024 10:28:40 -0800 (PST) X-Google-Smtp-Source: AGHT+IGMHVpdwyBrblUa9Mg79VAHnvvtSYwausolLBY7+osZJ+9e1ezdSAOodNLYNlSq/d59NkPC X-Received: by 2002:a17:902:82cb:b0:1d7:1c53:9328 with SMTP id u11-20020a17090282cb00b001d71c539328mr283712plz.50.1705688920505; Fri, 19 Jan 2024 10:28:40 -0800 (PST) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CDF.mail.protection.outlook.com (10.167.242.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Fri, 19 Jan 2024 18:23:43 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 12:23:41 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 10/17] x86/resctrl: Add interface to display monitor state of the group Date: Fri, 19 Jan 2024 12:22:12 -0600 Message-ID: X-Mailer: git-send-email 2.34.1 In-Reply-To: References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDF:EE_|CH3PR12MB8850:EE_ X-MS-Office365-Filtering-Correlation-Id: 50250ef5-bdcc-4a0a-cc4e-08dc191bc4a6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:43.2594 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 50250ef5-bdcc-4a0a-cc4e-08dc191bc4a6 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB8850 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039148882832601 X-GMAIL-MSGID: 1788544465199051298 The ABMC feature provides an option to the user to assign an RMID to the hardware counter and monitor the bandwidth for the longer duration. The assigned RMID will be active until user unassigns the RMID. Add a new field monitor_state in resctrl group interface to display the assignment state of the group. This field is available when ABMC feature is supported on the system. By default the monitor_state is initialized to unassigned state when ABMC is enabled. $cat /sys/fs/resctrl/monitor_state total=unassign;local=unassign Signed-off-by: Babu Moger --- v2: Added check to display "Unsupported" when user tries to access monitor state when ABMC is not enabled. --- Documentation/arch/x86/resctrl.rst | 20 ++++++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 8 +++++ arch/x86/kernel/cpu/resctrl/monitor.c | 2 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 45 ++++++++++++++++++++++++++ 4 files changed, 75 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index f09239cb93e8..4f89d5d1b61f 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -400,6 +400,26 @@ When monitoring is enabled all MON groups will also contain: the sum for all tasks in the CTRL_MON group and all tasks in MON groups. Please see example section for more details on usage. +"monitor_state": + Available when ABMC feature is supported. ABMC feature provides an + option to the user to assign an RMID to hardware counter and + monitor the bandwidth for the longer duration. The RMID will + be active until user unassigns it manually. Each group will have + two events that are assignable. By default, the events are + unassigned. Index 0 holds the monitor_state for MBM total bytes. + Index 1 holds the monitor_state for MBM local bytes. + + Example:: + + # cat /sys/fs/resctrl/monitor_state + total=unassign;local=unassign + + When the events are assigned, the output will look like below. + Example:: + + # cat /sys/fs/resctrl/monitor_state + total=assign;local=assign + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 3467221f2af5..865101c5e1c2 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -57,6 +57,12 @@ /* ABMC ENABLE */ #define ABMC_ENABLE BIT(0) +/* + * monitor group's state when ABMC is enabled + */ +#define TOTAL_ASSIGN BIT(0) +#define LOCAL_ASSIGN BIT(1) + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -163,12 +169,14 @@ enum rdtgrp_mode { * @parent: parent rdtgrp * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup + * @monitor_state: Assignment state of the group */ struct mongroup { struct kernfs_node *mon_data_kn; struct rdtgroup *parent; struct list_head crdtgrp_list; u32 rmid; + u32 monitor_state; }; /** diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index a45084e30738..de43be2252cc 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -829,6 +829,8 @@ int __init rdt_get_mon_l3_config(struct rdt_resource *r) RFTYPE_MON_INFO); resctrl_file_fflags_init("mbm_assign_enable", RFTYPE_MON_INFO); + resctrl_file_fflags_init("monitor_state", + RFTYPE_MON_BASE); } } diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 9c8db9562c91..7cae6ac13954 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -779,6 +779,36 @@ static int rdtgroup_tasks_show(struct kernfs_open_file *of, return ret; } +static int rdtgroup_monitor_state_show(struct kernfs_open_file *of, + struct seq_file *s, void *v) +{ + struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + struct rdtgroup *rdtgrp; + int ret = 0; + + if (!hw_res->abmc_enabled) { + rdt_last_cmd_puts("Assignable Bandwidth Monitoring is not enabled\n"); + seq_printf(s, "Unsuppoted\n"); + return ret; + } + + rdt_last_cmd_clear(); + + rdtgrp = rdtgroup_kn_lock_live(of->kn); + if (rdtgrp) + seq_printf(s, "total=%s;local=%s\n", + rdtgrp->mon.monitor_state & TOTAL_ASSIGN ? + "assign" : "unassign", + rdtgrp->mon.monitor_state & LOCAL_ASSIGN ? + "assign" : "unassign"); + else + ret = -EINVAL; + rdtgroup_kn_unlock(of->kn); + + return ret; +} + static int rdtgroup_closid_show(struct kernfs_open_file *of, struct seq_file *s, void *v) { @@ -1944,6 +1974,12 @@ static struct rftype res_common_files[] = { .flags = RFTYPE_FLAGS_CPUS_LIST, .fflags = RFTYPE_BASE, }, + { + .name = "monitor_state", + .mode = 0444, + .kf_ops = &rdtgroup_kf_single_ops, + .seq_show = rdtgroup_monitor_state_show, + }, { .name = "tasks", .mode = 0644, @@ -2439,6 +2475,7 @@ static void resctrl_abmc_msrwrite(void *arg) static int resctrl_abmc_setup(enum resctrl_res_level l, bool enable) { struct rdt_resource *r = &rdt_resources_all[l].r_resctrl; + struct rdtgroup *prgrp, *crgrp; struct rdt_domain *d; /* Update QOS_CFG MSR on all the CPUs in cpu_mask */ @@ -2447,6 +2484,14 @@ static int resctrl_abmc_setup(enum resctrl_res_level l, bool enable) resctrl_arch_reset_rmid_all(r, d); } + /* Reset monitor state for all the monitor groups */ + list_for_each_entry(prgrp, &rdt_all_groups, rdtgroup_list) { + memset(&prgrp->mon.monitor_state, 0, sizeof(prgrp->mon.monitor_state)); + + list_for_each_entry(crgrp, &prgrp->mon.crdtgrp_list, mon.crdtgrp_list) + memset(&crgrp->mon.monitor_state, 0, sizeof(crgrp->mon.monitor_state)); + } + return 0; } From patchwork Fri Jan 19 18:22:13 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189643 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1194489dyb; Fri, 19 Jan 2024 10:25:46 -0800 (PST) X-Google-Smtp-Source: AGHT+IFhuEsXkbcjhQq5PNVNNRvWPsM8fxRCVT3viTeLrqq4HV5z0BRiPw93BGm5sw/LcVo/g/Mz X-Received: by 2002:a05:6a20:89a6:b0:19a:30d9:b0b4 with SMTP id h38-20020a056a2089a600b0019a30d9b0b4mr227728pzg.32.1705688745785; Fri, 19 Jan 2024 10:25:45 -0800 (PST) Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by SJ1PEPF00001CDC.mail.protection.outlook.com (10.167.242.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.7202.16 via Frontend Transport; Fri, 19 Jan 2024 18:23:50 +0000 Received: from bmoger-ubuntu.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.34; Fri, 19 Jan 2024 12:23:49 -0600 From: Babu Moger To: , , , , , , CC: , , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v2 11/17] x86/resctrl: Report Unsupported when MBM events are read Date: Fri, 19 Jan 2024 12:22:13 -0600 Message-ID: <6a265cb586e4707a97b92641462007d5bda37cb9.1705688539.git.babu.moger@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: References: <20231201005720.235639-1-babu.moger@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ClientProxiedBy: SATLEXMB04.amd.com (10.181.40.145) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF00001CDC:EE_|BN9PR12MB5381:EE_ X-MS-Office365-Filtering-Correlation-Id: f24c4501-7aee-4e02-7725-08dc191bc90a X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:50.6391 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f24c4501-7aee-4e02-7725-08dc191bc90a X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDC.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN9PR12MB5381 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544282046220151 X-GMAIL-MSGID: 1788544282046220151 Hardware reports "Unavailable" when a user tries to read the event when ABMC is enabled and event is not assigned. "Unavailable" is reported in other error cases also. To differentiate these cases, skip reading the event and report "Unsupported" that way users can take corrective action. Signed-off-by: Babu Moger --- v2: New patch based on feedback. --- arch/x86/kernel/cpu/resctrl/ctrlmondata.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c index beccb0e87ba7..cc4c41eede25 100644 --- a/arch/x86/kernel/cpu/resctrl/ctrlmondata.c +++ b/arch/x86/kernel/cpu/resctrl/ctrlmondata.c @@ -542,12 +542,14 @@ void mon_event_read(struct rmid_read *rr, struct rdt_resource *r, int rdtgroup_mondata_show(struct seq_file *m, void *arg) { struct kernfs_open_file *of = m->private; + struct rdt_hw_resource *hw_res; u32 resid, evtid, domid; struct rdtgroup *rdtgrp; struct rdt_resource *r; union mon_data_bits md; struct rdt_domain *d; struct rmid_read rr; + int mon_state; int ret = 0; rdtgrp = rdtgroup_kn_lock_live(of->kn); @@ -568,6 +570,19 @@ int rdtgroup_mondata_show(struct seq_file *m, void *arg) goto out; } + hw_res = resctrl_to_arch_res(r); + if (hw_res->abmc_enabled && evtid != QOS_L3_OCCUP_EVENT_ID) { + if (evtid == QOS_L3_MBM_TOTAL_EVENT_ID) + mon_state = TOTAL_ASSIGN; + else + mon_state = LOCAL_ASSIGN; + + if (!(rdtgrp->mon.monitor_state & mon_state)) { + seq_puts(m, "Unsupported\n"); + goto out; + } + } + mon_event_read(&rr, r, d, rdtgrp, evtid, false); if (rr.err == -EIO) From patchwork Fri Jan 19 18:22:14 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189651 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1196503dyb; Fri, 19 Jan 2024 10:29:33 -0800 (PST) X-Google-Smtp-Source: AGHT+IHIo4omJ6ZG5Is6Dn/Gxoprjr1CuQ8ZHemf1/gD9nBU8E/w9u/JNTD5h3iU0fc2dg76wX80 X-Received: by 2002:a17:903:22cf:b0:1d7:199:cfb9 with SMTP id y15-20020a17090322cf00b001d70199cfb9mr361957plg.108.1705688973248; Fri, 19 Jan 2024 10:29:33 -0800 (PST) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:23:58.7137 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 8925fae3-573a-4faf-ef56-08dc191bcddc X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDD.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7102 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544520556027539 X-GMAIL-MSGID: 1788544520556027539 AMD Hardware provides a set of ABMC counters when the feature is supported. These hardware counters are used for assigning the RMIDs to the group. Introduce the bitmap assignable_counter_free_map to allocate and free counters. Signed-off-by: Babu Moger --- v2: Changed the bitmap name to assignable_counter_free_map from abmc_counter_free_map. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 21 ++++++++++++++++++++- 1 file changed, 20 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 7cae6ac13954..19b0ebf4f435 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -164,6 +164,22 @@ static bool closid_allocated(unsigned int closid) return (closid_free_map & (1 << closid)) == 0; } +static u64 assignable_counter_free_map; +static u32 assignable_counter_free_map_len; + +static void assignable_counters_init(void) +{ + struct rdt_hw_resource *hw_res = &rdt_resources_all[RDT_RESOURCE_L3]; + + if (hw_res->mbm_assignable_counters > 64) { + hw_res->mbm_assignable_counters = 64; + WARN(1, "Cannot support more than 64 Assignable counters\n"); + } + + assignable_counter_free_map = BIT_MASK(hw_res->mbm_assignable_counters) - 1; + assignable_counter_free_map_len = hw_res->mbm_assignable_counters; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -2777,6 +2793,10 @@ static int rdt_get_tree(struct fs_context *fc) closid_init(); + r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + if (r->mbm_assign_capable) + assignable_counters_init(); + if (rdt_mon_capable) flags |= RFTYPE_MON; @@ -2821,7 +2841,6 @@ static int rdt_get_tree(struct fs_context *fc) static_branch_enable_cpuslocked(&rdt_enable_key); if (is_mbm_enabled()) { - r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; list_for_each_entry(dom, &r->domains, list) mbm_setup_overflow_handler(dom, MBM_OVERFLOW_INTERVAL); } From patchwork Fri Jan 19 18:22:15 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189645 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1194898dyb; Fri, 19 Jan 2024 10:26:26 -0800 (PST) X-Google-Smtp-Source: AGHT+IHYoID8xDrlE11TyQfbreoZbH/bZ9q4VgTQqhBvqzmQuqK8i4GHHCEG+V7jqX1aOCuLXbBG X-Received: by 2002:a05:600c:1911:b0:40d:7d62:80ab with SMTP id j17-20020a05600c191100b0040d7d6280abmr97720wmq.117.1705688786275; Fri, 19 Jan 2024 10:26:26 -0800 (PST) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:06.2874 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b6b2b605-7c44-4b2d-9776-08dc191bd260 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE0.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6556 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039146946894720 X-GMAIL-MSGID: 1788544324725512167 ABMC (Bandwidth Monitoring Event Configuration) counters can be configured by writing to L3_QOS_ABMC_CFG MSR. When ABMC is enabled, the user can configure a counter by writing to L3_QOS_ABMC_CFG setting the CfgEn field while specifying the Bandwidth Source, Bandwidth Types, and Counter Identifier. Add the MSR definition and individual field definitions. MSR L3_QOS_ABMC_CFG (C000_03FDh) definitions. ========================================================================== Bits Mnemonic Description Access Type Reset Value ========================================================================== 63 CfgEn Configuration Enable R/W 0 62 CtrEn Counter Enable R/W 0 61:53 – Reserved MBZ 0 52:48 CtrID Counter Identifier R/W 0 47 IsCOS BwSrc field is a COS R/W 0 (not an RMID) R/W 0 46:44 – Reserved MBZ 0 43:32 BwSrc Bandwidth Source R/W 0 (RMID or COS) 31:0 BwType Bandwidth types to R/W 0 track for this counter ========================================================================== The feature details are documentd in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: No changes. --- arch/x86/include/asm/msr-index.h | 1 + arch/x86/kernel/cpu/resctrl/internal.h | 23 +++++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index ac0ce88a5978..148c2b8a2264 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -1127,6 +1127,7 @@ #define MSR_IA32_SMBA_BW_BASE 0xc0000280 #define MSR_IA32_EVT_CFG_BASE 0xc0000400 #define MSR_IA32_L3_QOS_EXT_CFG 0xc00003ff +#define MSR_IA32_L3_QOS_ABMC_CFG 0xc00003fd /* MSR_IA32_VMX_MISC bits */ #define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14) diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 865101c5e1c2..130854dc8b7f 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -63,6 +63,9 @@ #define TOTAL_ASSIGN BIT(0) #define LOCAL_ASSIGN BIT(1) +/* Maximum assignable counters per resctrl group */ +#define ABMC_MAX_CTR_PER_GROUP 2 + struct rdt_fs_context { struct kernfs_fs_context kfc; bool enable_cdpl2; @@ -170,6 +173,7 @@ enum rdtgrp_mode { * @crdtgrp_list: child rdtgroup node list * @rmid: rmid for this rdtgroup * @monitor_state: Assignment state of the group + * @abmc_ctr_id: ABMC counterids assigned to this group */ struct mongroup { struct kernfs_node *mon_data_kn; @@ -177,6 +181,7 @@ struct mongroup { struct list_head crdtgrp_list; u32 rmid; u32 monitor_state; + u32 abmc_ctr_id[ABMC_MAX_CTR_PER_GROUP]; }; /** @@ -532,6 +537,24 @@ union cpuid_0x10_x_edx { unsigned int full; }; +/* + * L3_QOS_ABMC_CFG MSR details. ABMC counters can be configured + * by writing to L3_QOS_ABMC_CFG. + */ +union l3_qos_abmc_cfg { + struct { + unsigned long bw_type :32, + bw_src :12, + rsvrd1 : 3, + is_cos : 1, + ctr_id : 5, + rsvrd : 9, + ctr_en : 1, + cfg_en : 1; + } split; + unsigned long full; +}; + void rdt_last_cmd_clear(void); void rdt_last_cmd_puts(const char *s); __printf(1, 2) From patchwork Fri Jan 19 18:22:16 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189646 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1194992dyb; Fri, 19 Jan 2024 10:26:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IHKvssklWh+ikzF4KXp/5PiAA747rJ27DEZJ3p3iVG8c07cP8z3NQgqvpi2zst7QkTa0cA+ X-Received: by 2002:a05:6402:18b:b0:55a:80d3:1219 with SMTP id r11-20020a056402018b00b0055a80d31219mr99240edv.30.1705688798116; Fri, 19 Jan 2024 10:26:38 -0800 (PST) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:14.3941 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9084ddee-9ab8-4697-9144-08dc191bd735 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7862 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1784039166004708010 X-GMAIL-MSGID: 1788544336763000636 If the BMEC (Bandwidth Monitoring Event Configuration) feature is supported, the bandwidth events can be configured to track specific events. The event configuration is domain specific. ABMC (Assignable Bandwidth Monitoring Counters) feature needs event configuration information to assign RMID to the hardware counter. Currently, this information is not available. Save the event configuration information in the rdt_hw_domain, so it can be used while for RMID assignment. Signed-off-by: Babu Moger --- v2: No changes. --- arch/x86/kernel/cpu/resctrl/core.c | 2 ++ arch/x86/kernel/cpu/resctrl/internal.h | 3 +++ arch/x86/kernel/cpu/resctrl/monitor.c | 11 +++++++++++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 11 +++++++++++ 4 files changed, 27 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/core.c b/arch/x86/kernel/cpu/resctrl/core.c index a38609c82b9e..e0ba43387afe 100644 --- a/arch/x86/kernel/cpu/resctrl/core.c +++ b/arch/x86/kernel/cpu/resctrl/core.c @@ -558,6 +558,8 @@ static void domain_add_cpu(int cpu, struct rdt_resource *r) return; } + arch_domain_mbm_evt_config(hw_dom); + list_add_tail(&d->list, add_pos); err = resctrl_online_domain(r, d); diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index 130854dc8b7f..e109c0388762 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -349,6 +349,8 @@ struct rdt_hw_domain { u32 *ctrl_val; struct arch_mbm_state *arch_mbm_total; struct arch_mbm_state *arch_mbm_local; + u32 mbm_total_cfg; + u32 mbm_local_cfg; }; static inline struct rdt_hw_domain *resctrl_to_arch_dom(struct rdt_domain *r) @@ -611,5 +613,6 @@ void rdt_domain_reconfigure_cdp(struct rdt_resource *r); void __init resctrl_file_fflags_init(const char *config, unsigned long fflags); void rdt_staged_configs_clear(void); +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/monitor.c b/arch/x86/kernel/cpu/resctrl/monitor.c index de43be2252cc..ec480015980c 100644 --- a/arch/x86/kernel/cpu/resctrl/monitor.c +++ b/arch/x86/kernel/cpu/resctrl/monitor.c @@ -854,3 +854,14 @@ void __init intel_rdt_mbm_apply_quirk(void) mbm_cf_rmidthreshold = mbm_cf_table[cf_index].rmidthreshold; mbm_cf = mbm_cf_table[cf_index].cf; } + +void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom) +{ + if (mbm_total_event.configurable) + hw_dom->mbm_total_cfg = MAX_EVT_CONFIG_BITS; + + if (mbm_local_event.configurable) + hw_dom->mbm_local_cfg = READS_TO_LOCAL_MEM | + NON_TEMP_WRITE_TO_LOCAL_MEM | + READS_TO_LOCAL_S_MEM; +} diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 19b0ebf4f435..df8d2390fc69 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1719,6 +1719,7 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); struct mon_config_info mon_info = {0}; int ret = 0; @@ -1748,6 +1749,16 @@ static int mbm_config_write_domain(struct rdt_resource *r, smp_call_function_any(&d->cpu_mask, mon_event_config_write, &mon_info, 1); + /* + * Update event config value in the domain when user changes it. + */ + if (evtid == QOS_L3_MBM_TOTAL_EVENT_ID) + hw_dom->mbm_total_cfg = val; + else if (evtid == QOS_L3_MBM_LOCAL_EVENT_ID) + hw_dom->mbm_local_cfg = val; + else + goto out; + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:22.9001 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: acf74f6c-f524-4d53-348a-08dc191bdd82 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CDF.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB9069 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544361245988719 X-GMAIL-MSGID: 1788544361245988719 With the support of ABMC (Assignable Bandwidth Monitoring Counters) feature, the user has the option to assign or unassign the RMID to hardware counter and monitor the bandwidth for the longer duration. Provide the interface to assign the counter to the group. The ABMC feature implements a pair of MSRs, L3_QOS_ABMC_CFG (MSR C000_03FDh) and L3_QOS_ABMC_DSC (MSR C000_3FEh). Each logical processor implements a separate copy of these registers. Attempts to read or write these MSRs when ABMC is not enabled will result in a #GP(0) exception. Individual assignable bandwidth counters are configured by writing to L3_QOS_ABMC_CFG MSR and specifying the Counter ID, Bandwidth Source, and Bandwidth Types. Reading L3_QOS_ABMC_DSC returns the configuration of the counter specified by L3_QOS_ABMC_CFG [CtrID]. The feature details are documented in the APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: Minor text changes in commit message. --- Documentation/arch/x86/resctrl.rst | 7 ++ arch/x86/kernel/cpu/resctrl/rdtgroup.c | 160 ++++++++++++++++++++++++- 2 files changed, 166 insertions(+), 1 deletion(-) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index 4f89d5d1b61f..2729c6fe6127 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -420,6 +420,13 @@ When monitoring is enabled all MON groups will also contain: # cat /sys/fs/resctrl/monitor_state total=assign;local=assign + The user needs to pin (or assign) RMID to read the MBM event in + ABMC mode. Each event can be assigned or unassigned separately. + Example:: + + # echo total=assign > /sys/fs/resctrl/monitor_state + # echo total=assign;local=assign > /sys/fs/resctrl/monitor_state + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index df8d2390fc69..3447fc4ff2e9 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -180,6 +180,18 @@ static void assignable_counters_init(void) assignable_counter_free_map_len = hw_res->mbm_assignable_counters; } +static int assignable_counters_alloc(void) +{ + u32 counterid = ffs(assignable_counter_free_map); + + if (counterid == 0) + return -ENOSPC; + counterid--; + assignable_counter_free_map &= ~(1 << counterid); + + return counterid; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1635,6 +1647,151 @@ static inline unsigned int mon_event_config_index_get(u32 evtid) } } +static void rdtgroup_abmc_msrwrite(void *info) +{ + u64 *msrval = info; + + wrmsrl(MSR_IA32_L3_QOS_ABMC_CFG, *msrval); +} + +static void rdtgroup_abmc_domain(struct rdt_domain *d, + struct rdtgroup *rdtgrp, + u32 evtid, int index, bool assign) +{ + struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); + union l3_qos_abmc_cfg abmc_cfg = { 0 }; + struct arch_mbm_state *arch_mbm; + + abmc_cfg.split.cfg_en = 1; + abmc_cfg.split.ctr_en = assign ? 1 : 0; + abmc_cfg.split.ctr_id = rdtgrp->mon.abmc_ctr_id[index]; + abmc_cfg.split.bw_src = rdtgrp->mon.rmid; + + /* + * Read the event configuration from the domain and pass it as + * bw_type. + */ + if (evtid == QOS_L3_MBM_TOTAL_EVENT_ID) { + abmc_cfg.split.bw_type = hw_dom->mbm_total_cfg; + arch_mbm = &hw_dom->arch_mbm_total[rdtgrp->mon.rmid]; + } else { + abmc_cfg.split.bw_type = hw_dom->mbm_local_cfg; + arch_mbm = &hw_dom->arch_mbm_local[rdtgrp->mon.rmid]; + } + + smp_call_function_any(&d->cpu_mask, rdtgroup_abmc_msrwrite, &abmc_cfg, 1); + + /* Reset the internal counters */ + if (arch_mbm) + memset(arch_mbm, 0, sizeof(struct arch_mbm_state)); +} + +static ssize_t rdtgroup_assign_abmc(struct rdtgroup *rdtgrp, + struct rdt_resource *r, + u32 evtid, int mon_state) +{ + int counterid = 0, index; + struct rdt_domain *d; + + if (rdtgrp->mon.monitor_state & mon_state) { + rdt_last_cmd_puts("ABMC counter is assigned already\n"); + return 0; + } + + index = mon_event_config_index_get(evtid); + if (index == INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return -EINVAL; + } + + /* + * Allocate a new counter and update domains + */ + counterid = assignable_counters_alloc(); + if (counterid < 0) { + rdt_last_cmd_puts("Out of ABMC counters\n"); + return -ENOSPC; + } + + rdtgrp->mon.abmc_ctr_id[index] = counterid; + + list_for_each_entry(d, &r->domains, list) + rdtgroup_abmc_domain(d, rdtgrp, evtid, index, 1); + + rdtgrp->mon.monitor_state |= mon_state; + + return 0; +} + +/** + * rdtgroup_monitor_state_write - Interface to assign/unassign an RMID. + * + * Return: 0 for success + */ +static ssize_t rdtgroup_monitor_state_write(struct kernfs_open_file *of, + char *buf, size_t nbytes, loff_t off) +{ + struct rdt_resource *r = &rdt_resources_all[RDT_RESOURCE_L3].r_resctrl; + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); + char *abmc_str, *event_str; + struct rdtgroup *rdtgrp; + int ret = 0, mon_state; + u32 evtid; + + rdtgrp = rdtgroup_kn_lock_live(of->kn); + if (!rdtgrp) { + rdtgroup_kn_unlock(of->kn); + return -EINVAL; + } + + if (!hw_res->abmc_enabled) { + rdt_last_cmd_puts("ABMC is not enabled\n"); + rdtgroup_kn_unlock(of->kn); + return -EINVAL; + } + + rdt_last_cmd_clear(); + + while (buf && buf[0] != '\0') { + /* Start processing the strings for each domain */ + abmc_str = strim(strsep(&buf, ";")); + event_str = strsep(&abmc_str, "="); + + if (event_str && abmc_str) { + if (!strcmp(event_str, "total")) { + mon_state = TOTAL_ASSIGN; + evtid = QOS_L3_MBM_TOTAL_EVENT_ID; + } else if (!strcmp(event_str, "local")) { + mon_state = LOCAL_ASSIGN; + evtid = QOS_L3_MBM_LOCAL_EVENT_ID; + } else { + rdt_last_cmd_puts("Invalid ABMC event\n"); + ret = -EINVAL; + break; + } + + if (!strcmp(abmc_str, "assign")) { + ret = rdtgroup_assign_abmc(rdtgrp, r, evtid, mon_state); + if (ret) { + rdt_last_cmd_puts("ABMC assign failed\n"); + break; + } + } else { + rdt_last_cmd_puts("Invalid ABMC event\n"); + ret = -EINVAL; + break; + } + } else { + rdt_last_cmd_puts("Invalid ABMC input\n"); + ret = -EINVAL; + break; + } + } + + rdtgroup_kn_unlock(of->kn); + return ret ?: nbytes; +} + static void mon_event_config_read(void *info) { struct mon_config_info *mon_info = info; @@ -2003,9 +2160,10 @@ static struct rftype res_common_files[] = { }, { .name = "monitor_state", - .mode = 0444, + .mode = 0644, .kf_ops = &rdtgroup_kf_single_ops, .seq_show = rdtgroup_monitor_state_show, + .write = rdtgroup_monitor_state_write, }, { .name = "tasks", From patchwork Fri Jan 19 18:22:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189648 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1195289dyb; Fri, 19 Jan 2024 10:27:12 -0800 (PST) X-Google-Smtp-Source: AGHT+IHpJZR8gl1qmRjEEMY6zh45I4P0T+MexdvtnYAhIeWqMxybD7FruViYVH/W2xuuleqsfYhn X-Received: by 2002:a17:906:b112:b0:a28:b34d:8694 with SMTP id u18-20020a170906b11200b00a28b34d8694mr254936ejy.62.1705688832456; Fri, 19 Jan 2024 10:27:12 -0800 (PST) Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:29.1557 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4659b8d1-7829-4802-1701-08dc191be015 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN7PR12MB7228 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544372744426460 X-GMAIL-MSGID: 1788544372744426460 With the support of ABMC (Assignable Bandwidth Monitoring Counters) feature, the user has the option to assign or unassign a RMID to hardware counter and monitor the bandwidth for the longer duration. Provide the interface to unassign the RMID. Signed-off-by: Babu Moger --- v2: No changes. --- Documentation/arch/x86/resctrl.rst | 11 ++++++++ arch/x86/kernel/cpu/resctrl/internal.h | 1 + arch/x86/kernel/cpu/resctrl/rdtgroup.c | 36 ++++++++++++++++++++++++++ 3 files changed, 48 insertions(+) diff --git a/Documentation/arch/x86/resctrl.rst b/Documentation/arch/x86/resctrl.rst index 2729c6fe6127..4ba9b1275a2b 100644 --- a/Documentation/arch/x86/resctrl.rst +++ b/Documentation/arch/x86/resctrl.rst @@ -427,6 +427,17 @@ When monitoring is enabled all MON groups will also contain: # echo total=assign > /sys/fs/resctrl/monitor_state # echo total=assign;local=assign > /sys/fs/resctrl/monitor_state + The user needs to unassign counter to release it. + Example:: + + # echo total=unassign > /sys/fs/resctrl/monitor_state + # cat /sys/fs/resctrl/monitor_state + total=unassign;local=assign + + # echo total=unassign;local=unassign > /sys/fs/resctrl/monitor_state + # cat /sys/fs/resctrl/monitor_state + total=unassign;local=unassign + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. diff --git a/arch/x86/kernel/cpu/resctrl/internal.h b/arch/x86/kernel/cpu/resctrl/internal.h index e109c0388762..ca3193986b4f 100644 --- a/arch/x86/kernel/cpu/resctrl/internal.h +++ b/arch/x86/kernel/cpu/resctrl/internal.h @@ -614,5 +614,6 @@ void __init resctrl_file_fflags_init(const char *config, unsigned long fflags); void rdt_staged_configs_clear(void); void arch_domain_mbm_evt_config(struct rdt_hw_domain *hw_dom); +void assignable_counters_free(int counterid); #endif /* _ASM_X86_RESCTRL_INTERNAL_H */ diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 3447fc4ff2e9..869fab878087 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -192,6 +192,11 @@ static int assignable_counters_alloc(void) return counterid; } +void assignable_counters_free(int counterid) +{ + assignable_counter_free_map |= 1 << counterid; +} + /** * rdtgroup_mode_by_closid - Return mode of resource group with closid * @closid: closid if the resource group @@ -1723,6 +1728,31 @@ static ssize_t rdtgroup_assign_abmc(struct rdtgroup *rdtgrp, return 0; } +static ssize_t rdtgroup_unassign_abmc(struct rdtgroup *rdtgrp, + struct rdt_resource *r, + u32 evtid, int mon_state) +{ + struct rdt_domain *d; + int index; + + index = mon_event_config_index_get(evtid); + if (index == INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return -EINVAL; + } + + if (rdtgrp->mon.monitor_state & mon_state) { + list_for_each_entry(d, &r->domains, list) + rdtgroup_abmc_domain(d, rdtgrp, evtid, index, 0); + + assignable_counters_free(rdtgrp->mon.abmc_ctr_id[index]); + } + + rdtgrp->mon.monitor_state &= ~mon_state; + + return 0; +} + /** * rdtgroup_monitor_state_write - Interface to assign/unassign an RMID. * @@ -1776,6 +1806,12 @@ static ssize_t rdtgroup_monitor_state_write(struct kernfs_open_file *of, rdt_last_cmd_puts("ABMC assign failed\n"); break; } + } else if (!strcmp(abmc_str, "unassign")) { + ret = rdtgroup_unassign_abmc(rdtgrp, r, evtid, mon_state); + if (ret) { + rdt_last_cmd_puts("ABMC unassign failed\n"); + break; + } } else { rdt_last_cmd_puts("Invalid ABMC event\n"); ret = -EINVAL; From patchwork Fri Jan 19 18:22:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Moger, Babu" X-Patchwork-Id: 189652 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp1197904dyb; Fri, 19 Jan 2024 10:31:51 -0800 (PST) X-Google-Smtp-Source: AGHT+IEbinEufpkLoxZoSNcbW3n4JCA/RtOW3iqdL4A0d3GfF5ImHaHQAPeLyjaqfbNBbY3NcssP X-Received: by 2002:a05:6e02:13e2:b0:361:a70e:d8e with SMTP id w2-20020a056e0213e200b00361a70e0d8emr302335ilj.4.1705689111577; Fri, 19 Jan 2024 10:31:51 -0800 (PST) Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Jan 2024 18:24:36.9797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: ea4c0f7d-d4e7-4732-6448-08dc191be4b5 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF00001CE2.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB5639 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788544665596819414 X-GMAIL-MSGID: 1788544665596819414 When ABMC (Assignable Bandwidth Monitoring Counters) feature is enabled, bandwidth events can be read in following methods. 1. The contents of a specific counter can be read by setting the following fields in QM_EVTSEL: [ExtendedEvtID]=1, [EvtID]=L3CacheABMC and setting [RMID] to the desired counter ID. Reading QM_CTR will then return the contents of the specified counter. The E bit will be set if the counter configuration was invalid, or if an invalid counter ID was set in the QM_EVTSEL[RMID] field. The rmid_read interface (resctrl_arch_rmid_read) does not support this method currently. Supporting this method will require changes in rmid_read interface. 2. Alternatively, the contents of a counter may be read by specifying an RMID and setting the [EvtID] to L3BWMonEvtn where n= {0,1}. If an assignable bandwidth counter is monitoring that RMID with a BwType bitmask that matches a QOS_EVT_CFG_n, that counter’s value will be returned when reading QM_CTR. However, if multiple counters have the same configuration, QM_CTR will return the value of the counter with the lowest CtrID. Method 2 can be supported without any changes to rmid_read interface. However, this requires the contents of the MSR QOS_EVT_CFG_[0,1] to match the BwType while assigning total and local events respectively. So, whenever event configuration changes, the ABMC assignment needs to be updated to match the event configuration. The feature details are documented in APM listed below [1]. [1] AMD64 Architecture Programmer's Manual Volume 2: System Programming Publication # 24593 Revision 3.41 section 19.3.3.3 Assignable Bandwidth Monitoring (ABMC). Signed-off-by: Babu Moger Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537 --- v2: Minor text changes. --- arch/x86/kernel/cpu/resctrl/rdtgroup.c | 40 ++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/arch/x86/kernel/cpu/resctrl/rdtgroup.c b/arch/x86/kernel/cpu/resctrl/rdtgroup.c index 869fab878087..91a20e601ffd 100644 --- a/arch/x86/kernel/cpu/resctrl/rdtgroup.c +++ b/arch/x86/kernel/cpu/resctrl/rdtgroup.c @@ -1828,6 +1828,38 @@ static ssize_t rdtgroup_monitor_state_write(struct kernfs_open_file *of, return ret ?: nbytes; } +static void rdtgroup_update_abmc(struct rdt_resource *r, + struct rdt_domain *d, u32 evtid) +{ + struct rdtgroup *prgrp, *crgrp; + int index, mon_state; + + if (evtid == QOS_L3_MBM_TOTAL_EVENT_ID) + mon_state = TOTAL_ASSIGN; + else + mon_state = LOCAL_ASSIGN; + + index = mon_event_config_index_get(evtid); + if (index == INVALID_CONFIG_INDEX) { + pr_warn_once("Invalid event id %d\n", evtid); + return; + } + + /* + * Update the assignment for all the monitor groups if the group + * is configured with ABMC assignment. + */ + list_for_each_entry(prgrp, &rdt_all_groups, rdtgroup_list) { + if (prgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, prgrp, evtid, index, 1); + + list_for_each_entry(crgrp, &prgrp->mon.crdtgrp_list, mon.crdtgrp_list) { + if (crgrp->mon.monitor_state & mon_state) + rdtgroup_abmc_domain(d, crgrp, evtid, index, 1); + } + } +} + static void mon_event_config_read(void *info) { struct mon_config_info *mon_info = info; @@ -1912,6 +1944,7 @@ static void mon_event_config_write(void *info) static int mbm_config_write_domain(struct rdt_resource *r, struct rdt_domain *d, u32 evtid, u32 val) { + struct rdt_hw_resource *hw_res = resctrl_to_arch_res(r); struct rdt_hw_domain *hw_dom = resctrl_to_arch_dom(d); struct mon_config_info mon_info = {0}; int ret = 0; @@ -1952,6 +1985,13 @@ static int mbm_config_write_domain(struct rdt_resource *r, else goto out; + /* + * Event configuration changed for the domain, so Update + * the ABMC assignment. + */ + if (hw_res->abmc_enabled) + rdtgroup_update_abmc(r, d, evtid); + /* * When an Event Configuration is changed, the bandwidth counters * for all RMIDs and Events will be cleared by the hardware. The