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Fri, 19 Jan 2024 13:00:35 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0WkT023724; Fri, 19 Jan 2024 13:00:34 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0Y2q023744; Fri, 19 Jan 2024 13:00:34 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id C9210273A; Fri, 19 Jan 2024 18:30:33 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 1/6] dmaengine: dw-edma: Pass 'struct dw_edma_chip' to irq_vector() Date: Fri, 19 Jan 2024 18:30:17 +0530 Message-Id: <1705669223-5655-2-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WlzlZGLYn8B3rU-ATzMvi9l1ccD_fOIz X-Proofpoint-ORIG-GUID: WlzlZGLYn8B3rU-ATzMvi9l1ccD_fOIz X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 lowpriorityscore=0 mlxlogscore=863 phishscore=0 bulkscore=0 impostorscore=0 suspectscore=0 priorityscore=1501 adultscore=0 malwarescore=0 spamscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190066 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523945317171628 X-GMAIL-MSGID: 1788523945317171628 From: Manivannan Sadhasivam eDMA client drivers defining the irq_vector() callback need to access the members of dw_edma_chip structure. So let's pass that pointer instead. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mrinmay Sarkar Reviewed-by: Dmitry Baryshkov --- drivers/dma/dw-edma/dw-edma-core.c | 11 +++++------ drivers/dma/dw-edma/dw-edma-pcie.c | 4 ++-- drivers/pci/controller/dwc/pcie-designware.c | 4 ++-- include/linux/dma/edma.h | 3 ++- 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 6823624..7fe1c19 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -849,7 +849,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, if (chip->nr_irqs == 1) { /* Common IRQ shared among all channels */ - irq = chip->ops->irq_vector(dev, 0); + irq = chip->ops->irq_vector(chip, 0); err = request_irq(irq, dw_edma_interrupt_common, IRQF_SHARED, dw->name, &dw->irq[0]); if (err) { @@ -874,7 +874,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, dw_edma_add_irq_mask(&rd_mask, *rd_alloc, dw->rd_ch_cnt); for (i = 0; i < (*wr_alloc + *rd_alloc); i++) { - irq = chip->ops->irq_vector(dev, i); + irq = chip->ops->irq_vector(chip, i); err = request_irq(irq, i < *wr_alloc ? dw_edma_interrupt_write : @@ -895,7 +895,7 @@ static int dw_edma_irq_request(struct dw_edma *dw, err_irq_free: for (i--; i >= 0; i--) { - irq = chip->ops->irq_vector(dev, i); + irq = chip->ops->irq_vector(chip, i); free_irq(irq, &dw->irq[i]); } @@ -975,7 +975,7 @@ int dw_edma_probe(struct dw_edma_chip *chip) err_irq_free: for (i = (dw->nr_irqs - 1); i >= 0; i--) - free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]); + free_irq(chip->ops->irq_vector(chip, i), &dw->irq[i]); return err; } @@ -984,7 +984,6 @@ EXPORT_SYMBOL_GPL(dw_edma_probe); int dw_edma_remove(struct dw_edma_chip *chip) { struct dw_edma_chan *chan, *_chan; - struct device *dev = chip->dev; struct dw_edma *dw = chip->dw; int i; @@ -997,7 +996,7 @@ int dw_edma_remove(struct dw_edma_chip *chip) /* Free irqs */ for (i = (dw->nr_irqs - 1); i >= 0; i--) - free_irq(chip->ops->irq_vector(dev, i), &dw->irq[i]); + free_irq(chip->ops->irq_vector(chip, i), &dw->irq[i]); /* Deregister eDMA device */ dma_async_device_unregister(&dw->dma); diff --git a/drivers/dma/dw-edma/dw-edma-pcie.c b/drivers/dma/dw-edma/dw-edma-pcie.c index 1c60437..2b13725 100644 --- a/drivers/dma/dw-edma/dw-edma-pcie.c +++ b/drivers/dma/dw-edma/dw-edma-pcie.c @@ -90,9 +90,9 @@ static const struct dw_edma_pcie_data snps_edda_data = { .rd_ch_cnt = 2, }; -static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr) +static int dw_edma_pcie_irq_vector(struct dw_edma_chip *chip, unsigned int nr) { - return pci_irq_vector(to_pci_dev(dev), nr); + return pci_irq_vector(to_pci_dev(chip->dev), nr); } static u64 dw_edma_pcie_address(struct device *dev, phys_addr_t cpu_addr) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 250cf7f..eca047a 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -858,9 +858,9 @@ static u32 dw_pcie_readl_dma(struct dw_pcie *pci, u32 reg) return val; } -static int dw_pcie_edma_irq_vector(struct device *dev, unsigned int nr) +static int dw_pcie_edma_irq_vector(struct dw_edma_chip *edma, unsigned int nr) { - struct platform_device *pdev = to_platform_device(dev); + struct platform_device *pdev = to_platform_device(edma->dev); char name[6]; int ret; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 3080747..7197a58 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -16,6 +16,7 @@ #define EDMA_MAX_RD_CH 8 struct dw_edma; +struct dw_edma_chip; struct dw_edma_region { u64 paddr; @@ -41,7 +42,7 @@ struct dw_edma_region { * automatically. */ struct dw_edma_plat_ops { - int (*irq_vector)(struct device *dev, unsigned int nr); + int (*irq_vector)(struct dw_edma_chip *chip, unsigned int nr); u64 (*pci_address)(struct device *dev, phys_addr_t cpu_addr); }; From patchwork Fri Jan 19 13:00:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 189547 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp987760dyb; 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Fri, 19 Jan 2024 13:00:37 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0bIf023767; Fri, 19 Jan 2024 13:00:37 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0aYK023765; Fri, 19 Jan 2024 13:00:37 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 1748B273A; Fri, 19 Jan 2024 18:30:36 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 2/6] dmaengine: dw-edma: Introduce helpers for getting the eDMA/HDMA max channel count Date: Fri, 19 Jan 2024 18:30:18 +0530 Message-Id: <1705669223-5655-3-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: GmMST81T2hRl2-fzUAeJ0DfgPBStIF6_ X-Proofpoint-GUID: GmMST81T2hRl2-fzUAeJ0DfgPBStIF6_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 spamscore=0 suspectscore=0 clxscore=1015 mlxlogscore=843 impostorscore=0 lowpriorityscore=0 mlxscore=0 bulkscore=0 priorityscore=1501 phishscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190066 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523903558496300 X-GMAIL-MSGID: 1788523903558496300 From: Manivannan Sadhasivam Add common helpers for getting the eDMA/HDMA max channel count. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mrinmay Sarkar --- drivers/dma/dw-edma/dw-edma-core.c | 18 ++++++++++++++++++ drivers/pci/controller/dwc/pcie-designware.c | 6 +++--- include/linux/dma/edma.h | 14 ++++++++++++++ 3 files changed, 35 insertions(+), 3 deletions(-) diff --git a/drivers/dma/dw-edma/dw-edma-core.c b/drivers/dma/dw-edma/dw-edma-core.c index 7fe1c19..2bd6e43 100644 --- a/drivers/dma/dw-edma/dw-edma-core.c +++ b/drivers/dma/dw-edma/dw-edma-core.c @@ -902,6 +902,24 @@ static int dw_edma_irq_request(struct dw_edma *dw, return err; } +static u32 dw_edma_get_max_ch(enum dw_edma_map_format mf, enum dw_edma_dir dir) +{ + if (mf == EDMA_MF_HDMA_NATIVE) + return HDMA_MAX_NR_CH; + + return dir == EDMA_DIR_WRITE ? EDMA_MAX_WR_CH : EDMA_MAX_RD_CH; +} + +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) +{ + return dw_edma_get_max_ch(mf, EDMA_DIR_READ); +} + +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) +{ + return dw_edma_get_max_ch(mf, EDMA_DIR_WRITE); +} + int dw_edma_probe(struct dw_edma_chip *chip) { struct device *dev; diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index eca047a..96575b8 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -864,7 +864,7 @@ static int dw_pcie_edma_irq_vector(struct dw_edma_chip *edma, unsigned int nr) char name[6]; int ret; - if (nr >= EDMA_MAX_WR_CH + EDMA_MAX_RD_CH) + if (nr >= dw_edma_get_max_rd_ch(edma->mf) + dw_edma_get_max_wr_ch(edma->mf)) return -EINVAL; ret = platform_get_irq_byname_optional(pdev, "dma"); @@ -923,8 +923,8 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); /* Sanity check the channels count if the mapping was incorrect */ - if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > EDMA_MAX_WR_CH || - !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > EDMA_MAX_RD_CH) + if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > dw_edma_get_max_wr_ch(pci->edma.mf) || + !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > dw_edma_get_max_rd_ch(pci->edma.mf)) return -EINVAL; return 0; diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 7197a58..550f6a4 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -106,6 +106,9 @@ struct dw_edma_chip { #if IS_REACHABLE(CONFIG_DW_EDMA) int dw_edma_probe(struct dw_edma_chip *chip); int dw_edma_remove(struct dw_edma_chip *chip); + +u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf); +u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf); #else static inline int dw_edma_probe(struct dw_edma_chip *chip) { @@ -116,6 +119,17 @@ static inline int dw_edma_remove(struct dw_edma_chip *chip) { return 0; } + +static inline u32 dw_edma_get_max_rd_ch(enum dw_edma_map_format mf) +{ + return 0; +} + +static inline u32 dw_edma_get_max_wr_ch(enum dw_edma_map_format mf) +{ + return 0; +} + #endif /* CONFIG_DW_EDMA */ #endif /* _DW_EDMA_H */ From patchwork Fri Jan 19 13:00:19 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 189549 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp988795dyb; Fri, 19 Jan 2024 05:02:52 -0800 (PST) X-Google-Smtp-Source: AGHT+IG7/KJaU+1xm5IfKQ9IDjCn1ADDbKm5DBfmf8P9UPEjrO8xbbWGuLxK9siGymvDgorgv/et X-Received: by 2002:ac8:5755:0:b0:42a:153c:af5d with SMTP id 21-20020ac85755000000b0042a153caf5dmr1466346qtx.34.1705669372509; Fri, 19 Jan 2024 05:02:52 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705669372; cv=pass; d=google.com; s=arc-20160816; b=EZNiibR+hs3S0spRwEVxjlRnAMcHSQOya6XgtT4ZGfXCYNPReL7ZaZ0j0Hx92lfRV7 Y4Zlua+JX7+SZ3iDbpsMxD3ML3l9njeGIDNtvmBLO/rnLvLjWY/EetFkH+Ws0b/JuYIZ 22WBH3jZNf6aDKQuO290ARLpPOP2a/z56O5ge0hu+3Iwti86Zp7D3cJ8oDuZdsmFoc5J Y+wJeRXz8qv1cRREwTjyc4HvoLspJv4cadkCoGihTRVusyhhWPap/fxFgwqz5AhcguIK L0luDunqdA0aFq1Ga8nYePzgVKA2rskRAEJDdCBae0sVYpnXdchjufWW0ytSi7I6bkHw uUxA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=J5N0eH+XorUHi+CvGk/WwzsrjWyuz4FCQ2eZXs4R5nY=; fh=A9BXgcrlMZ5z9wYoTmuXIwTqeYf3DKZIOMrQtykU1fI=; b=Mv/nwyapdR3XWVlO3iIJXJSmQghxrmhAi/gmJqHS2GLC2uBKfQAdL9pq2giA092FUb 0nXs1a09wBb9SL+WH4A4LK44yM0cejFnBY0keG9dxVKtdagxK23ghoqPrLuVLvxXlpAJ 91gfyv8HCdrxaA63RUBPTrOI8XviFjUs6yv6c3Pfa50J4Frp8qQQbNuiV9CAORO2Zcox 1YC94vGxbSnD2cIbIr62011TbGV1wnLDfpM3Uuu4SeCKIOxACAYMQgkiLkO6+CsrGpaD vM1iHdanlt96vNgntEp9IoNxgwgosuKWUvalQ84uzvEQpEoriI8Wt1cZ+jw0XhYPUFa0 eniw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=chlwqT5n; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-31160-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31160-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 19 Jan 2024 13:00:40 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0dLE023785; Fri, 19 Jan 2024 13:00:39 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0dlN023784; Fri, 19 Jan 2024 13:00:39 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 3BC35273A; Fri, 19 Jan 2024 18:30:38 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 3/6] PCI: dwc: Add HDMA support Date: Fri, 19 Jan 2024 18:30:19 +0530 Message-Id: <1705669223-5655-4-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: z69Q7pBn-mgOoTOjfxot1-qCLdMS5U1p X-Proofpoint-ORIG-GUID: z69Q7pBn-mgOoTOjfxot1-qCLdMS5U1p X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 mlxlogscore=803 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190066 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523968305530292 X-GMAIL-MSGID: 1788523968305530292 From: Manivannan Sadhasivam Hyper DMA (HDMA) is already supported by the dw-edma dmaengine driver. Unlike it's predecessor Embedded DMA (eDMA), HDMA supports only the unrolled mapping format. So the platform drivers need to provide a valid base address of the CSRs. Also, there is no standard way to auto detect the number of available read/write channels in a platform. So the platform drivers has to provide that information as well. For adding HDMA support, the mapping format set by the platform drivers is used to detect whether eDMA or HDMA is being used, since we cannot auto detect it in a sane way. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-designware.c | 55 ++++++++++++++++++++++++---- 1 file changed, 47 insertions(+), 8 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 96575b8..07a1f2d 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -880,7 +880,29 @@ static struct dw_edma_plat_ops dw_pcie_edma_ops = { .irq_vector = dw_pcie_edma_irq_vector, }; -static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +static int dw_pcie_find_hdma(struct dw_pcie *pci) +{ + /* + * Since HDMA supports only unrolled mapping, platform drivers need to + * provide a valid base address. + */ + if (!pci->edma.reg_base) + return -ENODEV; + + /* + * Since there is no standard way to detect the number of read/write + * HDMA channels, platform drivers are expected to provide the channel + * count. Let's also do a sanity check of them to make sure that the + * counts are within the limit specified by the spec. + */ + if (!pci->edma.ll_wr_cnt || pci->edma.ll_wr_cnt > dw_edma_get_max_wr_ch(pci->edma.mf) || + !pci->edma.ll_rd_cnt || pci->edma.ll_rd_cnt > dw_edma_get_max_rd_ch(pci->edma.mf)) + return -EINVAL; + + return 0; +} + +static int dw_pcie_find_edma(struct dw_pcie *pci) { u32 val; @@ -912,13 +934,6 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return -ENODEV; } - pci->edma.dev = pci->dev; - - if (!pci->edma.ops) - pci->edma.ops = &dw_pcie_edma_ops; - - pci->edma.flags |= DW_EDMA_CHIP_LOCAL; - pci->edma.ll_wr_cnt = FIELD_GET(PCIE_DMA_NUM_WR_CHAN, val); pci->edma.ll_rd_cnt = FIELD_GET(PCIE_DMA_NUM_RD_CHAN, val); @@ -930,6 +945,30 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) return 0; } +static int dw_pcie_edma_find_chip(struct dw_pcie *pci) +{ + int ret; + + if (pci->edma.mf == EDMA_MF_HDMA_NATIVE) { + ret = dw_pcie_find_hdma(pci); + if (ret) + return ret; + } else { + ret = dw_pcie_find_edma(pci); + if (ret) + return ret; + } + + pci->edma.dev = pci->dev; + + if (!pci->edma.ops) + pci->edma.ops = &dw_pcie_edma_ops; + + pci->edma.flags |= DW_EDMA_CHIP_LOCAL; + + return 0; +} + static int dw_pcie_edma_irq_verify(struct dw_pcie *pci) { struct platform_device *pdev = to_platform_device(pci->dev); From patchwork Fri Jan 19 13:00:20 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 189550 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp988945dyb; Fri, 19 Jan 2024 05:03:04 -0800 (PST) X-Google-Smtp-Source: AGHT+IH3gl5KmLLnG/YWgsQlGnpUDzudRODRlrhK0vaSlz1vYf9nstqN8SLlhAJ217wnhJdhM+zU X-Received: by 2002:a05:620a:29c5:b0:783:8db7:4f29 with SMTP id s5-20020a05620a29c500b007838db74f29mr355260qkp.32.1705669383927; Fri, 19 Jan 2024 05:03:03 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705669383; cv=pass; d=google.com; s=arc-20160816; b=GlYo9XNI7YbVV94gXlKlRQUIBWtRh+HN7U27PhX+Vju987znIePXSi9mnw+uBaYxCj TRmdG3GCUNclrPsXMhRy8FuXYfZoPl5EzxKVZhnX46a9hIOo7ckjMnt/7IFDjkpGAHIg 5vDQQi7vMGVJ+Ysyq8sWaRwIi3Rt3DZRgpIzdLFxj1hLJmCnnydNXgBJn+WX5NLCRNiD AXtvbPS8MKImy7r1cBZFkE3Ob9VrFtb8HWbSDpZWZDj4IjP9QBFJBmSbqcq4/SyKxIZu khMyhKBpVEk9nF7Ljg1OKB1zFLrGU8xnw+HBy0ttutra98di9dM9ZtaqL4vrBn+AilHa yNkg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=fK+ysfreXQCoYCrRDidxH8G6FWPAOE4Xo0Df71HiZKw=; fh=A9BXgcrlMZ5z9wYoTmuXIwTqeYf3DKZIOMrQtykU1fI=; b=vNaqzdi3FvuSoDWEAu8JlrqhE064MzP+RC8wjfHi8uce345CulmbrXTMASIUbya3I7 /6O5l3ycAaSwMalIotPIOPLIGj7QRPruqBJ5EaogQt0e9l0wvrM4lk8+EVNbmqX/lM0V w4ml8B8L+wIpEm1t8BGWG/AH8ZDfU1WAtqQogwoYKU1M0GyKoEkNdjg0rZKB1EW2ILTp 0wHfBT1e+OHPcEkxiN0Smkelx7TKHa9aalX8l29nwHl+qBMOCR/KJE5NJ8sBF2G5WJmv 8DV8N+5diyN7XD4X7/y63MrPvVBfboD8UsTVTyBclyI5S7y4XB7oyBLIPpw3SAANqgst Ytlw== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=l1SAwvsn; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-31162-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31162-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 19 Jan 2024 13:00:42 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0fbb023804; Fri, 19 Jan 2024 13:00:41 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0fN1023801; Fri, 19 Jan 2024 13:00:41 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 5BE75273A; Fri, 19 Jan 2024 18:30:40 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 4/6] dmaengine: dw-edma: Move HDMA_V0_MAX_NR_CH definition to edma.h Date: Fri, 19 Jan 2024 18:30:20 +0530 Message-Id: <1705669223-5655-5-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 2M1_j7cANaScCFkrQDV0zx96fN0Wmx4y X-Proofpoint-ORIG-GUID: 2M1_j7cANaScCFkrQDV0zx96fN0Wmx4y X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 adultscore=0 clxscore=1015 impostorscore=0 phishscore=0 mlxlogscore=695 mlxscore=0 suspectscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190066 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523979734583145 X-GMAIL-MSGID: 1788523979734583145 From: Manivannan Sadhasivam To maintain uniformity with eDMA, let's move the HDMA max channel definition to edma.h. While at it, let's also rename it to HDMA_MAX_NR_CH. Signed-off-by: Manivannan Sadhasivam Signed-off-by: Mrinmay Sarkar --- drivers/dma/dw-edma/dw-hdma-v0-core.c | 4 ++-- drivers/dma/dw-edma/dw-hdma-v0-regs.h | 3 +-- include/linux/dma/edma.h | 1 + 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c index 1f4cb7d..819ef1f 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c @@ -54,7 +54,7 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw) { int id; - for (id = 0; id < HDMA_V0_MAX_NR_CH; id++) { + for (id = 0; id < HDMA_MAX_NR_CH; id++) { SET_BOTH_CH_32(dw, id, int_setup, HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); SET_BOTH_CH_32(dw, id, int_clear, @@ -70,7 +70,7 @@ static u16 dw_hdma_v0_core_ch_count(struct dw_edma *dw, enum dw_edma_dir dir) * available, we set it to maximum channels and let the platform * set the right number of channels. */ - return HDMA_V0_MAX_NR_CH; + return HDMA_MAX_NR_CH; } static enum dma_status dw_hdma_v0_core_ch_status(struct dw_edma_chan *chan) diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h index a974abd..cd7eab2 100644 --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h @@ -11,7 +11,6 @@ #include -#define HDMA_V0_MAX_NR_CH 8 #define HDMA_V0_LOCAL_ABORT_INT_EN BIT(6) #define HDMA_V0_REMOTE_ABORT_INT_EN BIT(5) #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) @@ -92,7 +91,7 @@ struct dw_hdma_v0_ch { } __packed; struct dw_hdma_v0_regs { - struct dw_hdma_v0_ch ch[HDMA_V0_MAX_NR_CH]; /* 0x0000..0x0fa8 */ + struct dw_hdma_v0_ch ch[HDMA_MAX_NR_CH]; /* 0x0000..0x0fa8 */ } __packed; struct dw_hdma_v0_lli { diff --git a/include/linux/dma/edma.h b/include/linux/dma/edma.h index 550f6a4..2cdf249a 100644 --- a/include/linux/dma/edma.h +++ b/include/linux/dma/edma.h @@ -14,6 +14,7 @@ #define EDMA_MAX_WR_CH 8 #define EDMA_MAX_RD_CH 8 +#define HDMA_MAX_NR_CH 8 struct dw_edma; struct dw_edma_chip; From patchwork Fri Jan 19 13:00:21 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 189552 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp989923dyb; Fri, 19 Jan 2024 05:04:16 -0800 (PST) X-Google-Smtp-Source: AGHT+IE3tXV5oEtThIN09uneeQXO9y+IZyfn4ulf0rdvnPoN26mQzA0EizgtZNpDZ7PNjzqkxEdY X-Received: by 2002:a17:902:b7c7:b0:1d7:572:29 with SMTP id v7-20020a170902b7c700b001d705720029mr1234203plz.1.1705669455905; Fri, 19 Jan 2024 05:04:15 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705669455; cv=pass; d=google.com; s=arc-20160816; b=d7HVVlf8/n4p1CsCZJUP1ZHFwe1NidUX6dGjb3zEnlXC6KWdLXfhy0Zl7SgVCnEiI7 SQ5jLXUjH1P6lFrLhnAYkrfft4C5jYYS3Ez7aUx5ms7g9h3XE+JCgkVFki3JBm39uzna qnvktWxsu88i5yNZSsVclj9QNQ1G684XqHOIe+tUltFGMgWHN4EkVft5e8i7cMgmi2Vn 96JjmyDy43NxnzVHC/djCkCfGLF2ytMSjWuBZYbpPtS8qUKRVhOIs+8o7uq3i+XrdJvv 9KMsiI9yHh3hS1bOX58LtRRTkKWpiui5aU8lc9YuNl2wOWxGhA/tLRtX39Fc9WHiGria D/Eg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=kvzZR+kG3EOMUkKldFt2KjVBCWiNRqBgBOnY3xjuKO4=; fh=A9BXgcrlMZ5z9wYoTmuXIwTqeYf3DKZIOMrQtykU1fI=; b=d4gmMGfheet5AeKKrZK22AwUxvTAJGy/ZdIzKHe8qgQeb7E3130KIf3poxM8TLdIBU rDX/g934pUMvWK+ft++jbyn4TiLvFWWhbsjhvxMeRSEvzEJ+GZ67VbK1TAww+9d9Wfud 7GYOE9TfHPZQrr7tjG6hp42jtD4GiqmjXv6I34usf6TiNuBZmJl0/uGt8yC3Ehm7p2+D BZuIYGzNlnEJwZHFgIENJJMV87Zct8ylkXJru8mShp3rRC2mNQ10/o2toCBIIFSDFv2e +/BAn6jyJXS8618JxoNupNIg44Db+e/8lqGdL2gZfPrmf3Jy85c7dOXtkgnPpxH06+AT Iu7A== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b=DcJVAeFc; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-31161-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:40f1:3f00::1 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31161-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 19 Jan 2024 13:00:43 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0fbd023804; Fri, 19 Jan 2024 13:00:43 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0hlw023830; Fri, 19 Jan 2024 13:00:43 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 2D4EE273A; Fri, 19 Jan 2024 18:30:42 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 5/6] PCI: qcom-ep: Provide number of read/write channel for HDMA Date: Fri, 19 Jan 2024 18:30:21 +0530 Message-Id: <1705669223-5655-6-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 3DMeqHBM_sncGLSzpC3AZKYrcE71h8st X-Proofpoint-GUID: 3DMeqHBM_sncGLSzpC3AZKYrcE71h8st X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 phishscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 spamscore=0 lowpriorityscore=0 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=783 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190066 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788524055571526565 X-GMAIL-MSGID: 1788524055571526565 There is no standard way to auto detect the number of available read/write channels in a platform. So adding this change to provide read/write channels count and also provide "EDMA_MF_HDMA_NATIVE" flag to support HDMA for 8775 platform. 8775 has IP version 1.34.0 so intruduce a new cfg(cfg_1_34_0) for this platform. Add struct qcom_pcie_ep_cfg as match data. Assign hdma_supported flag into struct qcom_pcie_ep_cfg and set it true in cfg_1_34_0. Signed-off-by: Mrinmay Sarkar --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 45008e0..8d56435 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -149,6 +149,10 @@ enum qcom_pcie_ep_link_status { QCOM_PCIE_EP_LINK_DOWN, }; +struct qcom_pcie_ep_cfg { + bool hdma_supported; +}; + /** * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller * @pci: Designware PCIe controller struct @@ -167,6 +171,7 @@ enum qcom_pcie_ep_link_status { * @num_clks: PCIe clocks count * @perst_en: Flag for PERST enable * @perst_sep_en: Flag for PERST separation enable + * @cfg: PCIe EP config struct * @link_status: PCIe Link status * @global_irq: Qualcomm PCIe specific Global IRQ * @perst_irq: PERST# IRQ @@ -194,6 +199,7 @@ struct qcom_pcie_ep { u32 perst_en; u32 perst_sep_en; + const struct qcom_pcie_ep_cfg *cfg; enum qcom_pcie_ep_link_status link_status; int global_irq; int perst_irq; @@ -511,6 +517,10 @@ static void qcom_pcie_perst_assert(struct dw_pcie *pci) pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED; } +static const struct qcom_pcie_ep_cfg cfg_1_34_0 = { + .hdma_supported = true, +}; + /* Common DWC controller ops */ static const struct dw_pcie_ops pci_ops = { .link_up = qcom_pcie_dw_link_up, @@ -816,6 +826,13 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; pcie_ep->pci.edma.nr_irqs = 1; + + pcie_ep->cfg = of_device_get_match_data(dev); + if (pcie_ep->cfg && pcie_ep->cfg->hdma_supported) { + pcie_ep->pci.edma.ll_wr_cnt = 1; + pcie_ep->pci.edma.ll_rd_cnt = 1; + pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE; + } platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); @@ -875,7 +892,7 @@ static void qcom_pcie_ep_remove(struct platform_device *pdev) } static const struct of_device_id qcom_pcie_ep_match[] = { - { .compatible = "qcom,sa8775p-pcie-ep", }, + { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0}, { .compatible = "qcom,sdx55-pcie-ep", }, { .compatible = "qcom,sm8450-pcie-ep", }, { } From patchwork Fri Jan 19 13:00:22 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mrinmay Sarkar X-Patchwork-Id: 189551 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp988996dyb; Fri, 19 Jan 2024 05:03:07 -0800 (PST) X-Google-Smtp-Source: AGHT+IHty22JeGMmPPeok+qQYcT3MUrQ47RJNsxQ5vzDMhPn1AXSQz6gig9Gkzienu+6N16Z3TF7 X-Received: by 2002:a05:600c:c4:b0:40e:46b6:bc48 with SMTP id u4-20020a05600c00c400b0040e46b6bc48mr1542850wmm.41.1705669387519; Fri, 19 Jan 2024 05:03:07 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705669387; cv=pass; d=google.com; s=arc-20160816; b=Fy69Bd5nX1YkPkKrN/FkaY8YyrwTOzJlCWbBCNEuJUzveVo69R6f/2PxK64z5muOXi M+e0thD6FTHKpfoinVWKFKAlFseAi7GCMqcTNJ+VpHCtAmwXzqPDvtgq6EkK1KxLuxKO tJOPYtgaslbNpNWUkbOETt8pMy1eHTaIMgY0lS3nSsfewkRCokLurk2y4++YMhQU9ZXr ePDkMzPJblBSrhmwqKTlXmUWrSTFtdUaW0ObP4Gn0E8W+mitY+x5+thYHHRBhrxvBUrS gsef25mB9BM+Wl34vmCyjIOqc+bfQr+kCSOKfiNQ3C7iK3CsL75DaqtacPd44PgAD4M5 H7wQ== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-unsubscribe:list-subscribe:list-id:precedence:references :in-reply-to:message-id:date:subject:cc:to:from:dkim-signature; bh=jwanHwyWHbpZ4C33Snp/CmWYibz69kj30TZT29IAQw0=; fh=A9BXgcrlMZ5z9wYoTmuXIwTqeYf3DKZIOMrQtykU1fI=; b=CF2/ZmEICCwGqOXkGgkRCDNeUFTaUkpaJnp/YDfB+GiY51o+5HxjKY/ZxYO0HKyQZw wtSLXpM1lgQwGLBNKaXX05eZ0klrs5RMylPFhEMtb/JYGHkOKvmBoVKa55FlWxlERRHb bZPJkteORP8usfyy2GHCLreXa972IyY8cl0GcLBT4NWEb27YoA4FCrNe0h0uV1Q2tBsT K6Om9lgLndUEhRvHBgv0RsWVXRcEidpxHX1UrttE8E0+YH52i+b7VX+TNpwWECsj/MMK 6xtgO4ZbQY5xxT1waN3KiEyrQa2Q0V/jMBI0MnVi/vZ9l7z1vzqNfTxOvRevMUiTfQba c6BA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@quicinc.com header.s=qcppdkim1 header.b="LWYO/L2k"; arc=pass (i=1 spf=pass spfdomain=qualcomm.com dkim=pass dkdomain=quicinc.com dmarc=pass fromdomain=quicinc.com); spf=pass (google.com: domain of linux-kernel+bounces-31163-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.199.223 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31163-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=quicinc.com Received: from ny.mirrors.kernel.org (ny.mirrors.kernel.org. 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Fri, 19 Jan 2024 13:00:45 +0000 Received: from APBLRPPMTA01.qualcomm.com (APBLRPPMTA01.qualcomm.com [127.0.0.1]) by pps.reinject (8.17.1.5/8.17.1.5) with ESMTP id 40JD0jY1023853; Fri, 19 Jan 2024 13:00:45 GMT Received: from hu-sgudaval-hyd.qualcomm.com (hu-msarkar-hyd.qualcomm.com [10.213.111.194]) by APBLRPPMTA01.qualcomm.com (PPS) with ESMTP id 40JD0jEl023849; Fri, 19 Jan 2024 13:00:45 +0000 Received: by hu-sgudaval-hyd.qualcomm.com (Postfix, from userid 3891782) id 3D950273A; Fri, 19 Jan 2024 18:30:44 +0530 (+0530) From: Mrinmay Sarkar To: vkoul@kernel.org, jingoohan1@gmail.com, conor+dt@kernel.org, konrad.dybcio@linaro.org, manivannan.sadhasivam@linaro.org, robh+dt@kernel.org Cc: quic_shazhuss@quicinc.com, quic_nitegupt@quicinc.com, quic_ramkri@quicinc.com, quic_nayiluri@quicinc.com, dmitry.baryshkov@linaro.org, quic_krichai@quicinc.com, quic_vbadigan@quicinc.com, quic_parass@quicinc.com, quic_schintav@quicinc.com, quic_shijjose@quicinc.com, Mrinmay Sarkar , Gustavo Pimentel , Serge Semin , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , Kishon Vijay Abraham I , dmaengine@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, mhi@lists.linux.dev Subject: [PATCH v1 6/6] PCI: epf-mhi: Add flag to enable HDMA for SA8775P Date: Fri, 19 Jan 2024 18:30:22 +0530 Message-Id: <1705669223-5655-7-git-send-email-quic_msarkar@quicinc.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> References: <1705669223-5655-1-git-send-email-quic_msarkar@quicinc.com> X-QCInternal: smtphost X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: WWE7FCmYj8w85w0MqfhUdlV8VFvKiadI X-Proofpoint-ORIG-GUID: WWE7FCmYj8w85w0MqfhUdlV8VFvKiadI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.272,Aquarius:18.0.997,Hydra:6.0.619,FMLib:17.11.176.26 definitions=2024-01-19_07,2024-01-19_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 priorityscore=1501 mlxscore=0 bulkscore=0 phishscore=0 spamscore=0 adultscore=0 mlxlogscore=688 malwarescore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2311290000 definitions=main-2401190065 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788523983725284906 X-GMAIL-MSGID: 1788523983725284906 SA8775P supports HDMA as DMA engine so adding 'MHI_EPF_USE_DMA' flag to enable HDMA support. Signed-off-by: Mrinmay Sarkar Reviewed-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 2c54d80..570c1d1f 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -137,6 +137,7 @@ static const struct pci_epf_mhi_ep_info sa8775p_info = { .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, .msi_count = 32, .mru = 0x8000, + .flags = MHI_EPF_USE_DMA, }; struct pci_epf_mhi {