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Fri, 19 Jan 2024 03:35:07 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id a5-20020a92a305000000b0036062f40c51sm5347302ili.71.2024.01.19.03.35.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:35:06 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 1/5] RISC-V: Add stubs for sbi_console_putchar/getchar() Date: Fri, 19 Jan 2024 17:04:45 +0530 Message-Id: <20240119113449.492152-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119113449.492152-1-apatel@ventanamicro.com> References: <20240119113449.492152-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788518475124272743 X-GMAIL-MSGID: 1788518475124272743 The functions sbi_console_putchar() and sbi_console_getchar() are not defined when CONFIG_RISCV_SBI_V01 is disabled so let us add stub of these functions to avoid "#ifdef" on user side. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index b6f898c56940..e0a8eca32ba5 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -288,8 +288,13 @@ struct sbiret sbi_ecall(int ext, int fid, unsigned long arg0, unsigned long arg3, unsigned long arg4, unsigned long arg5); +#ifdef CONFIG_RISCV_SBI_V01 void sbi_console_putchar(int ch); int sbi_console_getchar(void); +#else +static inline void sbi_console_putchar(int ch) { } +static inline int sbi_console_getchar(void) { return -ENOENT; } +#endif long sbi_get_mvendorid(void); long sbi_get_marchid(void); long sbi_get_mimpid(void); From patchwork Fri Jan 19 11:34:46 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 189535 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp944861dyb; Fri, 19 Jan 2024 03:35:59 -0800 (PST) X-Google-Smtp-Source: AGHT+IERJfkKt6reUvXNSljT4GG9OLrmr3n2F0vZ6izF+O71Zv/fNfRbq758JGcDpCjYPQxWGPEE X-Received: by 2002:a4a:a802:0:b0:598:26a7:5591 with SMTP id o2-20020a4aa802000000b0059826a75591mr2229058oom.17.1705664158803; Fri, 19 Jan 2024 03:35:58 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705664158; cv=pass; d=google.com; s=arc-20160816; b=D++XWz+MOnEQaPGOwW7d7ObpBO2K7JDhVQeLsFobcaqOozKOiusWNzP4iTZnuZZSnF c1w82jKlDSwQPpzCfr05vtcWAg7mFjzkWaUbXXWTuKnsq0m3pZPWr9j9rSTKDpSLVrb2 CQ2a0BuGj/jUtE2ybivdGVrgkk+nWfYoxsfhSgtZwbDHQq/mkfB/s25ZDdx/XDmhC5vl jxbS0Lhhj6jVwefAgeVaDvdLfhI/yMdvLZ0XiQaGXlLBO28xDpK5bEDQXk3QJ+9bBBLc P98Omb9k6Z72Zyly10stwrk1JaPEitPfy/xoXJ9RZXHi2zCBRhxlHDLhrxJ5Yn+25buR I8vg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=HakN1bFuSJrmH5vBdRWtx03jEjEl7JQWSWUtuZHUeu4=; fh=sCaLDPmI3z3WfJgoG5Ri8nSrNxiyuF4F9Uj24RFqprM=; b=Z2y2O20AJjhaCKYnQM8z1XFbJzTspMPbZOmPGnEmcrWjpZshEnWcZ9PtM+pMGM1HWk w9c1y1fbCp7khB/XTWI47Lg8BLbPuRXeIKLS81Y79MfL9KNpyBBmrHoLcUnJTeFpaKJe ShLWswCulxRKEXbnpjiwqCEoh948i8qsMLLO+Z8HPaGyc9gamKrrLfGOKvWqPY8DNivF YaX+59VniemRb+QNGDxK3xGbKQ8s8zdrfuUptzkVgHO8le6oU6pKvqyf5jG47YPjmrl+ y8NRbQl1BgJG+dAi7noUR2RqAxfG/rfGtVx019Lu4iThEdMgB5qlahsFiN8ImhaPFown rZJA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=KQZxILTF; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-31101-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.48.161 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31101-ouuuleilei=gmail.com@vger.kernel.org" Received: from sy.mirrors.kernel.org (sy.mirrors.kernel.org. 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Fri, 19 Jan 2024 03:35:12 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id a5-20020a92a305000000b0036062f40c51sm5347302ili.71.2024.01.19.03.35.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:35:12 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 2/5] RISC-V: Add SBI debug console helper routines Date: Fri, 19 Jan 2024 17:04:46 +0530 Message-Id: <20240119113449.492152-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119113449.492152-1-apatel@ventanamicro.com> References: <20240119113449.492152-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788518501277740329 X-GMAIL-MSGID: 1788518501277740329 Let us provide SBI debug console helper routines which can be shared by serial/earlycon-riscv-sbi.c and hvc/hvc_riscv_sbi.c. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/include/asm/sbi.h | 5 +++ arch/riscv/kernel/sbi.c | 66 ++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h index e0a8eca32ba5..13594efb24bd 100644 --- a/arch/riscv/include/asm/sbi.h +++ b/arch/riscv/include/asm/sbi.h @@ -351,6 +351,11 @@ static inline unsigned long sbi_mk_version(unsigned long major, } int sbi_err_map_linux_errno(int err); + +extern bool sbi_debug_console_available; +ssize_t sbi_debug_console_write(const u8 *bytes, size_t num_bytes); +ssize_t sbi_debug_console_read(u8 *bytes, size_t num_bytes); + #else /* CONFIG_RISCV_SBI */ static inline int sbi_remote_fence_i(const struct cpumask *cpu_mask) { return -1; } static inline void sbi_init(void) {} diff --git a/arch/riscv/kernel/sbi.c b/arch/riscv/kernel/sbi.c index 5a62ed1da453..b06ad29f54b5 100644 --- a/arch/riscv/kernel/sbi.c +++ b/arch/riscv/kernel/sbi.c @@ -7,6 +7,7 @@ #include #include +#include #include #include #include @@ -571,6 +572,66 @@ long sbi_get_mimpid(void) } EXPORT_SYMBOL_GPL(sbi_get_mimpid); +bool sbi_debug_console_available; + +ssize_t sbi_debug_console_write(const u8 *bytes, size_t num_bytes) +{ + phys_addr_t base_addr; + struct sbiret ret; + + if (!sbi_debug_console_available) + return -EOPNOTSUPP; + + if (is_vmalloc_addr(bytes)) + base_addr = page_to_phys(vmalloc_to_page(bytes)) + + offset_in_page(bytes); + else + base_addr = __pa(bytes); + if (PAGE_SIZE < (offset_in_page(bytes) + num_bytes)) + num_bytes = PAGE_SIZE - offset_in_page(bytes); + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + num_bytes, lower_32_bits(base_addr), + upper_32_bits(base_addr), 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_WRITE, + num_bytes, base_addr, 0, 0, 0, 0); + + if (ret.error == SBI_ERR_FAILURE) + return -EIO; + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; +} + +ssize_t sbi_debug_console_read(u8 *bytes, size_t num_bytes) +{ + phys_addr_t base_addr; + struct sbiret ret; + + if (!sbi_debug_console_available) + return -EOPNOTSUPP; + + if (is_vmalloc_addr(bytes)) + base_addr = page_to_phys(vmalloc_to_page(bytes)) + + offset_in_page(bytes); + else + base_addr = __pa(bytes); + if (PAGE_SIZE < (offset_in_page(bytes) + num_bytes)) + num_bytes = PAGE_SIZE - offset_in_page(bytes); + + if (IS_ENABLED(CONFIG_32BIT)) + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + num_bytes, lower_32_bits(base_addr), + upper_32_bits(base_addr), 0, 0, 0); + else + ret = sbi_ecall(SBI_EXT_DBCN, SBI_EXT_DBCN_CONSOLE_READ, + num_bytes, base_addr, 0, 0, 0, 0); + + if (ret.error == SBI_ERR_FAILURE) + return -EIO; + return ret.error ? sbi_err_map_linux_errno(ret.error) : ret.value; +} + void __init sbi_init(void) { int ret; @@ -612,6 +673,11 @@ void __init sbi_init(void) sbi_srst_reboot_nb.priority = 192; register_restart_handler(&sbi_srst_reboot_nb); } + if ((sbi_spec_version >= sbi_mk_version(2, 0)) && + (sbi_probe_extension(SBI_EXT_DBCN) > 0)) { + pr_info("SBI DBCN extension detected\n"); + sbi_debug_console_available = true; + } } else { __sbi_set_timer = __sbi_set_timer_v01; __sbi_send_ipi = __sbi_send_ipi_v01; From patchwork Fri Jan 19 11:34:47 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 189536 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp944887dyb; Fri, 19 Jan 2024 03:36:03 -0800 (PST) X-Google-Smtp-Source: AGHT+IEgUxCiXePYYTBnS2Fu9xb/GK/Vq7fqgjqi6NoolaexkMTZNWw3YWwkc0e+JR/LmDU8uhNx X-Received: by 2002:a17:903:1cb:b0:1d4:59ab:36a0 with SMTP id e11-20020a17090301cb00b001d459ab36a0mr2627885plh.99.1705664162755; Fri, 19 Jan 2024 03:36:02 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705664162; cv=pass; d=google.com; s=arc-20160816; b=M/dh5MZjW/6hjnsfbbRmGfNNwu0Ceia7x9kLsgUxhJIu9GPSYkI5WYKpcseve+sJ2x 2ABwL5tn4P/zt2HwS7znMG4go7pjiShzXrAdBuflZBffOnrshpXvB7Z+riORoR+TalEG o/KVRGgkqUzv1ZeY/QFvMODlvQqPSB0/+DK7muWIp7r+zyE5LXzw+lO2hMvWydOCoxh2 GS4JFUeY3oMc2kOXYXtYCwL0Vcmoq5pUjmXS+bPsXKYNQ/fPOCdZE6YH/l5zTCd8uN9/ ZzDPvuju78mmZqL1ojJCnhL7WCXigxfOYblBdeY6Y/qbJfcKax60sQi8GGdw+yMb945T WNYg== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=gZs1DnoR+BqoPfBEx3sAKhKPyFXu5PFqqMfZZxzp+sc=; fh=sCaLDPmI3z3WfJgoG5Ri8nSrNxiyuF4F9Uj24RFqprM=; b=rPNCXw6W7CV5XXllZCXqFFIcwB+7/0k0/A1WYCYleUKFMRUdbXIlNBbR64ZSVvFMdk Nvh8H5+qjtwmly3pUrQB5bGTQjbyHrsvWWMUcrCohiQhbnCyjdmYsAPPIZn5B/qNPm74 074dnclQujKkOPFa2QhpH9KnMXpvZiKGIKDrPUxA+UZJDpuso7xzgkWKsuwF+antzHmw S22c62LMphp81YAvEHtCKVTx3UWBHzDFNtT2mRhojzVw2OQBcVH2Y+S11J5wB4aBty/8 P2Ex6mrMnl4iSagCfafyCJgI2p0DBTUZClDVI+Aqsy30EYrazSD0ikb9+HvNQFx6TvGY vwmQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=nwf1jBRG; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-31102-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31102-ouuuleilei=gmail.com@vger.kernel.org" Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 19 Jan 2024 03:35:18 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id a5-20020a92a305000000b0036062f40c51sm5347302ili.71.2024.01.19.03.35.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:35:18 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 3/5] tty/serial: Add RISC-V SBI debug console based earlycon Date: Fri, 19 Jan 2024 17:04:47 +0530 Message-Id: <20240119113449.492152-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119113449.492152-1-apatel@ventanamicro.com> References: <20240119113449.492152-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788518504833362682 X-GMAIL-MSGID: 1788518504833362682 We extend the existing RISC-V SBI earlycon support to use the new RISC-V SBI debug console extension. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Acked-by: Greg Kroah-Hartman --- drivers/tty/serial/Kconfig | 2 +- drivers/tty/serial/earlycon-riscv-sbi.c | 27 ++++++++++++++++++++++--- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/Kconfig b/drivers/tty/serial/Kconfig index 8b1f5756002f..ffcf4882b25f 100644 --- a/drivers/tty/serial/Kconfig +++ b/drivers/tty/serial/Kconfig @@ -87,7 +87,7 @@ config SERIAL_EARLYCON_SEMIHOST config SERIAL_EARLYCON_RISCV_SBI bool "Early console using RISC-V SBI" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select SERIAL_CORE select SERIAL_CORE_CONSOLE select SERIAL_EARLYCON diff --git a/drivers/tty/serial/earlycon-riscv-sbi.c b/drivers/tty/serial/earlycon-riscv-sbi.c index 27afb0b74ea7..0162155f0c83 100644 --- a/drivers/tty/serial/earlycon-riscv-sbi.c +++ b/drivers/tty/serial/earlycon-riscv-sbi.c @@ -15,17 +15,38 @@ static void sbi_putc(struct uart_port *port, unsigned char c) sbi_console_putchar(c); } -static void sbi_console_write(struct console *con, - const char *s, unsigned n) +static void sbi_0_1_console_write(struct console *con, + const char *s, unsigned int n) { struct earlycon_device *dev = con->data; uart_console_write(&dev->port, s, n, sbi_putc); } +static void sbi_dbcn_console_write(struct console *con, + const char *s, unsigned int n) +{ + int ret; + + while (n) { + ret = sbi_debug_console_write(s, n); + if (ret < 0) + break; + + s += ret; + n -= ret; + } +} + static int __init early_sbi_setup(struct earlycon_device *device, const char *opt) { - device->con->write = sbi_console_write; + if (sbi_debug_console_available) + device->con->write = sbi_dbcn_console_write; + else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) + device->con->write = sbi_0_1_console_write; + else + return -ENODEV; + return 0; } EARLYCON_DECLARE(sbi, early_sbi_setup); From patchwork Fri Jan 19 11:34:48 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 189538 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp945202dyb; Fri, 19 Jan 2024 03:36:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IHorMoXwZux/up3vPsNICf3p4El0QS46a2t+dtHc2swIw9ruH4ACKDT0xyK+C3KvwpKfjmb X-Received: by 2002:a05:6a00:2396:b0:6db:b35b:7367 with SMTP id f22-20020a056a00239600b006dbb35b7367mr1391011pfc.39.1705664203986; Fri, 19 Jan 2024 03:36:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705664203; cv=pass; d=google.com; s=arc-20160816; b=UFIX2rPQPeRhDx4ARJ2d4CbOFjCsMI0YLlNGzY1D1ww6uES9gLlU+6n7W7uAwiY4u4 xTkyZxrdUUTK5nkVjZ1un05n+0/0uWPyhqpxcq8gVgq0gpLvjBLsMqrb+FIrsW7EB/Be itVq2U8/yfFoyLOiO3JkwWxo4V8RoYAfWSQdYc8Mu8PJtqsjOuO4fakAjkEgUYFSMPH5 efIKuAFI4SABj66L5+7lgO2jzkcJgouevajklnSQBPyaiXuJp5X74yXZNDGrKQMQ5wxh Y2rcTF01Z42qxj7XJ+K7IQ870c4pXuuCVpP3BazlYYrC/mjt0SmDUXOGsqQLgIA8wyIT DTJw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=JB3Vj18FKp8kzrC7fP7ko88EXDexTWBrSVK1Kjp8q3Q=; fh=AB671bsq6wR7DceXjf9pC9mFDEFzybXlmQ7x1GwQJjg=; b=MeGl00qd0KDziFL9enxMjAYDItAZhu5fqkiuZ9ZYpzw6iZM4MreJcQFX3T2BGbx4rk agwNuu+H11CqnS4DlTNM2U+wx0o4UfSWhjrkFDD74uDopZYzr9gMmHRf7qRF3D4koPSc JwaSNNIylmOtvkigVjiSY2Kqr8ebknJIXUsS64j1zbaMGBuFAHD6A9G1CR1dG6057jxf fGfK4l/A0jchWg2nrv6SDAGZy1pFaUk28UxQjxhPU08X/EANPhModNRiAaA6kV55Wcq9 4oQHLuw17L5HlGLafVU+cae+gr9rhSqkJNUSiecM9lYYmRujq1pWJBDDrccuuNLZNtXk 4kgA== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=aCxx5Jw2; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-31103-ouuuleilei=gmail.com@vger.kernel.org designates 139.178.88.99 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31103-ouuuleilei=gmail.com@vger.kernel.org" Received: from sv.mirrors.kernel.org (sv.mirrors.kernel.org. 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Fri, 19 Jan 2024 03:35:24 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id a5-20020a92a305000000b0036062f40c51sm5347302ili.71.2024.01.19.03.35.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:35:23 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Atish Patra , Anup Patel Subject: [PATCH v6 4/5] tty: Add SBI debug console support to HVC SBI driver Date: Fri, 19 Jan 2024 17:04:48 +0530 Message-Id: <20240119113449.492152-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119113449.492152-1-apatel@ventanamicro.com> References: <20240119113449.492152-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788518548147004959 X-GMAIL-MSGID: 1788518548147004959 From: Atish Patra RISC-V SBI specification supports advanced debug console support via SBI DBCN extension. Extend the HVC SBI driver to support it. Signed-off-by: Atish Patra Signed-off-by: Anup Patel Reviewed-by: Andrew Jones Acked-by: Greg Kroah-Hartman --- drivers/tty/hvc/Kconfig | 2 +- drivers/tty/hvc/hvc_riscv_sbi.c | 37 ++++++++++++++++++++++++++------- 2 files changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/tty/hvc/Kconfig b/drivers/tty/hvc/Kconfig index 4f9264d005c0..6e05c5c7bca1 100644 --- a/drivers/tty/hvc/Kconfig +++ b/drivers/tty/hvc/Kconfig @@ -108,7 +108,7 @@ config HVC_DCC_SERIALIZE_SMP config HVC_RISCV_SBI bool "RISC-V SBI console support" - depends on RISCV_SBI_V01 + depends on RISCV_SBI select HVC_DRIVER help This enables support for console output via RISC-V SBI calls, which diff --git a/drivers/tty/hvc/hvc_riscv_sbi.c b/drivers/tty/hvc/hvc_riscv_sbi.c index a72591279f86..cede8a572594 100644 --- a/drivers/tty/hvc/hvc_riscv_sbi.c +++ b/drivers/tty/hvc/hvc_riscv_sbi.c @@ -40,21 +40,44 @@ static ssize_t hvc_sbi_tty_get(uint32_t vtermno, u8 *buf, size_t count) return i; } -static const struct hv_ops hvc_sbi_ops = { +static const struct hv_ops hvc_sbi_v01_ops = { .get_chars = hvc_sbi_tty_get, .put_chars = hvc_sbi_tty_put, }; -static int __init hvc_sbi_init(void) +static ssize_t hvc_sbi_dbcn_tty_put(uint32_t vtermno, const u8 *buf, size_t count) { - return PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_ops, 16)); + return sbi_debug_console_write(buf, count); } -device_initcall(hvc_sbi_init); -static int __init hvc_sbi_console_init(void) +static ssize_t hvc_sbi_dbcn_tty_get(uint32_t vtermno, u8 *buf, size_t count) { - hvc_instantiate(0, 0, &hvc_sbi_ops); + return sbi_debug_console_read(buf, count); +} + +static const struct hv_ops hvc_sbi_dbcn_ops = { + .put_chars = hvc_sbi_dbcn_tty_put, + .get_chars = hvc_sbi_dbcn_tty_get, +}; + +static int __init hvc_sbi_init(void) +{ + int err; + + if (sbi_debug_console_available) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_dbcn_ops, 256)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_dbcn_ops); + } else if (IS_ENABLED(CONFIG_RISCV_SBI_V01)) { + err = PTR_ERR_OR_ZERO(hvc_alloc(0, 0, &hvc_sbi_v01_ops, 256)); + if (err) + return err; + hvc_instantiate(0, 0, &hvc_sbi_v01_ops); + } else { + return -ENODEV; + } return 0; } -console_initcall(hvc_sbi_console_init); +device_initcall(hvc_sbi_init); From patchwork Fri Jan 19 11:34:49 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 189537 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp945148dyb; Fri, 19 Jan 2024 03:36:38 -0800 (PST) X-Google-Smtp-Source: AGHT+IEj2CgoxhiRu/CiizOsCBVz0afDVALZ7ZKM47Wv2Xm1iCmXYY+x4l1WMbI58lg7TIPr4F8s X-Received: by 2002:a17:906:244f:b0:a28:9621:40b4 with SMTP id a15-20020a170906244f00b00a28962140b4mr1374276ejb.141.1705664197785; Fri, 19 Jan 2024 03:36:37 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705664197; cv=pass; d=google.com; s=arc-20160816; b=qA+lsTqZx44eYloPGxK14MBrq5x5pFkcTgwqEP6I1ZcUInxKj7C7oQidj65HG6f4TP qM7KLND1WEHGFED7kakf2iWFRdySQwJfdKQBMc2QVt5N5I8lkBclG+hlyN7P80G9E3OR FBwMfBpzwBplGUrCgIwgCumYE7gWOeyYsjE3pwGnziyF+n4pTe8SJwftjdvYLZ9OYkaL AbRU0AQTk4qYqZ6FI3jELkVyA73PzqyUUSFutMhY6spP4by6b6w81R4kD9rIASXVGZKv Wshke/ZsuVaR7hfC7mZv9DsgyMJ9Y4ywaviuh61xyzgVyqUAw7hhxgoG83O/6myYCCVq ITvA== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=content-transfer-encoding:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:references:in-reply-to:message-id :date:subject:cc:to:from:dkim-signature; bh=9bsP20n9g/LbbgzyTFqfc2H9X3ZVkLkHm6HS5kmWZpw=; fh=sCaLDPmI3z3WfJgoG5Ri8nSrNxiyuF4F9Uj24RFqprM=; b=AgdV/yrAGDyohZ7px8H6PzcpYI/aDB2jT1odxk+PkztPLJXdKZM3OzrZODVDGjIbGd nkR4W8PepDR+xyWsz+9J0rOdKfMA5sH3lBf6RQUVDpzybkaMGPu3s0vLnuToxmhJTaR4 ZPCBuHHYWZ704NGamgMoNHQcCPW73P7L2IzPzIEQQO+zZswkJam+elB375sYdbYwQc1f H0wThOiv9Q14UhsLZho6HyEvIgKBNCk+vBz/5nYrwa6+5Y1oW2iLtaCWw4igWLhjYUE1 u3lg5yUzpYmnc0DrIGz1KL4UeDBPj5DPk5ms9Ua37Yq17mpS0qTXHLH4n/7CC32u1/9+ EkmQ== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@ventanamicro.com header.s=google header.b=mbi9StrE; arc=pass (i=1 spf=pass spfdomain=ventanamicro.com dkim=pass dkdomain=ventanamicro.com); spf=pass (google.com: domain of linux-kernel+bounces-31104-ouuuleilei=gmail.com@vger.kernel.org designates 2604:1380:4601:e00::3 as permitted sender) smtp.mailfrom="linux-kernel+bounces-31104-ouuuleilei=gmail.com@vger.kernel.org" Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 19 Jan 2024 03:35:29 -0800 (PST) Received: from anup-ubuntu-vm.localdomain ([103.97.165.210]) by smtp.gmail.com with ESMTPSA id a5-20020a92a305000000b0036062f40c51sm5347302ili.71.2024.01.19.03.35.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 03:35:29 -0800 (PST) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Greg Kroah-Hartman , Jiri Slaby Cc: Conor Dooley , Andrew Jones , linux-riscv@lists.infradead.org, linux-serial@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-kernel@vger.kernel.org, Anup Patel Subject: [PATCH v6 5/5] RISC-V: Enable SBI based earlycon support Date: Fri, 19 Jan 2024 17:04:49 +0530 Message-Id: <20240119113449.492152-6-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20240119113449.492152-1-apatel@ventanamicro.com> References: <20240119113449.492152-1-apatel@ventanamicro.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788518541990674207 X-GMAIL-MSGID: 1788518541990674207 Let us enable SBI based earlycon support in defconfig for both RV32 and RV64 so that "earlycon=sbi" can be used again. Signed-off-by: Anup Patel Reviewed-by: Andrew Jones --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 905881282a7c..eaf34e871e30 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -149,6 +149,7 @@ CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y CONFIG_SERIAL_SH_SCI=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y