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Fri, 19 Jan 2024 00:19:28 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id g6-20020a05600c4ec600b0040e6b0a1bc1sm21401815wmq.12.2024.01.19.00.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 00:19:28 -0800 (PST) Date: Fri, 19 Jan 2024 11:19:24 +0300 From: Dan Carpenter To: Niklas Cassel Cc: Jingoo Han , Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v2 1/2] PCI: dwc: Fix a 64bit bug in dw_pcie_ep_raise_msix_irq() Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788506162673740682 X-GMAIL-MSGID: 1788506162673740682 The "msg_addr" variable is u64. However, the "aligned_offset" is an unsigned int. This means that when the code does: msg_addr &= ~aligned_offset; it will unintentionally zero out the high 32 bits. Declare "aligned_offset" as a u64 to address this bug. Fixes: 2217fffcd63f ("PCI: dwc: endpoint: Fix dw_pcie_ep_raise_msix_irq() alignment support") Signed-off-by: Dan Carpenter --- v2: fix a typo in the commit message drivers/pci/controller/dwc/pcie-designware-ep.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 5befed2dc02b..2b6607c23541 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -525,7 +525,7 @@ int dw_pcie_ep_raise_msix_irq(struct dw_pcie_ep *ep, u8 func_no, struct dw_pcie_ep_func *ep_func; struct pci_epc *epc = ep->epc; u32 reg, msg_data, vec_ctrl; - unsigned int aligned_offset; + u64 aligned_offset; u32 tbl_offset; u64 msg_addr; int ret; From patchwork Fri Jan 19 08:24:18 2024 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dan Carpenter X-Patchwork-Id: 189436 Return-Path: Delivered-To: ouuuleilei@gmail.com Received: by 2002:a05:7301:2bc4:b0:101:a8e8:374 with SMTP id hx4csp866357dyb; Fri, 19 Jan 2024 00:24:44 -0800 (PST) X-Google-Smtp-Source: AGHT+IEuWtfbbyfEhjBpULEoMoFKpJGHvS1MFKVuQp4NgqZjOK/xxT5S2TYIxP9/Y4F3Og8ynV9e X-Received: by 2002:a17:907:c085:b0:a2c:96a1:99ed with SMTP id st5-20020a170907c08500b00a2c96a199edmr771089ejc.11.1705652683951; Fri, 19 Jan 2024 00:24:43 -0800 (PST) ARC-Seal: i=2; a=rsa-sha256; t=1705652683; cv=pass; d=google.com; s=arc-20160816; b=g9mmHsyumwGs6RFMeepYkFuA+whLmP3v1Qz7FLy2pGwy+kjTAWoki67fkxUhDBDSUb IqQXulWi56IlgZgHwc3KoOar9prJDPeK9TJA1fRhGCdQJOd78UE5ZbrQqzloH++eR2W4 MvXzA7Rxbdp3wj8sN+bwg8kiB0eLIT9N7OoOHJd9smx4bT8uHn+i2YZgT+nnBSMnyWSP F36Oc5A1icdItIWoUE+N+ufW7ylgUzOmL1VyypHSe+9oi7TCvxMVwFRDGcX2VKRAvvKG uEYf/DIMjaPCd2ZxaNVlETdbvm+79u3YRbKTHxV8veXhavqbHPwHEqgIfml3TeyP7vzZ JiZw== ARC-Message-Signature: i=2; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=in-reply-to:content-disposition:mime-version:list-unsubscribe :list-subscribe:list-id:precedence:message-id:subject:cc:to:from :date:dkim-signature; bh=JWMsaxBTQZjTZlrkYTLuJn10R3NfYJxlM8FKkmLstP8=; fh=eXzY3uCod0uoUhoSFH26hwNyKgz3imtHgoKrWTV58bE=; b=HNiu3cM4n0yG1uifLazFB3CROwKX6lJoxxE4iqGihEz4Z9jOuLQnT33D9mPsKopaOY paT3WV/DY5j20mMsgpUXoTz4DW013UvLW7ugiJwYCuxJ8bNXqtlJanwKf2TRdlL/0D7k qvJ/06x0Pb+ysaw+GhJhqoZbld5kQn+7PKW2Rs9WFlHTUoaIbLyu6x+KnKt9068mJ4AK JIMMdKnUWbX/QqXYhzMRXjQKRTA6+F4hkweedk2dAr7xvEo4cATo0ff4r4CGRAlAGu7d q++k7YvAZOfXQqmgEbD45bNlx4bReb+BFRiXG43/49nedQh9MkOBwnrm/4OEJ6B0+Azc uHhg== ARC-Authentication-Results: i=2; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HUmJMz+D; arc=pass (i=1 spf=pass spfdomain=linaro.org dkim=pass dkdomain=linaro.org dmarc=pass fromdomain=linaro.org); spf=pass (google.com: domain of linux-kernel+bounces-30900-ouuuleilei=gmail.com@vger.kernel.org designates 147.75.80.249 as permitted sender) smtp.mailfrom="linux-kernel+bounces-30900-ouuuleilei=gmail.com@vger.kernel.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from am.mirrors.kernel.org (am.mirrors.kernel.org. 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Fri, 19 Jan 2024 00:24:22 -0800 (PST) Received: from localhost ([102.140.209.237]) by smtp.gmail.com with ESMTPSA id jg1-20020a05600ca00100b0040d4e1393dcsm31685700wmb.20.2024.01.19.00.24.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jan 2024 00:24:22 -0800 (PST) Date: Fri, 19 Jan 2024 11:24:18 +0300 From: Dan Carpenter To: Jingoo Han Cc: Gustavo Pimentel , Manivannan Sadhasivam , Lorenzo Pieralisi , Krzysztof =?utf-8?q?Wilczy=C5=84?= =?utf-8?q?ski?= , Rob Herring , Bjorn Helgaas , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, kernel-janitors@vger.kernel.org Subject: [PATCH v2 2/2] PCI: dwc: Cleanup in dw_pcie_ep_raise_msi_irq() Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-Mailer: git-send-email haha only kidding X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: 1788506468731118668 X-GMAIL-MSGID: 1788506468731118668 The alignment code in dw_pcie_ep_raise_msix_irq() and dw_pcie_ep_raise_msi_irq() is quite similar. I recently update the code in the former, so tweak the latter to match as well for consistency sake. Signed-off-by: Dan Carpenter --- v2: Add this new patch I wrote two versions of this, one where both patches were folded together and this one where the style tweaks are separated out into their own patch. This is the better version. drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index 2b6607c23541..ccfc21cd0bb0 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -456,8 +456,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, u32 msg_addr_lower, msg_addr_upper, reg; struct dw_pcie_ep_func *ep_func; struct pci_epc *epc = ep->epc; - unsigned int aligned_offset; u16 msg_ctrl, msg_data; + u64 aligned_offset; bool has_upper; u64 msg_addr; int ret; @@ -483,8 +483,8 @@ int dw_pcie_ep_raise_msi_irq(struct dw_pcie_ep *ep, u8 func_no, msg_data = dw_pcie_ep_readw_dbi(ep, func_no, reg); } aligned_offset = msg_addr_lower & (epc->mem->window.page_size - 1); - msg_addr = ((u64)msg_addr_upper) << 32 | - (msg_addr_lower & ~aligned_offset); + msg_addr = ((u64)msg_addr_upper) << 32 | msg_addr_lower; + msg_addr &= ~aligned_offset; ret = dw_pcie_ep_map_addr(epc, func_no, 0, ep->msi_mem_phys, msg_addr, epc->mem->window.page_size); if (ret)